With Heterojunction Interface Channel Or Gate, E.g., Hfet, Higfet, Sisfet, Hjfet, Hemt (epo) Patents (Class 257/E21.403)
  • Patent number: 11984486
    Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
  • Patent number: 11967641
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third nitride regions, and first and second insulating films. The first nitride region includes Alx1Ga1?x1N, and includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The first nitride region includes first to fifth partial regions. The second nitride region includes Alx2Ga1?x2N, and sixth and seventh partial regions. At least a portion of the third electrode is between the sixth and seventh partial regions. The first insulating film includes silicon and oxygen and includes first and second insulating regions. The third nitride region includes Alx3Ga1?x3N, and first to seventh portions. The second insulating film includes silicon and oxygen and includes third to seventh insulating regions.
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: April 23, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Daimotsu Kato, Yosuke Kajiwara, Akira Mukai, Aya Shindome, Hiroshi Ono, Masahiko Kuraguchi
  • Patent number: 11967619
    Abstract: Laterally-gated transistors and lateral Schottky diodes are disclosed. The FET includes a substrate, source and drain electrodes, channel, a gate electrode structure, and a dielectric layer. The gate electrode structure includes an electrode in contact with the channel and a lateral field plate adjacent to the electrode. The dielectric layer is disposed between the lateral field plate and the channel. The lateral field plate contacts the dielectric layer and to modulate an electric field proximal to the gate electrode proximal to the drain or source electrodes. Also disclosed is a gate electrode structure with lateral field plates symmetrically disposed relative to the gate electrode. Also disclosed in a substrate with dielectric structures buried in the substrate remote from the gate electrode structure. A lateral Schottky diode having an anode structure includes an anode (A), cathodes (C) and lateral field plates located between the anode and the cathodes.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: April 23, 2024
    Assignee: TELEDYNE SCIENTIFIC & IMAGING, LLC
    Inventors: Keisuke Shinohara, Casey King, Eric Regan, Miguel Urteaga
  • Patent number: 11955397
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 9, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
  • Patent number: 11948801
    Abstract: A method of manufacturing a vertical FET device includes providing a semiconductor substrate structure including a marker layer; forming a hardmask layer coupled to the semiconductor substrate structure, wherein the hardmask layer comprises a set of openings operable to expose an upper surface portion of the semiconductor substrate structure; etching the upper surface portion of the semiconductor substrate structure to form a plurality of fins; etching at least a portion of the marker layer; detecting the etching of the at least a portion of the marker layer; epitaxially growing a semiconductor layer in recess regions disposed between adjacent fins of the plurality of fins; forming a source metal layer on each of the plurality of fins; and forming a gate metal layer coupled to the semiconductor layer.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: April 2, 2024
    Assignee: Nexgen Power Systems, Inc.
    Inventors: Wayne Chen, Andrew P. Edwards, Clifford Drowley, Subhash Srinivas Pidaparthi
  • Patent number: 11929407
    Abstract: A method of fabricating a HEMT includes the following steps. A substrate having a group III-V channel layer, a group III-V barrier layer, a group III-V gate layer, and a gate etch stop layer disposed thereon is provided. A passivation layer is formed to cover the group III-V barrier layer and the gate etch stop layer. A gate contact hole and at least one source/drain contact hole are formed in the passivation layer, where the gate contact hole exposes the gate etch stop layer, and the at least one source/drain contact hole exposes the group III-V channel layer. In addition, a conductive layer is conformally disposed on a top surface of the passivation layer and in the gate contact hole and the at least one source/drain contact hole.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: March 12, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ting-En Hsieh, Yu-Chieh Chou, Yung-Fong Lin
  • Patent number: 11916138
    Abstract: A sacrificial substrate wafer is provided. A low resistivity etch stop layer is formed on or in the top surface of the wafer. The etch stop layer may be a highly doped, p+ type epitaxially grown layer, or an implanted p+ type boron layer, or an epitaxially grown p+ type SiGe layer. Various epitaxial layers, such as an n? type drift layer, and doped regions are then formed over the etch stop layer to form a vertical power device. The starting wafer is then removed by a combination of mechanical grinding/polishing to leave a thinner layer of the starting wafer. A chemical or plasma etch is then used to remove the remainder of the starting wafer, using the etch stop layer to automatically stop the etching. A bottom metal electrode is then formed on the etch stop layer. The etch stop layer injects hole carriers into the drift layer.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: February 27, 2024
    Assignee: PAKAL TECHNOLOGIES, INC
    Inventors: Paul M Moore, Vladimir Rodov, Richard A Blanchard
  • Patent number: 11862722
    Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a barrier layer, a third nitride semiconductor layer and a gate structure. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The barrier layer is disposed on the second nitride semiconductor layer and has a bandgap greater than that of the second nitride semiconductor layer. The third nitride semiconductor layer is doped with impurity and disposed on the barrier layer. The gate structure is disposed on the third nitride semiconductor layer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: January 2, 2024
    Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
    Inventors: Chao Yang, Chunhua Zhou, Qiyue Zhao
  • Patent number: 11855198
    Abstract: A multi-gate HEMT includes at least two gates, with at least one recessed the same depth or at a deeper depth in a barrier layer than at least one other gate. Recessing a gate decreases the thickness of the barrier layer beneath the gate, reducing a density of high mobility carriers in a two-dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of a barrier layer and a buffer layer below the recessed gate. The recessed gate can increase gate control of the 2DEG conductive channel. The multi-gate HEMT has at least one gate recessed the same depth or a deeper depth into the buffer layer than another gate, which forms at least two different turn-on voltages for different gates. This can achieve improvement of transconductance linearity and a positive shift of the threshold voltage.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: December 26, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Chenjie Tang, Ye Lu, Peijie Feng, Junjing Bao
  • Patent number: 11843043
    Abstract: A method fabricating a GaN based sensor including: forming a gate dielectric layer over a GaN hetero-structure including a GaN layer formed over a substrate and a first barrier layer formed over the GaN layer; forming a first mask over the gate dielectric layer; etching the gate dielectric layer and the first barrier layer through the first mask, thereby forming source and drain contact openings; removing the first mask; forming a metal layer over the gate dielectric layer, wherein the metal layer extends into the source and drain contact openings; forming a second mask over the metal layer; etching the metal layer, the gate dielectric layer and the GaN heterostructure through the second mask, wherein a region of the GaN heterostructure is exposed; and thermally activating the metal layer in the source and drain contact openings. The gate dielectric may exhibit a sloped profile, and dielectric spacers may be formed.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: December 12, 2023
    Assignee: Tower Semiconductor Ltd.
    Inventors: Ruth Shima-Edelstein, Ronen Shaul, Roy Strul, Anatoly Sergienko, Liz Poliak, Ido Gilad, Alex Sirkis, Yakov Roizin
  • Patent number: 11791151
    Abstract: A process of preparing a wafer having a diameter of two inches or more, at least a surface of the wafer being formed from a group III nitride crystal, including preparing an alkaline or acidic etching liquid containing a peroxodisulfate ion as an oxidizing agent that accepts an electron, accommodating the wafer such that the surface of the wafer is immersed in the etching liquid such that the surface of the wafer is parallel with a surface of the etching liquid; and radiating light from the surface side of the etching liquid onto the surface of the wafer without agitating the etching liquid. First and second etching areas disposed at an interval from each other are defined on the surface of the wafer. In the process of radiating the light onto the surface of the wafer, the light is radiated perpendicularly onto surfaces of the first and second etching areas.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: October 17, 2023
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Fumimasa Hirikiri
  • Patent number: 11777023
    Abstract: A semiconductor device includes a substrate, a first GaN-based high-electron-mobility transistor (HEMT), a second GaN-based HEMT, a first interconnection, and a second interconnection is provided. The substrate has a plurality of first-type doped semiconductor regions and second-type doped semiconductor regions. The first GaN-based HEMT is disposed over the substrate to cover a first region on the first-type doped semiconductor regions and the second-type doped semiconductor regions in the substrate. The second GaN-based HEMT is disposed over the substrate to cover a second region. The first region is different from the second region. The first interconnection is disposed over and electrically connected to the substrate, forming a first interface. The second interconnection is disposed over and electrically connected to the substrate, forming a second interface. The first interface is separated from the second interface by at least two heterojunctions formed in the substrate.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: October 3, 2023
    Assignee: Innoscience (Suzhou) Technology Co., Ltd.
    Inventors: Weixing Du, Jheng-Sheng You
  • Patent number: 11769824
    Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: September 26, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Dong Seup Lee, Jungwoo Joh, Pinghai Hao, Sameer Pendharkar
  • Patent number: 11769799
    Abstract: The present invention provides a patterned silicon substrate-silicon germanium thin film composite structure comprising a silicon substrate having a patterned structure, a silicon germanium buffer layer positioned on the silicon substrate, a silicon germanium/silicon superlattice layer positioned on the silicon germanium buffer layer and a silicon germanium thin film layer positioned on the silicon germanium/silicon superlattice layer, wherein the silicon germanium/silicon superlattice layer comprises silicon germanium layers and silicon layers which are grown alternately. The present invention also provides a preparation method of the patterned silicon substrate-silicon germanium thin film composite structure of the present invention. The present invention also provides an application of the patterned silicon substrate-silicon germanium thin film composite structure of the present invention in strained silicon devices.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: September 26, 2023
    Assignee: Institute of Physics, Chinese Academy of Sciences
    Inventors: Jianjun Zhang, Jieyin Zhang
  • Patent number: 11769826
    Abstract: A semiconductor device includes a channel layer, a barrier layer, source contact and a drain contact, a doped group III-V layer, and a gate electrode. The barrier layer is positioned above the channel layer. The source contact and the drain contact are positioned above the barrier layer. The doped group III-V layer is positioned above the barrier layer and between the first drain contact and the first source contact. The first doped group III-V layer has a first non-vertical sidewall and a second non-vertical sidewall. The gate electrode is positioned above the doped group III-V layer and has a third non-vertical sidewall and a fourth non-vertical sidewall. A horizontal distance from the first non-vertical sidewall to the third non-vertical sidewall is different than a horizontal distance from the second non-vertical sidewall to the fourth non-vertical sidewall.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: September 26, 2023
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Hang Liao, Qiyue Zhao, Chang An Li, Chao Wang, Chunhua Zhou, King Yuen Wong
  • Patent number: 11764271
    Abstract: A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer; and forming a tri-layer gate having a gate foot in the first opening, the gate foot having a first width, a gate neck extending from the gate foot and extending for a length over the dielectric passivation layer on both sides of the first opening, the gate neck having a second width wider than the first width of the gate foot, and a gate head extending from the gate neck, the gate head having a third width wider than the second width of the gate neck.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: September 19, 2023
    Assignee: HRL LABORATORIES, LLC
    Inventors: Joel C. Wong, Jeong-Sun Moon, Robert M. Grabar, Michael T. Antcliffe
  • Patent number: 11715792
    Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Hsiang Wang, Chun Lin Tsai, Jiun-Lei Jerry Yu, Po-Chih Chen, Chia-Ling Yeh, Ching Yu Chen
  • Patent number: 11699723
    Abstract: An N-polar III-N high-electron mobility transistor device can include a III-N channel layer over an N-face of a III-N backbarrier, wherein a compositional difference between the channel layer and the backbarrier causes a 2DEG channel to be induced in the III-N channel layer adjacent to the interface between the III-N channel layer and the backbarrier. The device can further include a p-type III-N layer over the III-N channel layer and a thick III-N cap layer over the p-type III-N layer. The III-N cap layer can cause an increase in the charge density of the 2DEG channel directly below the cap layer, and the p-type III-N layer can serve to prevent a parasitic 2DEG from forming in the III-N cap layer.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: July 11, 2023
    Assignee: MONDE Wireless Inc.
    Inventor: Brian Romanczyk
  • Patent number: 11670709
    Abstract: Disclosed herein are IC structures, packages, and device assemblies with III-N transistors that include additional materials, referred to herein as “stressor materials,” which may be selectively provided over portions of polarization materials to locally increase or decrease the strain in the polarization material. Providing a compressive stressor material may decrease the tensile stress imposed by the polarization material on the underlying portion of the III-N semiconductor material, thereby decreasing the two-dimensional electron gas (2DEG) and increasing a threshold voltage of a transistor. On the other hand, providing a tensile stressor material may increase the tensile stress imposed by the polarization material, thereby increasing the 2DEG and decreasing the threshold voltage. Providing suitable stressor materials enables easier and more accurate control of threshold voltage compared to only relying on polarization material recess.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 6, 2023
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Nidhi Nidhi, Rahul Ramaswamy, Paul B. Fischer, Walid M. Hafez, Johann Christian Rode
  • Patent number: 11664277
    Abstract: According to claim 1, the invention relates to a method for providing at least one solid-body layer (4). The solid-body layer (4) is separated from a solid body (1).
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: May 30, 2023
    Assignee: Siltectra GmbH
    Inventors: Ralf Rieske, Marko Swoboda, Jan Richter
  • Patent number: 11658242
    Abstract: Some embodiments include an integrated assembly having a semiconductor material with a more-doped region adjacent to a less-doped region. A two-dimensional material is between the more-doped region and a portion of the less-doped region. Some embodiments include an integrated assembly which contains a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, and a two-dimensional material between the channel region and the first source/drain region.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Chandra Mouli, Haitao Liu
  • Patent number: 11646351
    Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: May 9, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Johnatan A. Kantarovsky, Mark D. Levy, Jeonghyun Hwang, Siva P. Adusumilli, Ajay Raman
  • Patent number: 11588096
    Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: February 21, 2023
    Assignee: The Regents of the University of California
    Inventors: Yuuki Enatsu, Chirag Gupta, Stacia Keller, Umesh K. Mishra, Anchal Agarwal
  • Patent number: 11557666
    Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.
    Type: Grant
    Filed: November 22, 2020
    Date of Patent: January 17, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 11545567
    Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: January 3, 2023
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Chih-Yen Chen
  • Patent number: 11476154
    Abstract: A field effect transistor, comprising a gate contact and gate metal forming a vertical structure, such vertical structure having sides and a top surrounded by an air gap formed between a source electrode and a drain electrode of the field effect transistor.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: October 18, 2022
    Assignee: Raytheon Company
    Inventors: Jeffrey R. LaRoche, John P. Bettencourt, Paul J. Duval, Kelly P. Ip
  • Patent number: 11355590
    Abstract: The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Peter Ramvall, Matthias Passlack
  • Patent number: 11322606
    Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: May 3, 2022
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Weifeng Sun, Siyang Liu, Sheng Li, Chi Zhang, Xinyi Tao, Ningbo Li, Longxing Shi
  • Patent number: 11316015
    Abstract: A method for forming the semiconductor device that includes forming an etch mask covering a drain side of the gate structure and the silicon containing fin structure; etching a source side of the silicon containing fin structure adjacent to the channel region; and forming a germanium containing semiconductor material on an etched sidewall of the silicon containing fin structure adjacent to the channel region. Germanium from the germanium containing semiconductor material is diffused into the channel region to provide a graded silicon germanium region in the channel region having germanium present at a highest concentration in the channel region at the source end of the channel region and a germanium deficient concentration at the drain end of the channel region.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 26, 2022
    Assignee: International Business Machines Corporation
    Inventors: Shogo Mochizuki, Kangguo Cheng, Choonghyun Lee, Juntao Li
  • Patent number: 10056300
    Abstract: A device includes an NMOS FinFET device including a first fin. The first fin includes a first strain relaxed buffer layer doped with carbon and a first channel semiconductor material formed above the carbon-doped strain relaxed buffer layer. A PMOS FinFET device includes a second fin. The second fin includes a second strain relaxed buffer layer and a second channel semiconductor material formed above the carbon-doped strain relaxed buffer layer. A first gate structure is positioned around a portion of the NMOS fin. A second gate structure is positioned around a portion of the PMOS fin.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • Patent number: 9437613
    Abstract: In one aspect, a method of forming a multiple VT device structure includes the steps of: forming an alternating series of channel and barrier layers as a stack having at least one first channel layer, at least one first barrier layer, and at least one second channel layer; defining at least one first and at least one second active area in the stack; selectively removing the at least one first channel/barrier layers from the at least one second active area, such that the at least one first channel layer and the at least one second channel layer are the top-most layers in the stack in the at least one first and the at least one second active areas, respectively, wherein the at least one first barrier layer is configured to confine charge carriers to the at least one first channel layer in the first active area.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: September 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Amlan Majumdar, Jeffrey W. Sleight
  • Patent number: 9299615
    Abstract: In one aspect, a method of forming a multiple VT device structure includes the steps of: forming an alternating series of channel and barrier layers as a stack having at least one first channel layer, at least one first barrier layer, and at least one second channel layer; defining at least one first and at least one second active area in the stack; selectively removing the at least one first channel/barrier layers from the at least one second active area, such that the at least one first channel layer and the at least one second channel layer are the top-most layers in the stack in the at least one first and the at least one second active areas, respectively, wherein the at least one first barrier layer is configured to confine charge carriers to the at least one first channel layer in the first active area.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Amlan Majumdar, Jeffrey W. Sleight
  • Patent number: 9041056
    Abstract: According to one embodiment, a semiconductor device including: a substrate; a gate electrode formed above the substrate; a gate insulating film formed under the gate electrode; a channel layer formed under the gate insulating film by using a channel layer material; a source region and a drain region formed in the substrate so as to interpose the channel layer therebetween in a channel direction; and a source extension layer formed in the substrate between the channel layer and the source region so as to overlap a source-side end portion of the channel layer. The source extension layer forms a heterointerface with the channel layer. The heterointerface is a tunnel channel for carries.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshitaka Miyata, Kanna Adachi, Shigeru Kawanaka
  • Patent number: 9034722
    Abstract: A method for manufacturing a compound semiconductor device so as to separate a first substrate from a compound semiconductor laminated structure which includes forming a first compound semiconductor layer over a first substrate containing AlxGa1-xN (0?x<1) and having a first band gap; forming a second compound semiconductor layer over the first compound semiconductor layer containing AlyInzGa1-y-zN (0<y<1, 0<y+z?1) and having a second band gap larger than the first band gap; forming a compound semiconductor laminated structure over the second compound semiconductor layer; and removing the first compound semiconductor layer while irradiating the first compound semiconductor layer with light having an energy between the first band gap and the second band gap, and thereby separating the first substrate from the compound semiconductor laminated structure.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: May 19, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Toshihide Kikkawa
  • Patent number: 9029836
    Abstract: In a method for fabricating a graphene structure, there is formed on a fabrication substrate a pattern of a plurality of distinct graphene catalyst materials. In one graphene synthesis step, different numbers of graphene layers are formed on the catalyst materials in the formed pattern. In a method for fabricating a graphene transistor, on a fabrication substrate at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor channel and at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor source, and at a substrate region specified for synthesizing a graphene transistor drain. Then in one graphene synthesis step, at least one layer of graphene is formed at the substrate region for the graphene transistor channel, and at the regions for the transistor source and drain there are formed a plurality of layers of graphene.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: May 12, 2015
    Assignee: President and Fellows of Harvard College
    Inventors: Jung-Ung Park, SungWoo Nam, Charles M. Lieber
  • Patent number: 9012288
    Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: April 21, 2015
    Assignee: Transphorm Inc.
    Inventors: Rongming Chu, Robert Coffie
  • Patent number: 8999772
    Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: April 7, 2015
    Assignee: Fujitsu Limited
    Inventors: Masahito Kanamura, Kozo Makiyama
  • Patent number: 8987075
    Abstract: A semiconductor device includes a substrate, a carrier transit layer disposed above the substrate, a compound semiconductor layer disposed on the carrier transit layer, a source electrode disposed on the compound semiconductor layer, a first groove disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate, a drain electrode disposed in the inside of the first groove, a gate electrode located between the source electrode and the first groove and disposed on the compound semiconductor layer, and a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: March 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Masato Nishimori, Atsushi Yamada
  • Patent number: 8981429
    Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: March 17, 2015
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Chih-Fang Huang, Po-Chin Peng, Tsung-Chieh Hsiao, Ya-Hsien Liu, K. C. Chang, Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang, Tsung-Yu Yang, Ting-Fu Chang
  • Patent number: 8969925
    Abstract: A semiconductor device includes a substrate, a body region adjoining the substrate surface, a source contact region within the body region, a drain contact region adjoining the substrate surface and being separated from the body region, a dual JFET gate region located between the body region and the drain contact region, and a lateral JFET channel region adjoining the surface of the substrate and located between the body and the drain contact regions. A vertical JFET gate region is arranged essentially enclosed by the body region, a vertical JFET channel region being arranged between the enclosed vertical JFET gate and the dual JFET gate regions, a reduced drain resistance region being arranged between the dual JFET gate and the drain contact regions, and a buried pocket located under part of the body region, under the dual JFET gate region and under the vertical JFET channel and reduced drain resistance regions.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: March 3, 2015
    Assignee: K.Eklund Innovation
    Inventors: Klas-Hakan Eklund, Lars Vestling
  • Patent number: 8956935
    Abstract: A compound semiconductor device includes: a compound semiconductor multilayer structure; a gate insulating film on the compound semiconductor multilayer structure; and a gate electrode, wherein the gate electrode includes a gate base portion on the gate insulating film and a gate umbrella portion, and a surface of the gate umbrella portion includes a Schottky contact with the compound semiconductor multilayer structure.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: February 17, 2015
    Assignee: Fujitsu Limited
    Inventor: Naoko Kurahashi
  • Patent number: 8952422
    Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: February 10, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hokyun Ahn, Jong-Won Lim, Jeong-Jin Kim, Hae Cheon Kim, Jae Kyoung Mun, Eun Soo Nam
  • Patent number: 8946771
    Abstract: The present disclosure relates to an enhancement mode gallium nitride (GaN) transistor device. The GaN transistor device has an electron supply layer located on top of a GaN layer. An etch stop layer (e.g., AlN) is disposed above the electron supply layer. A gate structure is formed on top of the etch stop layer, such that the bottom surface of the gate structure is located vertically above the etch stop layer. The position of etch stop layer in the GaN transistor device stack allows it to both enhance gate definition during processing (e.g., selective etching of the gate structure located on top of the AlN layer) and to act as a gate insulator that reduces gate leakage of the GaN transistor device.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wen Hsiung, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chun-Wei Hsu, Chen-Ju Yu, Fu-Chih Yang
  • Patent number: 8936976
    Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: January 20, 2015
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Prashant Majhi, Jack T. Kavalieros, Niti Goel, Wilman Tsai, Niloy Mukherjee, Yong Ju Lee, Gilbert Dewey, Willy Rachmady
  • Patent number: 8933489
    Abstract: An AlGaN/GaN.HEMT includes, a compound semiconductor lamination structure; a p-type semiconductor layer formed on the compound semiconductor lamination structure; and a gate electrode formed on the p-type semiconductor layer, in which Mg being an inert element of p-GaN is introduced into both sides of the gate electrode at the p-type semiconductor layer, and introduced portions of Mg are inactivated.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: January 13, 2015
    Assignee: Transphorm Japan, Inc.
    Inventor: Toshihide Kikkawa
  • Patent number: 8933485
    Abstract: An embodiment of a compound semiconductor device includes: a Si substrate; a Si oxide layer formed over a surface of the Si substrate; a nucleation layer formed over the Si oxide layer, the nucleation layer exposing a part of the Si oxide layer; and a compound semiconductor stacked structure formed over the Si oxide layer and the nucleation layer.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: January 13, 2015
    Assignee: Fujitsu Limited
    Inventor: Atsushi Yamada
  • Patent number: 8928096
    Abstract: A buried-channel field-effect transistor includes a semiconductor layer formed on a substrate. The semiconductor layer includes doped source and drain regions and an undoped channel region. the transistor further includes a gate dielectric formed over the channel region and partially overlapping the source and drain regions; a gate formed over the gate dielectric; and a doped shielding layer between the gate dielectric and the semiconductor layer.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni, Tak H. Ning
  • Patent number: 8921172
    Abstract: Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xuefeng Liu, Richard A. Phelps, Robert M. Rassel, Xiaowei Tian
  • Patent number: 8921893
    Abstract: A circuit structure includes a substrate, an unintentionally doped gallium nitride (UID GaN) layer over the substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. A number of islands are over the donor-supply layer between the gate structure and the drain. The gate structure disposed between the drain and the source. The gate structure is adjoins at least a portion of one of the islands and/or partially disposed over at least a portion of at least one of the islands.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ju Yu, Chih-Wen Hsiung, Fu-Wei Yao, Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Chih Yang
  • Patent number: 8912099
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: December 16, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichiro Kurahashi, Yoshitaka Kamo, Yoshitsugu Yamamoto