With Heterojunction Interface Channel Or Gate, E.g., Hfet, Higfet, Sisfet, Hjfet, Hemt (epo) Patents (Class 257/E21.403)
  • Patent number: 10056300
    Abstract: A device includes an NMOS FinFET device including a first fin. The first fin includes a first strain relaxed buffer layer doped with carbon and a first channel semiconductor material formed above the carbon-doped strain relaxed buffer layer. A PMOS FinFET device includes a second fin. The second fin includes a second strain relaxed buffer layer and a second channel semiconductor material formed above the carbon-doped strain relaxed buffer layer. A first gate structure is positioned around a portion of the NMOS fin. A second gate structure is positioned around a portion of the PMOS fin.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • Patent number: 9437613
    Abstract: In one aspect, a method of forming a multiple VT device structure includes the steps of: forming an alternating series of channel and barrier layers as a stack having at least one first channel layer, at least one first barrier layer, and at least one second channel layer; defining at least one first and at least one second active area in the stack; selectively removing the at least one first channel/barrier layers from the at least one second active area, such that the at least one first channel layer and the at least one second channel layer are the top-most layers in the stack in the at least one first and the at least one second active areas, respectively, wherein the at least one first barrier layer is configured to confine charge carriers to the at least one first channel layer in the first active area.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: September 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Amlan Majumdar, Jeffrey W. Sleight
  • Patent number: 9299615
    Abstract: In one aspect, a method of forming a multiple VT device structure includes the steps of: forming an alternating series of channel and barrier layers as a stack having at least one first channel layer, at least one first barrier layer, and at least one second channel layer; defining at least one first and at least one second active area in the stack; selectively removing the at least one first channel/barrier layers from the at least one second active area, such that the at least one first channel layer and the at least one second channel layer are the top-most layers in the stack in the at least one first and the at least one second active areas, respectively, wherein the at least one first barrier layer is configured to confine charge carriers to the at least one first channel layer in the first active area.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Amlan Majumdar, Jeffrey W. Sleight
  • Patent number: 9041056
    Abstract: According to one embodiment, a semiconductor device including: a substrate; a gate electrode formed above the substrate; a gate insulating film formed under the gate electrode; a channel layer formed under the gate insulating film by using a channel layer material; a source region and a drain region formed in the substrate so as to interpose the channel layer therebetween in a channel direction; and a source extension layer formed in the substrate between the channel layer and the source region so as to overlap a source-side end portion of the channel layer. The source extension layer forms a heterointerface with the channel layer. The heterointerface is a tunnel channel for carries.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshitaka Miyata, Kanna Adachi, Shigeru Kawanaka
  • Patent number: 9034722
    Abstract: A method for manufacturing a compound semiconductor device so as to separate a first substrate from a compound semiconductor laminated structure which includes forming a first compound semiconductor layer over a first substrate containing AlxGa1-xN (0?x<1) and having a first band gap; forming a second compound semiconductor layer over the first compound semiconductor layer containing AlyInzGa1-y-zN (0<y<1, 0<y+z?1) and having a second band gap larger than the first band gap; forming a compound semiconductor laminated structure over the second compound semiconductor layer; and removing the first compound semiconductor layer while irradiating the first compound semiconductor layer with light having an energy between the first band gap and the second band gap, and thereby separating the first substrate from the compound semiconductor laminated structure.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: May 19, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Toshihide Kikkawa
  • Patent number: 9029836
    Abstract: In a method for fabricating a graphene structure, there is formed on a fabrication substrate a pattern of a plurality of distinct graphene catalyst materials. In one graphene synthesis step, different numbers of graphene layers are formed on the catalyst materials in the formed pattern. In a method for fabricating a graphene transistor, on a fabrication substrate at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor channel and at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor source, and at a substrate region specified for synthesizing a graphene transistor drain. Then in one graphene synthesis step, at least one layer of graphene is formed at the substrate region for the graphene transistor channel, and at the regions for the transistor source and drain there are formed a plurality of layers of graphene.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: May 12, 2015
    Assignee: President and Fellows of Harvard College
    Inventors: Jung-Ung Park, SungWoo Nam, Charles M. Lieber
  • Patent number: 9012288
    Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: April 21, 2015
    Assignee: Transphorm Inc.
    Inventors: Rongming Chu, Robert Coffie
  • Patent number: 8999772
    Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: April 7, 2015
    Assignee: Fujitsu Limited
    Inventors: Masahito Kanamura, Kozo Makiyama
  • Patent number: 8987075
    Abstract: A semiconductor device includes a substrate, a carrier transit layer disposed above the substrate, a compound semiconductor layer disposed on the carrier transit layer, a source electrode disposed on the compound semiconductor layer, a first groove disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate, a drain electrode disposed in the inside of the first groove, a gate electrode located between the source electrode and the first groove and disposed on the compound semiconductor layer, and a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: March 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Masato Nishimori, Atsushi Yamada
  • Patent number: 8981429
    Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: March 17, 2015
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Chih-Fang Huang, Po-Chin Peng, Tsung-Chieh Hsiao, Ya-Hsien Liu, K. C. Chang, Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang, Tsung-Yu Yang, Ting-Fu Chang
  • Patent number: 8969925
    Abstract: A semiconductor device includes a substrate, a body region adjoining the substrate surface, a source contact region within the body region, a drain contact region adjoining the substrate surface and being separated from the body region, a dual JFET gate region located between the body region and the drain contact region, and a lateral JFET channel region adjoining the surface of the substrate and located between the body and the drain contact regions. A vertical JFET gate region is arranged essentially enclosed by the body region, a vertical JFET channel region being arranged between the enclosed vertical JFET gate and the dual JFET gate regions, a reduced drain resistance region being arranged between the dual JFET gate and the drain contact regions, and a buried pocket located under part of the body region, under the dual JFET gate region and under the vertical JFET channel and reduced drain resistance regions.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: March 3, 2015
    Assignee: K.Eklund Innovation
    Inventors: Klas-Hakan Eklund, Lars Vestling
  • Patent number: 8956935
    Abstract: A compound semiconductor device includes: a compound semiconductor multilayer structure; a gate insulating film on the compound semiconductor multilayer structure; and a gate electrode, wherein the gate electrode includes a gate base portion on the gate insulating film and a gate umbrella portion, and a surface of the gate umbrella portion includes a Schottky contact with the compound semiconductor multilayer structure.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: February 17, 2015
    Assignee: Fujitsu Limited
    Inventor: Naoko Kurahashi
  • Patent number: 8952422
    Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: February 10, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hokyun Ahn, Jong-Won Lim, Jeong-Jin Kim, Hae Cheon Kim, Jae Kyoung Mun, Eun Soo Nam
  • Patent number: 8946771
    Abstract: The present disclosure relates to an enhancement mode gallium nitride (GaN) transistor device. The GaN transistor device has an electron supply layer located on top of a GaN layer. An etch stop layer (e.g., AlN) is disposed above the electron supply layer. A gate structure is formed on top of the etch stop layer, such that the bottom surface of the gate structure is located vertically above the etch stop layer. The position of etch stop layer in the GaN transistor device stack allows it to both enhance gate definition during processing (e.g., selective etching of the gate structure located on top of the AlN layer) and to act as a gate insulator that reduces gate leakage of the GaN transistor device.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wen Hsiung, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chun-Wei Hsu, Chen-Ju Yu, Fu-Chih Yang
  • Patent number: 8936976
    Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: January 20, 2015
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Prashant Majhi, Jack T. Kavalieros, Niti Goel, Wilman Tsai, Niloy Mukherjee, Yong Ju Lee, Gilbert Dewey, Willy Rachmady
  • Patent number: 8933489
    Abstract: An AlGaN/GaN.HEMT includes, a compound semiconductor lamination structure; a p-type semiconductor layer formed on the compound semiconductor lamination structure; and a gate electrode formed on the p-type semiconductor layer, in which Mg being an inert element of p-GaN is introduced into both sides of the gate electrode at the p-type semiconductor layer, and introduced portions of Mg are inactivated.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: January 13, 2015
    Assignee: Transphorm Japan, Inc.
    Inventor: Toshihide Kikkawa
  • Patent number: 8933485
    Abstract: An embodiment of a compound semiconductor device includes: a Si substrate; a Si oxide layer formed over a surface of the Si substrate; a nucleation layer formed over the Si oxide layer, the nucleation layer exposing a part of the Si oxide layer; and a compound semiconductor stacked structure formed over the Si oxide layer and the nucleation layer.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: January 13, 2015
    Assignee: Fujitsu Limited
    Inventor: Atsushi Yamada
  • Patent number: 8928096
    Abstract: A buried-channel field-effect transistor includes a semiconductor layer formed on a substrate. The semiconductor layer includes doped source and drain regions and an undoped channel region. the transistor further includes a gate dielectric formed over the channel region and partially overlapping the source and drain regions; a gate formed over the gate dielectric; and a doped shielding layer between the gate dielectric and the semiconductor layer.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni, Tak H. Ning
  • Patent number: 8921172
    Abstract: Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xuefeng Liu, Richard A. Phelps, Robert M. Rassel, Xiaowei Tian
  • Patent number: 8921893
    Abstract: A circuit structure includes a substrate, an unintentionally doped gallium nitride (UID GaN) layer over the substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. A number of islands are over the donor-supply layer between the gate structure and the drain. The gate structure disposed between the drain and the source. The gate structure is adjoins at least a portion of one of the islands and/or partially disposed over at least a portion of at least one of the islands.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ju Yu, Chih-Wen Hsiung, Fu-Wei Yao, Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Chih Yang
  • Patent number: 8912099
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: December 16, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichiro Kurahashi, Yoshitaka Kamo, Yoshitsugu Yamamoto
  • Patent number: 8912084
    Abstract: A semiconductor device has a gate electrode including a leg part and a canopy part. A barrier layer is formed on a bottom face of the leg part of the gate electrode. In addition, on the lower surface of the barrier layer, a Schottky metal layer with an electrode width wider than the electrode width of the barrier layer is formed to have a Schottky junction with a semiconductor layer.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fumio Sasaki
  • Patent number: 8900939
    Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: December 2, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis Anderson, Karl D. Hobart, Michael A. Mastro, Charles R. Eddy, Jr.
  • Patent number: 8901606
    Abstract: A pseudomorphic high electron mobility transistor (pHEMT) comprises: a substrate comprising a Group III-V semiconductor material; buffer layer disposed over the substrate; and a channel layer disposed over the buffer layer. The buffer layer comprises microprecipitates of a Group V semiconductor element. A method of fabricating a pHEMT is also described.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: December 2, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Nate Perkins, Jonathan Abrokwah, Hans G. Rohdin, Phil Marsh, John Stanback
  • Patent number: 8896027
    Abstract: Disclosed is a high performance nitride semiconductor having a reverse leak current characteristic with two-dimensional electron gas as a conductive layer. A desired impurity is diffused into or a nitride semiconductor to which a desired impurity is added is re-grown on the bottom surface and the side face portion of a recessed portion formed by dry etching using chlorine gas on the upper surface of a nitride semiconductor stacked film to increase resistance of the side face portion of the nitride semiconductor stacked film contacting an anode electrode, reducing the reverse leak current.
    Type: Grant
    Filed: November 24, 2012
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Terano, Kazuhiro Mochizuki, Tomonobu Tsuchiya
  • Patent number: 8895378
    Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: November 25, 2014
    Assignee: Fujitsu Limited
    Inventors: Masahito Kanamura, Kozo Makiyama
  • Patent number: 8890211
    Abstract: A high performance high-electron mobility transistor (HEMT) design and methods of manufacturing the same are provided. This design introduces a bias layer in to the HEMT allowing the transistor to be fed with alternating current (AC) alone without the need for a negative direct current (DC) bias power supply.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: November 18, 2014
    Assignee: Lockheed Martin Corporation
    Inventors: Michael J. Mayo, Alfred A. Zinn, Roux M. Heyns
  • Patent number: 8884334
    Abstract: A transistor includes a first layer of a first type disposed over a buffer layer and having a first concentration of a first material. A first layer of a second type is disposed over the first layer of the first type, and a second layer of the first type is disposed over the first layer of the second type. The second layer of the first type having a second concentration of a first material that is greater than the first concentration of the first material. A source and a drain are spaced laterally from one another and are disposed over the buffer layer. A gate disposed over at least a portion of the second layer of the first type and disposed within a recessed area defined by the first and second layers of the first type and the first layer of the second type.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wen Hsiung, Chen-Ju Yu, Fu-Wei Yao
  • Patent number: 8884308
    Abstract: A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ju Yu, Chih-Wen Hsiung, Fu-Wei Yao, Chun-Wei Hsu, King-Yuen Wong, Jiun-Lei Jerry Yu, Fu-Chih Yang
  • Patent number: 8884265
    Abstract: An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: November 11, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Brian R. Bennett, John Bradley Boos, Theresa F. Chick, James G. Champlain
  • Patent number: 8877574
    Abstract: Portions of a top compound semiconductor layer are recessed employing a gate electrode as an etch mask to form a source trench and a drain trench. A low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material in the source trench and the drain trench. Metallization is performed on physically exposed surfaces of the elemental semiconductor material portions in the source trench and the drain trench by depositing a metal and inducing interaction with the metal and the at least one elemental semiconductor material. A metal semiconductor alloy of the metal and the at least one elemental semiconductor material can be performed at a temperature lower than 600° C. to provide a high electron mobility transistor with a well-defined device profile and reliable metallization contacts.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Davood Shahrjerdi
  • Patent number: 8860109
    Abstract: Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: October 14, 2014
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Jea-Gun Park, Tae-Hun Shim, Gon-Sub Lee, Seong-Je Kim, Tae-Hyun Kim
  • Patent number: 8860087
    Abstract: The present invention relates to a nitride semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a plurality of p-type nitride semiconductor segments formed on the nitride semiconductor layer and each formed lengthways from a first sidewall thereof, which is spaced apart from the source electrode, to a drain side; and a gate electrode formed to be close to the source electrode and in contact with the nitride semiconductor layer between the plurality of p-type semiconductor segments and portions of the p-type semiconductor segments extending in the direction of a source-side sidewall of the gate electrode aligned with the first sidewalls of the p-type nitride semiconductor segments is provided.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: October 14, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Hwan Park, Woo Chul Jeon, Ki Yeol Park, Seok Yoon Hong
  • Patent number: 8835985
    Abstract: According to an example embodiment, a power electronic device includes a first semiconductor layer, a second semiconductor layer on a first surface of the first semiconductor layer, and a source, a drain, and a gate on the second semiconductor layer. The source, drain and gate are separate from one another. The power electronic device further includes a 2-dimensional electron gas (2DEG) region at an interface between the first semiconductor layer and the second semiconductor layer, a first insulating layer on the gate and a second insulating layer adjacent to the first insulating layer. The first insulating layer has a first dielectric constant and the second insulating layer has a second dielectric constant less than the first dielectric constant.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-jun Hwang, Jai-kwang Shin, Jae-joon Oh, Jong-seob Kim, Hyuk-soon Choi, Ki-ha Hong
  • Patent number: 8829568
    Abstract: An insulating layer, an undoped first GaN layer and an AlGaN layer are laminated in this order on a surface of a semiconductor substrate. A surface barrier layer formed by a two-dimensional electron gas is provided in an interface between the first GaN layer and the AlGaN layer. A recess (first recess) which reaches the first GaN layer but does not pierce the first GaN layer is formed in a surface layer of the AlGaN layer. A first high withstand voltage transistor and a control circuit are formed integrally on the aforementioned semiconductor substrate. The first high withstand voltage transistor is formed in the first recess and on a surface of the AlGaN layer. The control circuit includes an n-channel MOSFET formed in part of the first recess, and a depression type n-channel MOSFET formed on a surface of the AlGaN layer.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: September 9, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Katsunori Ueno
  • Patent number: 8823012
    Abstract: Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: September 2, 2014
    Assignee: Efficient Power Conversion Corporation
    Inventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao, Guang Yuan Zhao, Robert Strittmatter, Fang Chang Liu
  • Patent number: 8816396
    Abstract: According to an example embodiment, a high electron mobility transistor (HEMT) includes a substrate, a buffer layer on the substrate, a channel layer on the buffer layer, and a barrier structure on the channel layer. The buffer layer includes a 2-dimensional electron gas (2DEG). A polarization of the barrier structure varies in a region corresponding to a gate electrode. The HEMT further includes and the gate electrode, a source electrode, and a drain electrode on the barrier structure.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-jun Hwang, Jong-seob Kim, Hyuk-soon Choi, Ki-ha Hong, Jai-kwang Shin, Jae-joon Oh
  • Patent number: 8815664
    Abstract: A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: August 26, 2014
    Assignees: Sumitomo Electric Industries, Ltd., Sumitomo Electric Device Innovations, Inc.
    Inventors: Takeshi Araya, Tsutomu Komatani
  • Patent number: 8815666
    Abstract: Provided is a power device. The power device may include a two-dimensional electron gas (2-DEG) layer in a portion corresponding to a gate electrode pattern since a second nitride layer is further formed on a lower portion of the gate electrode pattern after a first nitride layer is formed and thus, may be capable of performing a normally-OFF operation. Accordingly, the power device may adjust generation of the 2-DEG layer based on a voltage of a gate, and may reduce power consumption. The power device may regrow only the portion corresponding to the gate electrode pattern or may etch a portion excluding the portion corresponding to the gate electrode pattern and thus, a recess process may be omissible, a reproducibility of the power device may be secured, and a manufacturing process may be simplified.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae Hoon Lee
  • Patent number: 8809136
    Abstract: A semiconductor device having a source electrode and a drain electrode formed over a semiconductor substrate, a gate electrode formed over the semiconductor substrate and disposed between the source electrode and the drain electrode, a protection film made of an insulating material and formed between the source electrode and the gate electrode and between the drain electrode and the gate electrode, and a gate side opening formed at least in one of a portion of the protection film-between the source electrode and the gate electrode and a portion of the protection film between the drain electrode and the gate electrode and disposed away from all of the gate electrode, the source electrode and the drain electrode.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Limited
    Inventor: Toshihiro Ohki
  • Patent number: 8809968
    Abstract: This invention relates to a semiconductor layer structure. The semiconductor layer structure described includes a substrate and a buffer layer deposited onto the substrate. The semiconductor layer structure is characterized in that a drain voltage threshold lower than the breakdown voltage threshold is determined by isolating ions that are selectively implanted in just one region of the substrate into the substrate, wherein charge can dissipate from the one contact through the buffer layer towards a substrate region without isolating ions, if the one potential deviates from the other at least by the drain voltage threshold, and wherein the substrate region without isolating ions is located underneath the one contact. The semiconductor layer structure described allows dissipation of currents induced by induction in blocking active structures without damaging the active structures.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: August 19, 2014
    Assignee: Forschungsverbund Berlin E.V.
    Inventors: Oliver Hilt, Rimma Zhytnytska, Hans-Joachim Würfl
  • Patent number: 8803158
    Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Chin Chiu, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu, King-Yuen Wong
  • Patent number: 8796738
    Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: August 5, 2014
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8796737
    Abstract: High electron mobility transistors (HEMTs) and methods of manufacturing the same. A HEMT may include a channel layer and a channel supply layer, and the channel supply layer may be a multilayer structure. The channel supply layer may include an etch stop layer and an upper layer on the etch stop layer. A recess region may be in the upper layer. The recess region may be a region recessed to an interface between the upper layer and the etch stop layer. A gate electrode may be on the recess region.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-jun Hwang, Jai-kwang Shin, Jae-joon Oh, Jong-bong Ha, Hyuk-soon Choi, Ki-ha Hong
  • Patent number: 8791504
    Abstract: A circuit structure includes a substrate, a nucleation layer of undoped aluminum nitride, a graded buffer layer comprising aluminum, gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant, a ungraded buffer layer comprising gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant without aluminum, and a bulk layer of undoped gallium nitride over the ungraded buffer layer. The various dopants in the graded buffer layer and the ungraded buffer layer increases resistivity and results in layers having an intrinsically balanced conductivity.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: July 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Hung-Ta Lin, Chin-Cheng Chang, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang
  • Patent number: 8791465
    Abstract: A compound semiconductor device includes a compound semiconductor laminated structure, a passivation film formed on the compound semiconductor laminated structure and having a through-hole, and a gate electrode formed on the passivation film so as to plug the through-hole. A grain boundary between different crystalline orientations is formed in the gate electrode, and a starting point of the grain boundary is located apart from the through-hole on a flat surface of the passivation film.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Limited
    Inventors: Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Patent number: 8772834
    Abstract: According to example embodiments, a HEMT includes a channel layer, a channel supply layer on the channel layer, a source electrode and a drain electrode spaced apart on the channel layer, a depletion-forming layer on the channel supply layer, and a plurality of gate electrodes on the depletion-forming layer between the source electrode and the drain electrode. The channel supply layer is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured to form a depletion region in the 2DEG. The plurality of gate electrodes include a first gate electrode and a second gate electrode spaced apart from each other.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-chul Jeon, Jong-seob Kim, Ki-yeol Park, Young-hwan Park, Jae-joon Oh, Jong-bong Ha, Jai-kwang Shin
  • Patent number: 8772832
    Abstract: The present invention reduces the dynamic on resistance in the channel layer of a GaN device by etching a void in the nucleation and buffer layers between the gate and the drain. This void and the underside of the device substrate may be plated to form a back gate metal layer. The present invention increases the device breakdown voltage by reducing the electric field strength from the gate to the drain of a HEMT. This electric field strength is reduced by placing a back gate metal layer below the active region of the channel. The back gate metal layer may be in electrical contact with the source or drain.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: July 8, 2014
    Assignee: HRL Laboratories, LLC
    Inventor: Karim S Boutros
  • Patent number: 8772836
    Abstract: To provide a semiconductor device in which a rectifying element capable of reducing a leak current in reverse bias when a high voltage is applied and reducing a forward voltage drop Vf and a transistor element are integrally formed on a single substrate. A semiconductor device has a transistor element and a rectifying element on a single substrate. The transistor element has an active layer formed on the substrate and three electrodes (source electrode, drain electrode, and gate electrode) disposed on the active layer. The rectifying element has an anode electrode disposed on the active layer, a cathode electrode which is the drain electrode, and a first auxiliary electrode between the anode electrode and cathode electrode.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: July 8, 2014
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Osamu Machida
  • Patent number: 8759879
    Abstract: A semiconductor device containing a GaN FET has n-type doping in at least one III-N semiconductor layer of a low-defect layer and an electrical isolation layer below a barrier layer. A sheet charge carrier density of the n-type doping is 1 percent to 200 percent of a sheet charge carrier density of the two-dimensional electron gas.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: June 24, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Naveen Tipirneni, Sameer Pendharkar, Jungwoo Joh