Abstract: The invention describes a method for fabricating silicon semiconductor wafers with the layer structures from III-V semiconductor layers for the integration of HEMTs based on semiconductor III-V layers with silicon components. SOI silicon semiconductor wafers are used, the active semiconductor layer of which has the III-V semiconductor layers (24) of the HEMT design (2) placed on it stretching over two mutually insulated regions (24a, 24b) of the active silicon layer. An appropriate layer arrangement is likewise disclosed.

Abstract: An improved high breakdown voltage semiconductor device and method for manufacturing is provided. The device has a substrate and a AlaGa1-aN layer on the substrate wherein 0.1?a?1.00. A GaN layer is on the AlaGa1-aN layer. An In1-bGabN/GaN channel layer is on the GaN layer wherein 0.1?b?1.00. A AlcIndGa1-c-dN spacer layer is on the In1-bGabN/GaN layer wherein 0.1?c?1.00 and 0.0?d?0.99. A AleIn1-eN nested superlattice barrier layer is on the AlcIndGa1-c-dN spacer layer wherein 0.10?e?0.99. A AlfIngGa1-f-gN leakage suppression layer is on the AleIn1-eN barrier layer wherein 0.1?f?0.99 and 0.1?g?0.99 wherein the leakage suppression layer decreases leakage current and increases breakdown voltage during high voltage operation. A superstructure, preferably with metallic electrodes, is on the AlfIngGa1-f-gN leakage suppression layer.

Abstract: A fin field effect transistor (FinFET) device is provided. The FinFET includes a superlattice layer and a strained layer. The superlattice layer is supported by a substrate. The strained layer is disposed on the superlattice layer and provides a gate channel. The gate channel is stressed by the superlattice layer. In an embodiment, the superlattice layer is formed by stacking different silicon germanium alloys or stacking other III-V semiconductor materials.

Abstract: An overvoltage protection device for compound semiconductor field effect transistors includes an implanted region disposed in a compound semiconductor material. The implanted region has spatially distributed trap states which cause the implanted region to become electrically conductive at a threshold voltage. A first contact is connected to the implanted region. A second contact spaced apart from the first contact is also connected to the implanted region. The distance between the first and second contacts partly determines the threshold voltage of the overvoltage protection device.

Abstract: There is provided a semiconductor device including a base substrate; a semiconductor layer formed on the base substrate and having a mesa protrusion including a receiving groove; a source electrode and a drain electrode disposed to be spaced apart from each other on the semiconductor layer, the source electrode having a source leg and the drain electrode having a drain leg; and a gate electrode insulated from the source electrode and the drain electrode and having a recess part received into the receiving groove. The mesa protrusion has a superlattice structure including at least one trench at an interface between the mesa protrusion and the source electrode and between the mesa protrusion and the drain electrode, respectively, and the source leg and the drain leg are received in the trench.

Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

Abstract: A field effect transistor having a channel, a gate, and a structure for decreasing a gate-to-channel capacitance of the transistor as an operating frequency of the transistor increases. The structure can comprise, for example, a barrier disposed between the gate and the channel, which has a dielectric permittivity and/or a conductivity that varies with an operating frequency of the transistor. In an embodiment, the barrier comprises a layer of conducting material, such as conducting polymer, conducting semiconductor, conducting semi-metal, amorphous silicon, polycrystalline silicon, and/or the like.

Abstract: An embodiment of a transistor device includes a compound semiconductor material on a semiconductor carrier and a source region and a drain region spaced apart from each other in the compound semiconductor material with a channel region interposed between the source and drain regions. A Schottky diode is integrated with the semiconductor carrier, and contacts extend from the source and drain regions through the compound semiconductor material. The contacts are in electrical contact with the Schottky diode so that the Schottky diode is connected in parallel between the source and drain regions. In another embodiment, the integrated Schottky diode is formed by a region of doped amorphous silicon or doped polycrystalline silicon disposed in a trench structure on the drain side of the device.

Abstract: Disclosed herein are embodiments of a normally-off compound semiconductor tunnel field effect transistor having a drive current above 100 mA per mm of gate length and a sub-threshold slope below 60 mV per decade at room temperature, and methods of manufacturing such a normally-off compound semiconductor tunnel transistor. The compound semiconductor tunnel field effect transistor is fast-switching and can be used for high voltage applications e.g. 30V up to 600V and higher.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a two-dimensional carrier gas layer, a first main electrode, a second main electrode, a first gate electrode, and a second gate electrode. The first gate electrode is provided between a part of the first main electrode and a part of the second main electrode opposite to the part of the first main electrode. The second gate electrode is provided between another part of the first main electrode and another part of the second main electrode opposite to the another part of the first main electrode with a separation region interposed between the first gate electrode and the second gate electrode. The second gate electrode is controlled independently of the first gate electrode.

Abstract: The Si substrate of a group III-N HEMT is formed in layers that define a p-n junction which electrically isolates an upper region of the Si substrate from a lower region of the Si substrate. As a result, the upper region of the Si substrate can electrically float, thereby obtaining a full buffer breakdown voltage, while the lower region of the Si substrate can be attached to a package by way of a conductive epoxy, thereby significantly improving the thermal conductivity of the group III-N HEMT and minimizing undesirable floating-voltage regions.

Abstract: Power electronic devices including 2-dimensional electron gas (2DEG) channels and methods of manufacturing the same. A power electronic device includes lower and upper material layers for forming a 2DEG channel, and a gate contacting an upper surface of the upper material layer. A region below the gate of the 2DEG channel is an off region where the density of a 2DEG is reduced or zero. The entire upper material layer may be continuous and may have a uniform thickness. A region of the upper material layer under the gate contains an impurity for reducing or eliminating a lattice constant difference between the lower and upper material layers.

Abstract: A semiconductor device includes a substrate, a carrier transit layer disposed above the substrate, a compound semiconductor layer disposed on the carrier transit layer, a source electrode disposed on the compound semiconductor layer, a first groove disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate, a drain electrode disposed in the inside of the first groove, a gate electrode located between the source electrode and the first groove and disposed on the compound semiconductor layer, and a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate.

Abstract: A method of manufacturing a nitride semiconductor device including: forming a nitride semiconductor layer over a substrate wherein the nitride semiconductor layer has a 2DEG channel inside; forming a drain electrode in ohmic contact with the nitride semiconductor layer and a source electrode spaced apart from the drain electrode, in Schottky contact with the nitride semiconductor layer, wherein the source electrode has an ohmic pattern in ohmic contact with the nitride semiconductor layer inside; forming a dielectric layer on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode; and forming a gate electrode on the dielectric layer to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed on the dielectric layer over a drain-side edge portion of the source electrode.

Abstract: The buffer breakdown of a group III-N HEMT on a p-type Si substrate is significantly increased by forming an n-well in the p-type Si substrate to lie directly below the metal drain region of the group III-N HEMT. The n-well forms a p-n junction which becomes reverse biased during breakdown, thereby increasing the buffer breakdown by the reverse-biased breakdown voltage of the p-n junction and allowing the substrate to be grounded. The buffer layer of a group III-N HEMT can also be implanted with n-type and p-type dopants which are aligned with the p-n junction to minimize any leakage currents at the junction between the substrate and the buffer layer.

Abstract: Disclosed are embodiments of a metal oxide semiconductor field effect transistor (MOSFET) structure and a method of forming the structure. The structure incorporates source/drain regions and a channel region between the source/drain regions. The source/drain regions can comprise silicon, which has high diffusivity to the source/drain dopant. The channel region can comprise a silicon alloy selected for optimal charge carrier mobility and band energy and for its low source/drain dopant diffusivity. During processing, the source/drain dopant can diffuse into the edge portions of the channel region. However, due to the low diffusivity of the silicon alloy to the source/drain dopant, the dopant does not diffuse deep into channel region. Thus, the edge portions of the silicon alloy channel region can have essentially the same dopant profile as the source/drain regions, but a different dopant profile than the center portion of the silicon alloy channel region.

Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.

Abstract: The invention discloses a semiconductor device which comprises an NMOS transistor and a PMOS transistor formed on a substrate; and grid electrodes, source cathode doped areas, drain doped areas, and side walls formed on two sides of the grid electrodes are arranged on the NMOS transistor and the PMOS transistor respectively. The device is characterized in that the side walls on the two sides of the grid electrode of the NMOS transistor possess tensile stress, and the side walls on the two sides of the grid electrode of the PMOS transistor possess compressive stress. The stress gives the side walls a greater role in adjusting the stress applied to channels and the source/drain areas, with the carrier mobility further enhanced and the performance of the device improved.

Abstract: A semiconductor device includes a compound semiconductor layer provided over a substrate, a plurality of source electrodes and a plurality of drain electrodes provided over the compound semiconductor layer, a plurality of first vias each of which is configured to pass through the compound semiconductor layer and be coupled to a corresponding one of the plurality of source electrodes, a plurality of second vias each of which is configured to pass through the compound semiconductor layer and be coupled to a corresponding one of the plurality of drain electrodes, a common source wiring line configured to be coupled to the plurality of first vias and be buried in the substrate, and a common drain wiring line configured to be coupled to the plurality of second vias and be buried in the substrate.

Abstract: A transistor includes a first semiconductor layer. A second semiconductor layer is located on the first semiconductor layer. A portion of the second semiconductor layer is removed to expose a first portion of the first semiconductor layer and to provide vertical sidewalls of the second semiconductor layer. A gate spacer is located on the second semiconductor layer. A gate dielectric includes a first portion located on the first portion of the first semiconductor layer and a second portion adjacent to the vertical sidewalls of the second semiconductor layer. A gate conductor is located on the first portion of the gate dielectric and abuts the gate dielectric second portion. A channel region is located in at least part of the first portion of the first semiconductor layer. Raised source/drain regions are located in the second semiconductor layer. At least part of the raised source/drain regions is located below the gate spacer.

Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer and a channel layer. The channel layer may include an effective channel region and a high resistivity region. The effective channel region may be between the high resistivity region and the channel supply layer. The high resistivity region may be a region into which impurities are ion-implanted. According to example embodiments, a method of forming a HEMT includes forming a device unit, including a channel layer and a channel supply layer, on a first substrate; adhering a second substrate to the device unit; removing the first substrate; and forming a high resistivity region by ion-implanting impurities into at least a portion of the channel layer.

Abstract: A HEMT includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer, and a passivation material layer having one or more buried portions contacting or almost contacting the UID GaN layer. A carrier channel layer at the interface of the donor-supply layer and the UID GaN layer has patches of non-conduction in a drift region between the gate and the drain. A method for making the HEMT is also provided.

Abstract: The present invention describes a transistor based on a Hetero junction FET structure, where the metal gate has been replaced by a stack formed by a highly doped compound semiconductor and an insulating layer in order to achieve enhancement mode operation and at the same time drastically reduce the gate current leakage. The combination of the insulating layer with a highly doped semiconductor allows the tuning of the threshold voltage of the device at the desired value by simply changing the composition of the semiconductor layer forming the gate region and/or its doping allowing a higher degree of freedom. In one of the embodiment, a back-barrier layer and a heavily doped threshold tuning layer are used to suppress Short Channel Effect phenomena and to adjust the threshold voltage of the device at the desired value. The present invention can be realized both with polar and non-polar (or semi-polar) materials.

Abstract: A compound semiconductor device includes a substrate; a compound semiconductor layer formed over the substrate; and a gate electrode formed over the compound semiconductor layer with a gate insulating film arranged therebetween. The gate insulating film includes a first layer having reverse spontaneous polarization, the direction of which is opposite to spontaneous polarization of the compound semiconductor layer.

Abstract: A semiconductor device such as a diode or transistor includes a semiconductor substrate, a first region of III-V semiconductor material on the semiconductor substrate and a second region of III-V semiconductor material on the first region. The second region is spaced apart from the semiconductor substrate by the first region. The second region is of a different composition than the first region. The semiconductor device further includes a buried contact extending from the semiconductor substrate to the second region through the first region. The buried contact electrically connects the second region to the semiconductor substrate.

Abstract: A semiconductor device including a first GaN layer, an AlGaN layer, a second GaN layer, a gate electrode, a source electrode, and a drain electrode sequentially stacked on a substrate, capable of improving a leakage current and a breakdown voltage characteristics generated in the gate electrode by locally forming a p type GaN layer on the AlGaN layer, and a manufacturing method thereof, and a manufacturing method thereof are provided. The semiconductor device includes: a substrate, a first GaN layer formed on the substrate, an AlGaN layer formed on the first GaN layer, a second GaN layer formed on the AlGaN layer and including a p type GaN layer, and a gate electrode formed on the second GaN layer, wherein the p type GaN layer may be in contact with a portion of the gate electrode.

Abstract: In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices.

Abstract: Methods and apparatuses are disclosed for providing heterostructure field effect transistors (HFETs) with high-quality gate dielectric and field plate dielectric. The gate dielectric and field plate dielectric are in situ deposited on a semiconductor surface. The location of the gate electrode may be defined by etching a first pattern in the field plate dielectric and using the gate dielectric as an etch-stop. Alternatively, an additional etch-stop layer may be in situ deposited between the gate dielectric and the field plate dielectric. After etching the first pattern, a conductive material may be deposited and patterned to define the gate electrode. Source and drain electrodes that electrically contact the semiconductor surface are formed on opposite sides of the gate electrode.

Abstract: An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. A recess positioning between the gate electrode and the drain electrode in a plan view is formed at a surface of the compound semiconductor stacked structure.

Abstract: A hetero-structure field effect transistor (HFET). The HFET may include a first contact and a second contact and a hetero-junction structure. The hetero-junction structure may include a first layer made from a first semiconductor material and a second layer made from a second semiconductor material. An interface at which the first layer and the second layer are in contact with each other may be provided, along which a two dimensional electron gas (2DEG) is formed in a part of the first layer directly adjacent to the interface, for propagating of electrical signals from the first contact to the second contact or vice versa. The transistor may further include a gate structure for controlling a conductance of the channel; a substrate layer made from a substrate semiconductor material, and a dielectric layer separating the first layer from the substrate layer. The second contact may include an electrical connection between the substrate layer and the first layer.

Abstract: A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.

Abstract: Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including a base substrate; a semiconductor layer disposed on the base substrate; and an electrode structure disposed on the semiconductor layer, wherein the electrode structure includes: a first electrode ohmic-contacting the semiconductor layer; a ohmic contact unit ohmic-contacting the semiconductor layer and spaced apart from the first electrode; and a schottky contact unit schottky-contacting the semiconductor layer and covering the ohmic contact unit.

Abstract: An enhancement-mode group III-N high electron mobility transistor (HEMT) with a reverse polarization cap is formed in a method that utilizes a reverse polarization cap structure, such as an InGaN cap structure, to deplete the two-dimensional electron gas (2DEG) and form a normally off device, and a spacer layer that lies below the reverse polarization cap structure and above the barrier layer of the HEMT which allows the reverse polarization cap layer to be etched without etching into the barrier layer.

Abstract: A high-power and high-gain ultra-short gate HEMT device has exceptional gain and an exceptionally high breakdown voltage provided by an increased width asymmetric recess for the gate electrode, by a composite channel layer including a thin indium arsenide layer embedded in the indium gallium arsenide channel layer and by double doping through the use of an additional silicon doping spike. The improved transistor has an exceptional 14 dB gain at 110 GHz and exhibits an exceptionally high 3.5-4 V breakdown voltage, thus to provide high gain, high-power and ultra-high frequency in an ultra-short gate device.

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

Abstract: The present disclosure relates to an enhancement mode gallium nitride (GaN) transistor device. The GaN transistor device has an electron supply layer located on top of a GaN layer. An etch stop layer (e.g., AlN) is disposed above the electron supply layer. A gate structure is formed on top of the etch stop layer, such that the bottom surface of the gate structure is located vertically above the etch stop layer. The position of etch stop layer in the GaN transistor device stack allows it to both enhance gate definition during processing (e.g., selective etching of the gate structure located on top of the AlN layer) and to act as a gate insulator that reduces gate leakage of the GaN transistor device.

Abstract: An enhancement-mode GaN transistor, the transistor having a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate containing acceptor type dopant elements, and a diffusion barrier comprised of a III Nitride material between the gate and the buffer layer.

Abstract: An electrode structure, a GaN-based semiconductor device including the electrode structure, and methods of manufacturing the same, may include a GaN-based semiconductor layer and an electrode structure on the GaN-based semiconductor layer. The electrode structure may include an electrode element including a conductive material and a diffusion layer between the electrode element and the GaN-based semiconductor layer. The diffusion layer may include a material which is an n-type dopant with respect to the GaN-based semiconductor layer, and the diffusion layer may contact the GaN-based semiconductor layer. A region of the GaN-based semiconductor layer contacting the diffusion layer may be doped with the n-type dopant. The material of the diffusion layer may comprise a Group 4 element.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.

Abstract: A tunneling field effect transistor structure and a method for forming the same are provided. The tunneling field effect transistor structure comprises: a substrate; a plurality of convex structures formed on the substrate, every two adjacent convex structures being separated by a predetermined cavity less than 30 nm in width, the convex structures comprising a plurality of sets, and each set comprising more than two convex structures; a plurality of floated films formed on tops of the convex structures, each floated film corresponding to one set of convex structures, a region of each floated film corresponding to a top of an intermediate convex structure in each set being formed as a channel region, and regions of the each floated film at both sides of the channel region are formed as a source region and a drain region with opposite conductivity types respectively; and a gate stack formed on each channel region.

Abstract: An enhancement mode gallium nitride (GaN) transistor with a Mg doped layer and a Mg growth interruption (diffusion barrier) layer to trap excess or residual Mg dopant. The Mg growth interruption (diffusion barrier) layer is formed by growing GaN, stopping the supply of gallium while maintaining a supply of ammonia or other nitrogen containing source to form a layer of magnesium nitride (MgN), and then resuming the flow of gallium to form a GaN layer to seal in the layer of MgN.

Abstract: The disclosure relates to electronic devices and associated methods of manufacture including materials of the Group III/N. An exemplary device successively includes, from its base towards its surface: (i) a support substrate, (ii) a layer adapted to contain an electron gas, (iii) a barrier layer, and (iv) a superficial layer extending on at least one part of the surface of the barrier layer, wherein the superficial layer has an electrical field of which the current is controlled so that, in at least one first region of the superficial layer, the electrical field is weaker than in a second region of the superficial layer.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device such as, for example, a high electron mobility transistor (HEMT) or metal-insulator-semiconductor field-effect transistor (MISFET), or combinations thereof. The IC device includes a buffer layer formed on a substrate, a barrier layer formed on the buffer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) and gallium (Ga), a cap layer formed on the barrier layer, the cap layer including nitrogen (N) and at least one of indium (In) and gallium (Ga), and a gate formed on the cap layer, the gate being directly coupled with the cap layer. Other embodiments may also be described and/or claimed.

Abstract: An integrated device including a III-nitride HEMT and a Schottky diode includes a substrate comprising a first III-nitride material and a drift region comprising a second III-nitride material coupled to the substrate and disposed adjacent to the substrate along a vertical direction. The integrated device also includes a first barrier layer coupled to the drift region and a channel layer comprising a third III-nitride material having a first bandgap and coupled to the barrier layer. The integrated device further includes a second barrier layer characterized by a second bandgap and coupled to the channel layer and a Schottky contact coupled to the drift region. The second bandgap is greater than the first bandgap.

Abstract: An improved structure of the high electron mobility transistor (HEMT) and a fabrication method thereof are disclosed. The improved HEMT structure comprises a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a first etch stop layer, a first n type doped layer formed by AlxGa1-xAs, and a second n type doped layer. The fabrication method comprises steps of: etching a gate, a drain, and a source recess by using a multiple selective etching process. Below the gate, the drain, and the source recess is the Schottky layer. A gate electrode is deposited in the gate recess to form Schottky contact. A drain electrode and a source electrode are deposited to form ohmic contacts in the drain recess and the source recess respectively, and on the second n type doped layer surrounding the drain recess and the source recess respectively.

Abstract: A semiconductor device includes a first element structure that includes a charge supply layer of first polarity; a charge channel layer of second polarity, the charge channel layer being formed above the charge supply layer and including a recess portion; and a first electrode formed in the recess portion above the charge channel layer.

Abstract: The present invention relates to a nitride semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a p-type nitride layer formed on the nitride semiconductor layer between the source and drain electrodes; an n-type nitride layer formed on the p-type nitride layer; and a gate electrode formed between the source and drain electrodes to be close to the source electrode and in contact with the n-type nitride layer so that a source-side sidewall thereof is aligned with source-side sidewalls of the p-type and n-type nitride layers is provided. Further, a method of manufacturing a nitride semiconductor device is provided.

Abstract: An embodiment of a compound semiconductor device includes: a substrate; a compound semiconductor stacked structure formed over the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. The compound semiconductor stacked structure includes: an electron channel layer; and a nitride semiconductor layer which includes an electron supply layer formed over the electron channel layer. An indium (In) fraction at a surface of the nitride semiconductor layer in each of a region between the gate electrode and the source electrode and a region between the gate electrode and the drain electrode is lower than an indium (In) fraction at a surface of the nitride semiconductor layer in a region below the gate electrode.

Abstract: A semiconductor device includes: a first semiconductor layer formed on a substrate; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; and a source electrode and a drain electrode formed in contact with the second semiconductor layer, wherein a semiconductor material of the third semiconductor layer is doped with a p-type impurity element; and the third semiconductor layer has a jutting out region that juts out beyond an edge of the gate electrode toward a side where the drain electrode is provided.

Abstract: An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; a first p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a second p-type semiconductor layer formed between the electron supply layer and at least one of the source electrode and the drain electrode. The one of the source electrode and the drain electrode on the second p-type semiconductor layer includes: a first metal film; and a second metal film Which contacts the first metal film on the gate electrode side of the first metal film, and a resistance of which is higher than that of the first metal film.