With An Heterojunction Interface Channel Or Gate, E.g., Hfet, Higfet, Si Sfet, Hjfet, Hemt (epo) Patents (Class 257/E21.407)
  • Patent number: 10679860
    Abstract: A method for fabrication of high electron mobility transistor (HEMT) semiconductor devices is presented. The method includes providing a substrate, growing a HEMT layer structure on the substrate; and self-aligned common metal stack formation of source, drain and gate electrodes on the HEMT layer structure using a single lithographic mask.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: June 9, 2020
    Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Lakshmi Kanta Bera, Yee Chong Loke, Surani Bin Dolmanan, Sudhiranjan Tripathy, Wai Hoe Tham
  • Patent number: 10319829
    Abstract: A method of regrowing material includes providing a III-nitride structure including a masking layer and patterning the masking layer to form an etch mask. The method also includes removing, using an in-situ etch, a portion of the III-nitride structure to expose a regrowth region and regrowing a III-nitride material in the regrowth region.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: June 11, 2019
    Assignee: NEXGEN POWER SYSTEMS, INC.
    Inventors: David P. Bour, Thomas R. Prunty, Hui Nie, Madhan M. Raj
  • Patent number: 10263065
    Abstract: Methods of forming a metal resistor are provided. The methods may include: depositing a metal layer, e.g., tungsten, on a substrate; and forming the metal resistor by implanting a semiconductor species, e.g., silicon and/or germanium, into the metal layer to form a semiconductor-metal alloy layer from at least a portion of the metal layer. In certain embodiments, an adhesion layer may be deposited by ALD prior to metal layer depositing. The metal resistor has a sheet resistance that remains substantially constant prior to and after subsequent annealing.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: April 16, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Domingo A. Ferrer Luppi, Aritra Dasgupta, Benjamin G. Moser
  • Patent number: 10243138
    Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Gen P. Lauer, Janusz J. Nowak, Eugene J. O'Sullivan
  • Patent number: 10199217
    Abstract: Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: February 5, 2019
    Assignee: Transphorm Inc.
    Inventors: Rongming Chu, Umesh Mishra, Rakesh K. Lal
  • Patent number: 10134877
    Abstract: A method for manufacturing an organic light emitting diode (OLED) display can include forming a gate electrode on a substrate, forming a semiconductor layer by depositing a gate insulating layer and an oxide semiconductor material and patterning the oxide semiconductor material, forming an etch stopper on a central portion of the semiconductor layer, conducting a plasma treatment using the etch stopper as a mask to conductorize portions of the semiconductor layer exposed by the etch stopper for defining a channel area, a source area and a drain area, and forming a source electrode contacting portions of the conductorized source area and a drain electrode contacting portions of the conductorized drain area.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: November 20, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sungjin Hong, Byungchul Ahn, Youngju Koh, Woojin Nam, Ryosuke Tani
  • Patent number: 9935283
    Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
  • Patent number: 9601608
    Abstract: A high-electron mobility transistor (HEMT) device employing a gate protection layer is provided. A substrate has a channel layer arranged over the substrate and has a barrier layer arranged over the channel layer. The channel and barrier layers define a heterojunction, and a gate structure is arranged over a gate region of the barrier layer. The gate structure includes a gate arranged over a cap, where the cap is disposed on the barrier layer. The gate protection layer is arranged along sidewalls of the cap and arranged below the gate between opposing surfaces of the gate and the cap. Advantageously, the gate protection layer passivates the gate, reduces leakage current along sidewalls of the cap, and improves device reliability and threshold voltage uniformity. A method for manufacturing the HEMT device is also provided.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Wei Tsai, King-Yuen Wong, Han-Chin Chiu, Sheng-de Liu
  • Patent number: 9590069
    Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 7, 2017
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Niloy Mukherjee, Niti Goel, Sanaz Kabehie Gardner, Seung Hoon Sung, Ravi Pillarisetty, Robert S. Chau
  • Patent number: 9305878
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a metal contact structure, an electrically conductive capping layer formed on the metal contact structure, and a conductive via electrically connected to the metal contact structure through the electrically conductive capping layer.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: April 5, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Torsten Huisinga, Carsten Peters, Andreas Ott, Axel Preusse
  • Patent number: 9041056
    Abstract: According to one embodiment, a semiconductor device including: a substrate; a gate electrode formed above the substrate; a gate insulating film formed under the gate electrode; a channel layer formed under the gate insulating film by using a channel layer material; a source region and a drain region formed in the substrate so as to interpose the channel layer therebetween in a channel direction; and a source extension layer formed in the substrate between the channel layer and the source region so as to overlap a source-side end portion of the channel layer. The source extension layer forms a heterointerface with the channel layer. The heterointerface is a tunnel channel for carries.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshitaka Miyata, Kanna Adachi, Shigeru Kawanaka
  • Patent number: 9018056
    Abstract: A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face III-Nitride material, a non-inverted N-channel III-Nitride field effect transistor, epitaxially grown, a first III-Nitride barrier layer, two-dimensional hole gas, second III-Nitride barrier layer, and a two-dimensional hole gas. A method of making complementary non-inverted P-channel and non-inverted N-channel III-Nitride FET comprising growing epitaxial layers, depositing oxide, defining opening, growing epitaxially a first nitrogen-polar III-Nitride material, buffer, back barrier, channel, spacer, barrier, and cap layer, and carrier enhancement layer, depositing oxide, growing AlN nucleation layer/polarity inversion layer, growing gallium-polar III-Nitride, including epitaxial layers, depositing dielectric, fabricating P-channel III-Nitride FET, and fabricating N-channel III-Nitride FET.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: April 28, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Michael A. Mastro, Charles R. Eddy, Jr., Jennifer K. Hite
  • Patent number: 8987075
    Abstract: A semiconductor device includes a substrate, a carrier transit layer disposed above the substrate, a compound semiconductor layer disposed on the carrier transit layer, a source electrode disposed on the compound semiconductor layer, a first groove disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate, a drain electrode disposed in the inside of the first groove, a gate electrode located between the source electrode and the first groove and disposed on the compound semiconductor layer, and a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: March 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Masato Nishimori, Atsushi Yamada
  • Patent number: 8981429
    Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: March 17, 2015
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Chih-Fang Huang, Po-Chin Peng, Tsung-Chieh Hsiao, Ya-Hsien Liu, K. C. Chang, Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang, Tsung-Yu Yang, Ting-Fu Chang
  • Patent number: 8946032
    Abstract: A power device manufacturing method is provided. The power device manufacturing method may perform patterning of regions on which a source electrode and a drain electrode are to be formed, may regrow n+-gallium nitride (GaN) and p+-GaN in the patterned regions and thus, a thin film crystal may not be damaged. Also, a doping concentration of n+-GaN or p+-GaN may be adjusted, an ohmic resistance in the source electrode region and the drain electrode region may decrease, and a current density may increase. The power device manufacturing method may regrow n+-GaN and p+-GaN at a high temperature after an n-GaN layer and a p-GaN layer are patterned. Accordingly, a thin film crystal may not be damaged and thus, a reliability may be secured, and an annealing process may not be additionally performed and thus, a process may be simplified and a cost may be reduced.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae Hoon Lee
  • Patent number: 8941148
    Abstract: A semiconductor device is disclosed. One embodiment includes a lateral HEMT (High Electron Mobility Transistor) structure with a heterojunction between two differing group III-nitride semiconductor compounds and a layer arranged on the heterojunction. The layer includes a group III-nitride semiconductor compound and at least one barrier to hinder current flow in the layer.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: January 27, 2015
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Prechtl
  • Patent number: 8941118
    Abstract: A III-nitride transistor includes a III-nitride channel layer, a barrier layer over the channel layer, the barrier layer having a thickness of 1 to 10 nanometers, a dielectric layer on top of the barrier layer, a source electrode contacting the channel layer, a drain electrode contacting the channel layer, a gate trench extending through the dielectric layer and barrier layer and having a bottom located within the channel layer, a gate insulator lining the gate trench and extending over the dielectric layer, and a gate electrode in the gate trench and extending partially toward the source and the drain electrodes to form an integrated gate field-plate, wherein a distance between an interface of the channel layer and the barrier layer and the bottom of the gate trench is greater than 0 nm and less than or equal to 5 nm.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: January 27, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Rongming Chu, David F. Brown, Adam J. Williams
  • Patent number: 8933489
    Abstract: An AlGaN/GaN.HEMT includes, a compound semiconductor lamination structure; a p-type semiconductor layer formed on the compound semiconductor lamination structure; and a gate electrode formed on the p-type semiconductor layer, in which Mg being an inert element of p-GaN is introduced into both sides of the gate electrode at the p-type semiconductor layer, and introduced portions of Mg are inactivated.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: January 13, 2015
    Assignee: Transphorm Japan, Inc.
    Inventor: Toshihide Kikkawa
  • Patent number: 8921893
    Abstract: A circuit structure includes a substrate, an unintentionally doped gallium nitride (UID GaN) layer over the substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. A number of islands are over the donor-supply layer between the gate structure and the drain. The gate structure disposed between the drain and the source. The gate structure is adjoins at least a portion of one of the islands and/or partially disposed over at least a portion of at least one of the islands.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ju Yu, Chih-Wen Hsiung, Fu-Wei Yao, Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Chih Yang
  • Patent number: 8921172
    Abstract: Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xuefeng Liu, Richard A. Phelps, Robert M. Rassel, Xiaowei Tian
  • Patent number: 8912099
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: December 16, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichiro Kurahashi, Yoshitaka Kamo, Yoshitsugu Yamamoto
  • Patent number: 8900939
    Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: December 2, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis Anderson, Karl D. Hobart, Michael A. Mastro, Charles R. Eddy, Jr.
  • Patent number: 8895421
    Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: November 25, 2014
    Assignee: Transphorm Inc.
    Inventors: Primit Parikh, Yuvaraj Dora, Yifeng Wu, Umesh Mishra, Nicholas Fichtenbaum, Rakesh K. Lal
  • Patent number: 8877574
    Abstract: Portions of a top compound semiconductor layer are recessed employing a gate electrode as an etch mask to form a source trench and a drain trench. A low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material in the source trench and the drain trench. Metallization is performed on physically exposed surfaces of the elemental semiconductor material portions in the source trench and the drain trench by depositing a metal and inducing interaction with the metal and the at least one elemental semiconductor material. A metal semiconductor alloy of the metal and the at least one elemental semiconductor material can be performed at a temperature lower than 600° C. to provide a high electron mobility transistor with a well-defined device profile and reliable metallization contacts.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Davood Shahrjerdi
  • Patent number: 8859345
    Abstract: A III-nitride heterojunction power semiconductor device having a barrier layer that includes a region of reduced nitrogen content.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: October 14, 2014
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8860085
    Abstract: A III-nitride heterojunction power semiconductor device having a barrier layer that includes a region of reduced nitrogen content.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: October 14, 2014
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8860087
    Abstract: The present invention relates to a nitride semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a plurality of p-type nitride semiconductor segments formed on the nitride semiconductor layer and each formed lengthways from a first sidewall thereof, which is spaced apart from the source electrode, to a drain side; and a gate electrode formed to be close to the source electrode and in contact with the nitride semiconductor layer between the plurality of p-type semiconductor segments and portions of the p-type semiconductor segments extending in the direction of a source-side sidewall of the gate electrode aligned with the first sidewalls of the p-type nitride semiconductor segments is provided.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: October 14, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Hwan Park, Woo Chul Jeon, Ki Yeol Park, Seok Yoon Hong
  • Patent number: 8829568
    Abstract: An insulating layer, an undoped first GaN layer and an AlGaN layer are laminated in this order on a surface of a semiconductor substrate. A surface barrier layer formed by a two-dimensional electron gas is provided in an interface between the first GaN layer and the AlGaN layer. A recess (first recess) which reaches the first GaN layer but does not pierce the first GaN layer is formed in a surface layer of the AlGaN layer. A first high withstand voltage transistor and a control circuit are formed integrally on the aforementioned semiconductor substrate. The first high withstand voltage transistor is formed in the first recess and on a surface of the AlGaN layer. The control circuit includes an n-channel MOSFET formed in part of the first recess, and a depression type n-channel MOSFET formed on a surface of the AlGaN layer.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: September 9, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Katsunori Ueno
  • Patent number: 8815666
    Abstract: Provided is a power device. The power device may include a two-dimensional electron gas (2-DEG) layer in a portion corresponding to a gate electrode pattern since a second nitride layer is further formed on a lower portion of the gate electrode pattern after a first nitride layer is formed and thus, may be capable of performing a normally-OFF operation. Accordingly, the power device may adjust generation of the 2-DEG layer based on a voltage of a gate, and may reduce power consumption. The power device may regrow only the portion corresponding to the gate electrode pattern or may etch a portion excluding the portion corresponding to the gate electrode pattern and thus, a recess process may be omissible, a reproducibility of the power device may be secured, and a manufacturing process may be simplified.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae Hoon Lee
  • Patent number: 8809968
    Abstract: This invention relates to a semiconductor layer structure. The semiconductor layer structure described includes a substrate and a buffer layer deposited onto the substrate. The semiconductor layer structure is characterized in that a drain voltage threshold lower than the breakdown voltage threshold is determined by isolating ions that are selectively implanted in just one region of the substrate into the substrate, wherein charge can dissipate from the one contact through the buffer layer towards a substrate region without isolating ions, if the one potential deviates from the other at least by the drain voltage threshold, and wherein the substrate region without isolating ions is located underneath the one contact. The semiconductor layer structure described allows dissipation of currents induced by induction in blocking active structures without damaging the active structures.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: August 19, 2014
    Assignee: Forschungsverbund Berlin E.V.
    Inventors: Oliver Hilt, Rimma Zhytnytska, Hans-Joachim Würfl
  • Patent number: 8796738
    Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: August 5, 2014
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8785973
    Abstract: In an ultra high voltage lateral GaN structure having a 2DEG region extending between two terminals, an isolation region is provided between the two terminals to provide for reversible snapback.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: July 22, 2014
    Assignee: National Semiconductor Corporation
    Inventor: Vladislav Vashchenko
  • Patent number: 8772834
    Abstract: According to example embodiments, a HEMT includes a channel layer, a channel supply layer on the channel layer, a source electrode and a drain electrode spaced apart on the channel layer, a depletion-forming layer on the channel supply layer, and a plurality of gate electrodes on the depletion-forming layer between the source electrode and the drain electrode. The channel supply layer is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured to form a depletion region in the 2DEG. The plurality of gate electrodes include a first gate electrode and a second gate electrode spaced apart from each other.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-chul Jeon, Jong-seob Kim, Ki-yeol Park, Young-hwan Park, Jae-joon Oh, Jong-bong Ha, Jai-kwang Shin
  • Patent number: 8759169
    Abstract: The invention relates to a method for producing silicon semiconductor wafers and components having layer structures of III-V layers for integrating III-V semiconductor components. The method employs SOI silicon semiconductor wafers having varying substrate orientations, and the III-V semiconductor layers are produced in trenches (28, 43, 70) produced by etching within certain regions (38, 39), which are electrically insulated from each other, of the active semiconductor layer (24, 42) by means of a cover layer or cover layers (29) using MOCVD methods.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: June 24, 2014
    Assignee: X—FAB Semiconductor Foundries AG
    Inventors: Gabriel Kittler, Ralf Lerner
  • Patent number: 8754455
    Abstract: Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xuefeng Liu, Richard A. Phelps, Robert M. Rassel, Xiaowei Tian
  • Patent number: 8741707
    Abstract: A method for fabricating an edge termination, which can be used in conjunction with GaN-based materials, includes providing a substrate of a first conductivity type. The substrate has a first surface and a second surface. The method also includes forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The substrate, the first GaN epitaxial layer and the second GaN epitaxial layer can be referred to as an epitaxial structure.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: June 3, 2014
    Assignee: Avogy, Inc.
    Inventors: Donald R. Disney, Isik C. Kizilyalli, Linda Romano, Andrew Edwards, Hui Nie
  • Patent number: 8735909
    Abstract: There is provided a light emitting device in which low power consumption can be realized even in the case of a large screen. The surface of a source signal line or a power supply line in a pixel portion is plated to reduce a resistance of a wiring. The source signal line in the pixel portion is manufactured by a step different from a source signal line in a driver circuit portion. The power supply line in the pixel portion is manufactured by a step different from a power supply line led on a substrate. A terminal is similarly plated to made the resistance reduction. It is desirable that a wiring before plating is made of the same material as a gate electrode and the surface of the wiring is plated to form the source signal line or the power supply line.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Mai Osada
  • Patent number: 8697506
    Abstract: A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: April 15, 2014
    Assignee: General Electric Company
    Inventors: Vinayak Tilak, Alexei Vertiatchikh, Kevin Sean Matocha, Peter Micah Sandvik, Siddharth Rajan
  • Patent number: 8698201
    Abstract: A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer and a barrier layer over the channel layer includes forming a gate of a first dielectric, forming first sidewalls of a second dielectric on either side and adjacent to the gate, selectively etching into the buffer layer to form a mesa for the field effect transistor, depositing a dielectric layer over the mesa, planarizing the dielectric layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the dielectric layer over the mesa are on the same planarized surface, depositing metal on the planzarized surface, annealing to form the gate into a metal silicided gate, and etching to remove excess non-silicided metal.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: April 15, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Dean C. Regan, Keisuke Shinohara, Andrea Corrion, Ivan Milosavljevic, Miroslav Micovic, Peter J. Willadsen, Colleen M. Butler, Hector L. Bracamontes, Bruce T. Holden, David T. Chang
  • Patent number: 8680578
    Abstract: A III-nitride based field effect transistor obtains improved performance characteristics through manipulation of the relationship between the in-plane lattice constant of the interface of material layers. A high mobility two dimensional electron gas generated at the interface of the III-nitride materials permits high current conduction with low ON resistance, and is controllable through the manipulation of spontaneous polarization fields obtained according to the characteristics of the III-nitride material. The field effect transistor produced can be made to be a nominally on device where the in-plane lattice constants of the material forming the interface match. A nominally off device may be produced where one of the material layers has an in-plane lattice constant that is larger than that of the other layer material. The layer materials are preferably InAlGaN/GaN layers that are particularly tailored to the characteristics of the present invention.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: March 25, 2014
    Assignee: International Rectifier Corporation
    Inventor: Robert Beach
  • Patent number: 8674407
    Abstract: The present invention provides a semiconductor device having such a structure formed by sequentially laminating a lower barrier layer composed of lattice-relaxed AlxGa1-xN (0?x?1), a channel layer composed of InyGa1-yN (0?y?1) with compressive strain and a contact layer composed of AlzGa1-zN (0?z?1), wherein a two-dimensional electron gas is produced in the vicinity of an interface of said InyGa1-yN channel layer with said AlzGa1-zN contact layer; a gate electrode is formed so as to be embedded in the recessed portion with intervention of an insulating film, which recessed portion is formed by removing a part of said AlzGa1-zN contact layer by etching it away until said InyGa1-yN channel layer is exposed; and, ohmic electrodes are formed on the AlzGa1-zN contact layer. Thus, the semiconductor device has superior uniformity and reproducibility of the threshold voltage while maintaining a low gate leakage current, and is also applicable to the enhancement mode type.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: March 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuji Ando, Yasuhiro Okamoto, Kazuki Ota, Takashi Inoue, Tatsuo Nakayama, Hironobu Miyamoto
  • Patent number: 8664696
    Abstract: According to one embodiment, a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: March 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Wataru Saito, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno
  • Patent number: 8658482
    Abstract: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode 22 formed on the n-GaN cap layer 18; a gate electrode 26 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; a first protection layer 24 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; and a second protection layer 30 buried in an opening 28 formed in the first protection layer 24 between the gate electrode 26 and the drain electrode 22 down to the n-GaN cap layer 18 and formed of an insulation film different from the first protection layer.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 25, 2014
    Assignee: Fujitsu Limited
    Inventor: Toshihide Kikkawa
  • Patent number: 8653561
    Abstract: A III-nitride semiconductor electronic device comprises a semiconductor laminate provided on a primary surface of a substrate, a first electrode in contact with the semiconductor laminate, and a second electrode. The semiconductor laminate includes a channel layer and a barrier layer making a junction with the channel layer. The channel layer comprises first III-nitride semiconductor containing aluminum as a Group III constituent element, and the barrier layer comprises second III-nitride semiconductor containing aluminum as a Group III constituent element. The semiconductor laminate including first, second and third regions arranged along the primary surface, and the third region is located between the first region and the second region. The barrier layer includes first to third portions included in the first to third regions, respectively.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: February 18, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Hashimoto, Katsushi Akita, Yoshiyuki Yamamoto, Masaaki Kuzuhara, Norimasa Yafune
  • Patent number: 8653559
    Abstract: A field effect transistor (FET) includes source and drain electrodes, a channel layer, a barrier layer over the channel layer, a passivation layer covering the barrier layer for passivating the barrier layer, a gate electrode extending through the barrier layer and the passivation layer, and a gate dielectric surrounding a portion of the gate electrode that extends through the barrier layer and the passivation layer, wherein the passivation layer is a first material and the gate dielectric is a second material, and the first material is different than the second material.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: February 18, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Andrea Corrion, Karim S. Boutros, Mary Y. Chen, Samuel J. Kim, Rongming Chu, Shawn D. Burnham
  • Patent number: 8653558
    Abstract: In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate. The source and drain are on opposing sides of a channel region of a channel layer. The channel region is an upper portion of the channel layer. The channel layer comprises gallium nitride. The insulation layer is over the channel layer and has a first portion and a second portion. The first portion is nearer the drain than the source and has a first thickness. The second portion is nearer the source than drain and has the first thickness. The insulation layer has an opening through the insulation layer. The opening is between the first portion and the second portion.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: February 18, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bruce M. Green, Jenn Hwa Huang, Weixiao Huang
  • Patent number: 8648390
    Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: February 11, 2014
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart, Charles R. Eddy, Jr., Michael A. Mastro, Travis Anderson
  • Patent number: 8643062
    Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: February 4, 2014
    Assignee: Transphorm Inc.
    Inventors: Primit Parikh, Yuvaraj Dora, Yifeng Wu, Umesh Mishra, Nicholas Fichtenbaum, Rakesh K. Lal
  • Patent number: 8637902
    Abstract: There is provided a semiconductor device having a High Electron Mobility Transistor (HEMT) structure allowing for enhanced performance and a method of manufacturing the same. The semiconductor device includes a base substrate; a semiconductor layer provided on the base substrate; a source electrode, a gate electrode and a drain electrode provided on the semiconductor layer to be spaced apart from one another; and an ohmic-contact layer partially provided at an interface between the drain electrode and the semiconductor layer.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: January 28, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ki Yeol Park, Woo Chul Jeon, Young Hwan Park, Jung Hee Lee
  • Patent number: 8633094
    Abstract: A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: January 21, 2014
    Assignee: Power Integrations, Inc.
    Inventors: Jamal Ramdani, Linlin Liu, John Paul Edwards