Abstract: Semiconductor devices, such as transistors, FETs and HEMTs having a non-linear gate foot region and non-linear channel width are disclosed as well as methods of making and using such devices and the operational benefits of the devices.

Abstract: A bipolar junction transistor (BJT) is formed in a thin (less than about 20 nanometers) segment of a semiconductive material such as silicon where a lower portion of the semiconductive material has doping of a first conductivity type and forms a collector and an upper portion of the semiconductive material has doping of a second conductivity type and forms a base. Either a metal or a polysilicon emitter is formed on the base. An illustrative method for forming the BJT comprises forming first and second layers of a semiconductive material having first and second conductivity types, respectively; forming a hard mask on an upper surface of the second layer; using the hard mask to etch first and second channels in the semiconductive material on first and second opposing sides of the hard mask; removing the hard mask; and forming an emitter on the upper surface of the second layer.

Abstract: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.

Abstract: Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer.

Abstract: An insulating layer, an undoped first GaN layer and an AlGaN layer are laminated in this order on a surface of a semiconductor substrate. A surface barrier layer formed by a two-dimensional electron gas is provided in an interface between the first GaN layer and the AlGaN layer. A recess (first recess) which reaches the first GaN layer but does not pierce the first GaN layer is formed in a surface layer of the AlGaN layer. A first high withstand voltage transistor and a control circuit are formed integrally on the aforementioned semiconductor substrate. The first high withstand voltage transistor is formed in the first recess and on a surface of the AlGaN layer. The control circuit includes an n-channel MOSFET formed in part of the first recess, and a depression type n-channel MOSFET formed on a surface of the AlGaN layer.

Abstract: A Gallium Nitride (GaN) series of devices—transistors and diodes are disclosed—that have greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The devices also include a simpler and superior flip chip connection scheme and a means to reduce the thermal resistance. A simplified fabrication process is disclosed and the layout scheme which uses island electrodes rather than finger electrodes is shown to increase the active area density by two to five times that of conventional interdigitated structures. Ultra low on resistance transistors and very low loss diodes can be built using the island topology. Specifically, the present disclosure provides a means to enhance cost/effective performance of all lateral GaN structures.

Abstract: Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer.

Abstract: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.

Abstract: Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer.

Abstract: A nickelide material with reduced resistivity is provided as source/drain contact surfaces in both NMOS and PMOS technology. The nickelide material layer may be a ternary material such as NiInAs, and may be formed from a binary material previously formed in the source/drain regions. The binary material may be the channel material or it may be an epitaxial layer formed over the channel material. The same ternary nickelide material may be used as the source/drain contact surface in both NMOS and PMOS transistors. Various binary or ternary channel materials may be used for the NMOS transistors and for the PMOS transistors.

Abstract: Methods and apparatus for depositing thin films incorporating the use of a surfactant are described. Methods and apparatuses include a deposition process and system comprising multiple isolated processing regions which enables rapid repetition of sub-monolayer deposition of thin films. The use of surfactants allows the deposition of high quality epitaxial films at lower temperatures having low values of surface roughness. The deposition of Group III-V thin films such as GaN is used as an example.

Abstract: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.

Abstract: An improved semiconductor device manufactured using, for example, replacement gate technologies. The method includes forming a dummy gate structure having a gate stack and spacers. The method further includes forming a dielectric material adjacent to the dummy gate structure. The method further includes removing the spacers to form gaps, and implanting a halo extension through the gaps and into an underlying diffusion region.

Abstract: Using a laser lift-off (LLO) nonbonding technique, freestanding 4-layer GaN/AlGaN heterostructure membranes have been formed. A 4×4 mm mask was attached to the area at the center of the most-upper AlGaN layer was attached using a nonbonding material such as vacuum grease. A microscopic slide attached by an adhesive provided support for the structure during the laser lift-off without bonding to the layers. The vacuum grease and the mask isolated the adhesive from the structure at the center. The microscopic slide served as a temporarily nonbonding handle substrate. Laser lift-off of the sapphire substrate from the heterostructures was performed. The remaining adhesive served as a supporting frame for the structure making a free-standing 4-layer GaN/AGaN heterostructure membrane. Other frameless freestanding membranes can be fabricated for a variety of applications including further III-nitride growth, heterogeneous integration, packaging of micro systems, and thin film patterns.

Abstract: A method of manufacturing epitaxial material used for GaN based LED with low polarization effect, which includes steps of growing n-type InGaAlN layer composed of GaN buffer layer (2) and n-type GaN layer (3), low polarizing active layer composed of InGaAlN multi-quantum well structure polarized regulating and controlling layer (4) and InGaAlN multi-quantum well structure light emitting layer (5) and p-type InGaAlN layer (6) on sapphire or SiC substrate (1) in turn. The method adds InGaAlN multi-quantum well structure polarized regulating and controlling layer, thus reduces polarization effect of quantum well active region.

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.

Abstract: Methods are disclosed generally directed to design and synthesis of quantum dot nanoparticles having improved uniformity and size. In a preferred embodiment, a release layer is deposited on a semiconductor wafer. A heterostructure is grown on the release layer using epitaxial deposition techniques. The heterostructure has at least one layer of quantum dot material, and optionally, one or more layers of reflective Bragg reflectors. A mask is deposited over a top layer and reactive ion-beam etching applied to define a plurality of heterostructures. The release layer can be dissolved releasing the heterostructures from the wafer. Some exemplary applications of these methods include formation of fluorophore materials and high efficiency photon emitters, such as quantum dot VCSEL devices. Other applications include fabrication of other optoelectronic devices, such as photodetectors.

Abstract: A method of manufacturing a metal-oxide-semiconductor transistor device is disclosed, in which, an insulation region is formed to define the insulation region and an active region, wherein the active region is adjacent to the insulation region and electrically insulated by the insulation region. A selective epitaxial process is performed to form an epitaxial layer on the active region; wherein the epitaxial layer laterally extends onto a surface of a peripheral portion of the insulation region. Thereafter, a doped well is formed in the semiconductor substrate of the active region. A gate structure is formed on the epitaxial layer. Finally, a drain/source region is formed in the semiconductor substrate and the epitaxial layer at a side of the gate structure.

Abstract: A GaN related compound semiconductor element includes: a channel layer made of a GaN related compound semiconductor; and a source layer and a drain layer, which are disposed in a manner of sandwiching the channel layer. The source layer includes two adjacent ridge portions which are formed by selective growth. A source electrode is formed over the surface, sandwiched by the ridge portions, of the channel layer, and the surfaces of the respective two adjacent ridge portions. The selective-growth mask formed between the two ridge portions is removed by wet etching. In addition, as another embodiment, a gate electrode is formed in a manner that the direction of the longer dimension of the gate electrode is aligned with the m plane of the channel layer. Moreover, as still another embodiment, the channel layer has a multilayer structure in which a GaN layer doped with no impurity is used as an intermediate layer.