With One Or Zero Or Quasi-one Or Quasi-zero Dimensional Channel, E.g., In Plane Gate Transistor (ipg), Single Electron Transistor (set), Striped Channel Transistor, Coulomb Blockade Device (epo) Patents (Class 257/E21.408)
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Patent number: 9825161Abstract: Provided is a logical operation element that performs logical operations on three or more inputs using a single unique device. The logical operation element 30 is provided with an electrode 5A and the other electrode 5B that are provided to have a nanogap, a metal nanoparticle 7 arranged between the electrode 5A and the other electrode 5B in insulated state, and a plurality of gate electrodes 5C, 5D, 11, 11A, 11B for adjusting a charge of the metal nanoparticle 7. Electric current that flows between the electrode 5A and the other electrode 5B is controlled in accordance with the voltage applied to three or more of the gate electrodes 5C, 5D, 11, 11A, 11B.Type: GrantFiled: March 9, 2014Date of Patent: November 21, 2017Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Yutaka Majima, Toshiharu Teranishi, Kazuhiko Matsumoto, Kenzo Maehashi, Tomofumi Susaki, Yasuhide Ohno, Kosuke Matsuzaki, Guillaume Hubert Frederic Hackenberger
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Patent number: 9006791Abstract: A non-inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a nitrogen-polar III-Nitride first material, a barrier material layer, a two-dimensional hole gas in the barrier layer, and wherein the nitrogen-polar III-Nitride material comprises one or more III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is nitrogen-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the nitrogen-polar (001) face is the dominant face, growing a nucleation layer, growing a GaN epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal.Type: GrantFiled: January 31, 2014Date of Patent: April 14, 2015Assignee: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler, Karl D. Hobart
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Patent number: 8637374Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.Type: GrantFiled: February 8, 2012Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, Phaedon Avouris, Kevin K. Chan, Philip G. Collins, Richard Martel, Hon-Sum Philip Wong
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Patent number: 8124961Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.Type: GrantFiled: June 3, 2011Date of Patent: February 28, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Dae Suk, Kyoung-Hwan Yeo, Ming Li, Yun-Young Yeoh
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Patent number: 8048747Abstract: The present disclosure fabricates an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory device. The memory device is stacked with memory layers having a low aspect ratio. The memory device can be easily fabricated with only two extra masks for saving cost. The present disclosure uses a general method for mass-producing TFT and is thus fit for fabricating NAND-type or NOR-type flash memory to be used as embedded memory in a system-on-chip.Type: GrantFiled: November 2, 2010Date of Patent: November 1, 2011Assignee: National Applied Research LaboratoriesInventors: Min-Cheng Chen, Hou-Yu Chen, Chia-Yi Lin
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Patent number: 8022393Abstract: The disclosure pertains to a method for making a nanoscale filed effect transistor structure on a semiconductor substrate. The method comprises disposing a mask on a semiconductor upper layer of a multi-layer substrate, and removing areas of the upper layer not covered by the mask in a nanowire lithography process. The mask includes two conductive terminals separated by a distance, and a nanowire in contact with the conductive terminals across the distance. The nanowire lithography may be carried out using a deep-reactive-ion-etching, which results in an integration of the nanowire mask and the underlying semiconductor layer to form a nanoscale semiconductor channel for the field effect transistor.Type: GrantFiled: July 29, 2008Date of Patent: September 20, 2011Assignee: Nokia CorporationInventor: Alan Colli
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Patent number: 7955932Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.Type: GrantFiled: October 3, 2007Date of Patent: June 7, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Dae Suk, Kyoung-Hwan Yeo, Ming Li, Yun-Young Yeoh
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Patent number: 7944017Abstract: An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is less influenced by the diffusion of p type impurities from the gate region and the back gate region. Moreover, by continuously forming the impurity region from a portion below the source region to a portion below the drain region, the resistance value of a current path in the impurity region is substantially uniformed. Therefore, the IDSS is stabilized, the forward transfer admittance gm and the voltage gain Gv are improved, and the noise voltage Vno is decreased. Furthermore, the IDSS variation within a single wafer is suppressed.Type: GrantFiled: August 5, 2008Date of Patent: May 17, 2011Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Mitsuo Hatamoto, Yoshiaki Matsumiya
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Patent number: 7863651Abstract: A substrate is levitated a first distance over a mother substrate when a first group of Coulomb islands are charged. A second group of Coulomb islands are charged and increase a separation to a second distance. When the magnitude of the potential of all Coulomb islands is decreased, the separation decreases from the second distance to the first distance. All potentials associated with the Coulomb islands have decreased yet the distance of separation equals to the first distance. Increasing the number of Coulomb islands in a substrate can reduce the magnitude of potentials applied to the Coulomb islands thereby reducing the concern of voltage stress.Type: GrantFiled: December 7, 2007Date of Patent: January 4, 2011Assignee: MetaMEMS Corp.Inventor: Thaddeus John Gabara
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Patent number: 7749922Abstract: The present invention provides structures and devices comprising conductive segments and conductance constricting segments of a nanowire, such as metallic, superconducting or semiconducting nanowire. The present invention provides structures and devices comprising conductive nanowire segments and conductance constricting nanowire segments having accurately selected phases including crystalline and amorphous states, compositions, morphologies and physical dimensions, including selected cross sectional dimensions, shapes and lengths along the length of a nanowire. Further, the present invention provides methods of processing nanowires capable of patterning a nanowire to form a plurality of conductance constricting segments having selected positions along the length of a nanowire, including conductance constricting segments having reduced cross sectional dimensions and conductance constricting segments comprising one or more insulating materials such as metal oxides.Type: GrantFiled: May 4, 2006Date of Patent: July 6, 2010Assignee: The Board of Trustees of the University of IllinoisInventors: Alexey Bezryadin, Mikas Remeika
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Patent number: 7224026Abstract: Diode devices with superior and pre-settable characteristics and of nanometric dimensions, comprise etched insulative lines (8, 16, 18) in a conductive substrate to define between the lines charge carrier flow paths, formed as elongate channels (20) at least 100 nm long and less than 100 nm wide. The current-voltage characteristic of the diode devices are similar to a conventional diode, but both the threshold voltage (from 0V to a few volts) and the current level (from nA to ?A) can be tuned by orders of magnitude by changing the device geometry. Standard silicon wafers can be used as substrates. A full family of logic gates, such as OR, AND, and NOT, can be constructed based on this device solely by simply etching insulative lines in the substrate.Type: GrantFiled: April 18, 2002Date of Patent: May 29, 2007Assignee: The University of ManchesterInventors: Amin Song, Pär Omling