With Multiple Gate, One Gate Having Mos Structure And Others Having Same Or A Different Structure, I.e., Non Mos, E.g., Jfet Gate (epo) Patents (Class 257/E21.421)
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Publication number: 20090146209Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the sType: ApplicationFiled: December 10, 2008Publication date: June 11, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Miwako Akiyama, Yusuke Kawaguchi, Yoshihiro Yamaguchi
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Patent number: 7541300Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate having a silicon carbide substrate, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; a trench penetrating the second and the third semiconductor layers to reach the first semiconductor layer; a channel layer on a sidewall and a bottom of the trench; an oxide film on the channel layer; a gate electrode on the oxide film; a first electrode connecting to the third semiconductor layer; and a second electrode connecting to the silicon carbide substrate. A position of a boundary between the first semiconductor layer and the second semiconductor layer is disposed lower than an utmost lowest position of the oxide film.Type: GrantFiled: July 12, 2007Date of Patent: June 2, 2009Assignee: DENSO CORPORATIONInventors: Malhan Rajesh Kumar, Yuichi Takeuchi
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Patent number: 7538391Abstract: A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer.Type: GrantFiled: January 9, 2007Date of Patent: May 26, 2009Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Shreesh Narasimha, Edward J. Nowak, John J. Pekarik, Jeffrey W. Sleight, Richard Q. Williams
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Publication number: 20090127592Abstract: Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.Type: ApplicationFiled: November 19, 2007Publication date: May 21, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Badih El-Kareh, Leonard Forbes
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Publication number: 20090108356Abstract: A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.Type: ApplicationFiled: October 25, 2007Publication date: April 30, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Michael P. Chudzik, Rama Divakaruni, Geng Wang, Robert C. Wong, Haining S. Yang
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Publication number: 20090104745Abstract: In accordance with the present teachings, methods of making dual doped polysilicon gates are provided. The method can include providing a semiconductor structure including a plurality of polysilicon gates having a first critical dimension disposed over a dielectric layer and planarizing the plurality of polysilicon gates with a spin-on material to form a plurality of planarized polysilicon gates. The method can further include doping an exposed first region with p-type dopants to form a plurality of p-doped planarized polysilicon gates and doping an exposed second region with n-type dopants to form a plurality of n-doped planarized polysilicon gates. The method can also include removing the spin-on material to form a plurality of p-doped polysilicon gates and a plurality of n-doped polysilicon gates, wherein critical dimension of each of the plurality of n-doped polysilicon gates and the plurality of p-doped polysilicon gates are substantially similar to the first critical dimension.Type: ApplicationFiled: October 23, 2007Publication date: April 23, 2009Inventors: Hyesook Hong, Luigi Colombo, Jinhan Choi
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Publication number: 20090085119Abstract: Double gate transistor microelectronic device comprising: a support, a structure suited to forming at least one multi-branch channel and comprising a plurality of separate parallel semi-conductor rods and situated in a plane orthogonal to the principal plane of the support, the rods linking a first block suited to forming a source region of the transistor and a second block provided, suited to forming a drain region of the transistor, a first gate electrode situated on one side of said structure against the sides of said semi-conductor rods, a second gate electrode, separate from the first gate and situated on another side of the structure against the opposite sides of the rods, the semi-conductor rods and one or several insulating rods situated between the semi-conductor rods, separating the first gate electrode and the second gate electrode.Type: ApplicationFiled: September 26, 2008Publication date: April 2, 2009Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE, INSTITUT NATIONAL POLYTECHNIQUE DE GRENOBLEInventors: Thomas Ernst, Cecilia Dupre
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Patent number: 7511345Abstract: The present invention provides a MOS transistor device for providing ESD protection including at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further includes at least one isolation gate formed in at least one of the interleaved fingers. The device can further include a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.Type: GrantFiled: June 12, 2006Date of Patent: March 31, 2009Assignees: Sarnoff Corporation, Sarnoff EuropeInventors: Benjamin Van Camp, Gerd Vermont
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Publication number: 20090079004Abstract: This invention relates to an improved microelectronic method for making a double gate structure for a transistor, and particularly gate patterns (108a,128a,208a,228a,308a,328a) with a critical dimension less than the critical dimension of the transistor channel zone (104b). This method particularly includes a step to reduce double gate patterns, using isotropic etching. The invention also relates to a microelectronic device obtained using such a method.Type: ApplicationFiled: November 17, 2006Publication date: March 26, 2009Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUEInventors: Christophe LICITRA, Maud Vinet
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Publication number: 20090072316Abstract: Multiple gate transistors are provided with a dual stress layer for increased channel mobility and enhanced effective and saturated drive currents. Embodiments include transistors comprising a first stress layer under the bottom gate and a second stress layer overlying the top gate. Embodiments further include transistors with the bottom gate within or through the first stress layer. Methodology includes sequentially depositing stressed silicon nitride, nitride, oxide, amorphous silicon, and oxide layers on a substrate having a bottom oxide layer thereon, patterning to define a channel length, depositing a top nitride layer, patterning stopping on the stressed silicon nitride layer, removing the amorphous silicon layer, epitaxially growing silicon through a window in the substrate to form source, drain, and channel regions, doping, removing the deposited nitride and oxide layers, growing gate oxides, depositing polysilicon to form gates, growing isolation oxides, and depositing the top stress layer.Type: ApplicationFiled: September 14, 2007Publication date: March 19, 2009Applicant: Advanced Micro Devices, Inc.Inventor: Rasit O. TOPALOGLU
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Publication number: 20090072318Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device can include a gate insulating layer on a semiconductor substrate, a gate electrode on the gate insulating layer and source/drain regions in the semiconductor substrate at sides of the gate electrode. The gate electrode includes a first gate electrode and a second gate electrode on and electrically connected to the first gate electrode.Type: ApplicationFiled: September 17, 2008Publication date: March 19, 2009Inventor: Hyung Sun Yun
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Publication number: 20090068804Abstract: Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.Type: ApplicationFiled: November 19, 2008Publication date: March 12, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Sameer Pendharkar
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Patent number: 7494878Abstract: A method of manufacturing a MOS transistor device. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.Type: GrantFiled: October 25, 2006Date of Patent: February 24, 2009Assignee: United Microelectronics Corp.Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Neng-Kuo Chen, Shao-Ta Hsu, Teng-Chun Tsai, Chien-Chung Huang
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Publication number: 20090042349Abstract: A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.Type: ApplicationFiled: October 20, 2008Publication date: February 12, 2009Applicant: Freescale Semiconductor, Inc.Inventors: Erwin J. Prinz, Michael A. Sadd, Robert F. Steimle
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Patent number: 7488654Abstract: Disclosed are methods for forming FinFETs using a first hard mask pattern to define active regions and a second hard mask to protect portions of the insulating regions between active regions. The resulting field insulating structure has three distinct regions distinguished by the vertical offset from a reference plane defined by the surface of the active regions. These three regions will include a lower surface found in the recessed openings resulting from the damascene etch, an intermediate surface and an upper surface on the remaining portions of the lateral field insulating regions. The general correspondence between the reference plane and the intermediate surface will tend to suppress or eliminate residual gate electrode materials from this region during formation of the gate electrodes, thereby improving the electrical isolation between adjacent active regions and improving the performance of the resulting semiconductor devices.Type: GrantFiled: August 24, 2006Date of Patent: February 10, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Sung Kim, Tae-Young Chung
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Publication number: 20090026523Abstract: A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit.Type: ApplicationFiled: July 24, 2007Publication date: January 29, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert C. Wong, Haining S. Yang
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Publication number: 20090020819Abstract: Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.Type: ApplicationFiled: July 16, 2007Publication date: January 22, 2009Inventors: Brent A. Anderson, Andres Bryant, John J. Ellis-Monaghan, Edward J. Nowak
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Patent number: 7479421Abstract: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.Type: GrantFiled: September 28, 2005Date of Patent: January 20, 2009Assignee: Intel CorporationInventors: Jack T. Kavalieros, Justin K. Brask, Brian S. Doyle, Uday Shah, Suman Datta, Mark L. Doczy, Matthew V. Metz, Robert S. Chau
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Publication number: 20090017589Abstract: Dual-gate memory cells and tri-gate CMOS devices are integrated on a common substrate. A plurality of silicon bodies are formed from a monocrystalline silicon on the substrate to define a plurality of transistors including dual-gate memory cells, PMOS transistors, and NMOS transistors. An insulative layer is formed overlying the silicon body of the memory cell. A layer of a high-k dielectric and at least a metal layer cover the silicon bodies and their overlying layers. Next, gain regions of the transistors are filled with polysilicon. Thus, a gate is formed on the top surface and both sidewalls of a tri-gate transistor. Thereafter, the high-k dielectric and the metal layer overlying the insulative layer of the memory cell are removed to expose the insulative layer. Thus, two electrically-isolated gates of the memory cell are formed.Type: ApplicationFiled: September 12, 2008Publication date: January 15, 2009Inventors: Ibrahim Ban, Peter L.D. Chang
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Publication number: 20090014802Abstract: The semiconductor device according to the present invention is a Fin-FET that can substantially increase the channel width without unnecessarily elevating the height of the Fin. The Fin-FET has gate electrodes 22 formed on the upper surface, both left and right sides and the bottom surface of channel-forming semiconductor layer 11a formed by processing semiconductor substrate 11 into a fin shape; and a channel region the four surfaces of which are surrounded by gate electrodes 22.Type: ApplicationFiled: July 11, 2008Publication date: January 15, 2009Applicant: ELPIDA MEMORY, INC.Inventor: Keizo Kawakita
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Publication number: 20090001474Abstract: In one embodiment of the invention, a non-planar transistor includes a gate electrode and multiple fins. A trench contact is coupled to the fins. The contact bottom is formed above the substrate and does not directly contact the substrate. The contact bottom is higher than the gate top.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Inventors: Suman Datta, Titash Rakshit, Jack T. Kavalieros, Brian S. Doyle
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Publication number: 20080308861Abstract: A circuit has a fin supported by a substrate. A source is formed at a first end of the fin and a drain is formed at a second end of the fin. A pair of independently accessible gates are laterally spaced along the fin between the source and the drain. Each gate is formed around approximately three sides of the fin.Type: ApplicationFiled: June 18, 2007Publication date: December 18, 2008Applicant: Infineon Technologies Agam CampeonInventor: Muhammad Nawaz
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Patent number: 7465634Abstract: An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights.Type: GrantFiled: October 18, 2006Date of Patent: December 16, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Yong-Tian Hou, Jin Ying, Hun-Jan Tao
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Publication number: 20080303096Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes forming a transistor, the transistor including a fin having a first side and a second side opposite the first side. The transistor includes a first gate electrode disposed on the first side of the fin and a second gate electrode disposed on the second side of the fin. The method includes forming a silicide or germanide of a metal on the first gate electrode and the second gate electrode of the transistor. The amount of the metal of the silicide or germanide is substantially homogeneous over the first gate electrode and the second gate electrode proximate the fin.Type: ApplicationFiled: June 7, 2007Publication date: December 11, 2008Inventor: Thomas Schulz
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Publication number: 20080293203Abstract: A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.Type: ApplicationFiled: July 31, 2008Publication date: November 27, 2008Inventors: Jae-Man Yoon, Choong-Ho Lee, Chul Lee, Dong-Gun Park
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Patent number: 7449735Abstract: Disclosed is a complementary CMOS device having a first FET with sidewall channels and a second FET with a planar channel. The first FET can be a p-FET and the second FET can be an n-FET or vice versa. The conductor used to form the gate electrodes of the different type FETs is different and is pre-selected to optimize performance. For example, a p-FET gate electrode material can have a work function near the valence band and an n-FET gate electrode material can have a work function near the conduction band. The first gate electrodes of the first FET are located adjacent to the sidewall channels and the second gate electrode of the second FET is located above the planar channel. However, the device structure is unique in that the second gate electrode extends laterally above the first FET and is electrically coupled to the first gate electrodes.Type: GrantFiled: October 10, 2006Date of Patent: November 11, 2008Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Patent number: 7449766Abstract: Methods to form contact openings and allow the formation of self-aligned contacts for use in the manufacture of semiconductor devices are described. During formation of a multi-layered resist, a hard mask material is introduced beneath an anti-reflective coating to be used as an etch stop layer. The multi-layered resist is patterned and etched, to transfer the desired contact pattern to a substrate material, such as a silicon substrate, to form contact openings therein. The contact openings provide for the formation of self-aligned contacts therein.Type: GrantFiled: November 23, 2005Date of Patent: November 11, 2008Assignee: Micron Technology, Inc.Inventor: James L. Dale
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Publication number: 20080272439Abstract: Process for fabrication of MOS semiconductor structures and transistors such as CMOS structures and transistors with thin gate oxide, polysilicon surface contacts having thickness on the order of 500 Angstroms or less and with photo-lithographically determined distances between the gate surface contact and the source and drain contacts. Semiconductor devices having polysilicon surface contacts wherein the ratio of the vertical height to the horizontal dimension is approximately unity. Small geometry Metal-Oxide-Semiconductor (MOS) transistor with thin polycrystalline surface contacts and method and process for making the MOS transistor. MOS and CMOS transistors and process for making. Process for making transistors using Silicon Nitride layer to achieve strained Silicon substrate. Strained Silicon devices and transistors wherein fabrication starts with strained Silicon substrate.Type: ApplicationFiled: April 30, 2008Publication date: November 6, 2008Applicant: DSM SOLUTIONS, INC.Inventors: Ashok K. Kapoor, Madhukar B. Vora
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Patent number: 7439574Abstract: Provided are a silicon/oxide/nitride/oxide/silicon (SONOS) memory, a fabricating method thereof, and a memory programming method. The SONOS memory includes a substrate; a first insulating layer stacked on the substrate; a semiconductor layer, which is patterned on the first insulating layer in a predetermined shape, including source and drain electrodes separated by a predetermined interval; a second insulating layer located on the semiconductor layer between the source and drain electrodes; a memory layer, which is deposited on sides of a portion of the semiconductor layer between the source and drain electrodes and on sides and an upper surface of the second insulating layer, including electron transferring channels and an electron storing layer; and a gate electrode, which is deposited on a surface of the memory layer, for controlling transfer of electrons in the memory layer. The programming method may provide a large capacity, stable, multi-level memory.Type: GrantFiled: June 13, 2003Date of Patent: October 21, 2008Assignees: Samsung Electronics Co., Ltd., Seoul National UniversityInventors: Chung-woo Kim, Byung-gook Park, Jong-duk Lee, Yong-kyu Lee
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Publication number: 20080242024Abstract: To provide a semiconductor device using a Fin-FET and having a contact configuration such that the GIDL is reduced while limiting an increase in contact resistance, source and drain regions of the Fin-FET are formed by solid-phase diffusion positively utilizing impurity implantation after forming of contact holes 13 and oozing-out of an impurity from polysilicon contact plugs 14. Also, contact plugs 14 are extended to side surfaces of convex semiconductor layers 101a to form side wall portions 14a, thereby increasing the contact area.Type: ApplicationFiled: March 18, 2008Publication date: October 2, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Shigeru SUGIOKA
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Publication number: 20080242030Abstract: A method for manufacturing a fin transistor includes forming a trench by etching a semiconductor substrate. A flowable insulation layer is filled in the trench to form a field insulation layer defining an active region. The portion of the flowable insulation layer coming into contact with a gate forming region is etched so as to protrude the gate forming region in the active region. A protective layer over the semiconductor substrate is formed to fill the portion of the etched flowable insulation layer. The portion of the protective layer formed over the active region is removed to expose the active region of the semiconductor substrate. The exposed active region of the semiconductor substrate is cleaned. The protective layer remaining on the portion of the etched flowable insulation layer is removed. Gates are formed over the protruded gate forming regions in the active region.Type: ApplicationFiled: December 28, 2007Publication date: October 2, 2008Inventors: Dong Sun SHEEN, Seok Pyo SONG, Young Ho LEE
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Publication number: 20080237722Abstract: A transistor, comprising a first gate structure formed on a substrate, and having a stacked structure of a first gate electrode and a first gate hard mask, a first gate spacer formed on sidewalls of the first gate structure, a second gate structure having a stacked structure of a second gate electrode and a second gate hard mask, the second gate structure surrounding both sidewalls and top surfaces of the first gate structure and the first gate spacer, and a second gate spacer formed on sidewalls of the second gate structure.Type: ApplicationFiled: December 26, 2007Publication date: October 2, 2008Inventor: In-Chan Lee
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Publication number: 20080237731Abstract: A semiconductor device includes a semiconductor layer formed on an insulation layer and having an MOS (Metal Oxide Semiconductor) transistor area and a bi-polar transistor area; an MOS transistor formed in the MOS transistor area; and a bi-polar transistor formed in the bi-polar transistor area. The MOS transistor includes a source area of a second conductive type; a drain area of the second conductive type; and a channel area of a first conductive type. The MOS transistor further includes a gate electrode formed on the channel area with a first oxide layer inbetween. The bi-polar transistor includes a collector area of the second conductive type; an emitter area of the second conductive type; and a base area of the first conductive type. The bi-polar transistor further includes a dummy pattern formed on the base area with a second oxide layer inbetween.Type: ApplicationFiled: March 14, 2008Publication date: October 2, 2008Inventors: Koichi Kishiro, Koji Yuki
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Publication number: 20080237730Abstract: A semiconductor device includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first gate electrode formed; first impurity diffused areas; and first sidewall portions. The first sidewall portions include a first lower insulation film and a first charge accumulation film. The second field effect transistor includes a second gate electrode; second impurity diffused areas; and second sidewall portions. The second sidewall portions include a second lower insulation film and a second charge accumulation film. The first lower insulation film contains one of a silicon thermal oxide film and a non-doped silicate glass, and the second lower insulation film contains a non-doped silicate glass. The second sidewall portions have a width along a gate longitudinal direction larger than that of the first sidewall portions. The second lower insulation film has a thickness larger than that of the first lower insulation film.Type: ApplicationFiled: March 13, 2008Publication date: October 2, 2008Inventors: Katsutoshi Saeki, Yoshitaka Satou
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Publication number: 20080233698Abstract: A semiconductor device comprises a semiconductor substrate, a MOSFET including a double gate structure provided on the semiconductor substrate, and an isolation region for isolating the MOSFET from other elements comprising a trench provided on the surface of the semiconductor substrate and an insulator provided in the trench, a part of the isolation region in the trench around the MOSFET having a bottom deeper than other part of the isolation region.Type: ApplicationFiled: March 10, 2008Publication date: September 25, 2008Inventors: Tsutomu Sato, Ichiro Mizushima
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Publication number: 20080233694Abstract: A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n-type dopant. The NMOS device may be doped with either an n-type or a p-type dopant. The work function of the CMOS device is set by the material selection of the gate dielectric materials. A polysilicon depletion effect is reduced or avoided.Type: ApplicationFiled: April 25, 2008Publication date: September 25, 2008Inventor: Hong-Jyh Li
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Publication number: 20080233699Abstract: A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.Type: ApplicationFiled: June 5, 2008Publication date: September 25, 2008Inventors: Roger Allen Booth, William Paul Hovis, Jack Allan Mandelman
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Publication number: 20080224222Abstract: A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV.Type: ApplicationFiled: December 27, 2007Publication date: September 18, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Se-Aug JANG, Heung-Jae CHO, Kwan-Yong LIM, Tae-Yoon KIM
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Publication number: 20080224224Abstract: A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to the shorter gate, the total gate capacitance is reduced, which is directly reflected in an improved switching speed of the device. In addition to the advantage of an improved switching speed, the transistor also has a processing advantage (no alignment of the gate with the drain is necessary), as well as a performance improvement (the ambipolar behavior of the TFET is reduced).Type: ApplicationFiled: March 7, 2008Publication date: September 18, 2008Applicants: Interuniversitair Microelektronica Centrum vzw (IMEC), Katholieke Universiteit LeuvenInventors: William G. Vandenderghe, Anne S. Verhulst
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Publication number: 20080217616Abstract: A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.Type: ApplicationFiled: March 4, 2008Publication date: September 11, 2008Inventors: Yong-hoon Son, Si-young Choi, Jong-wook Lee
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Publication number: 20080217664Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.Type: ApplicationFiled: March 8, 2007Publication date: September 11, 2008Inventors: Xiaoju Wu, Fan-Chi Frank Hou, Pinghai Hao
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Publication number: 20080203440Abstract: A method of fabricating a semiconductor device having a pair of shallow silicided source and drain junctions with minimal leakage is disclosed. The semiconductor device typically has a MISFET structure with NiSi regions partially making up the source and drain regions. The fabrication method includes the steps of providing silicon surfaces having Si{110} crystal planes on both sides of this gate electrode and forming a plurality of nickel silicide (NiSi) regions, each having a rectangular planar shape whose shorter sides being equal or less than 0.5 ?m in length and running along a Si<100> direction.Type: ApplicationFiled: December 13, 2007Publication date: August 28, 2008Inventor: Masakatsu TSUCHIAKI
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Publication number: 20080203476Abstract: The invention relates to a semiconductor device (10) consisting of a substrate (11) and a semiconductor body (2) comprising a strip-shaped semiconductor region (3,3A,3B) of silicon in which a field effect transistor is formed, wherein a source region (4) of a first conductivity type, a channel region (33) of a second conductivity type opposed to the first, and a drain region (5) of the first conductivity type are arranged in succession, successively, seen in the longitudinal direction of the strip-shaped semiconductor region (3,3A,3B), and wherein the channel region (33) is provided with a gate dielectric (6), on which a first gate electrode (7) is present on a first vertical side of the strip-shaped semiconductor region (3,3A,3B), which gate electrode (7) is provided with a first connection region (7A), and on which a second gate electrode (8) is present on a second vertical side of the strip-shaped semiconductor region (3,3A,3B) positioned opposite the first vertical side, which second gate electrode (8) isType: ApplicationFiled: December 19, 2005Publication date: August 28, 2008Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventor: Youri V. Ponomarev
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Publication number: 20080199995Abstract: A method of forming a trench gate field effect transistor includes the following processing steps. Trenches are formed in a semiconductor substrate. The semiconductor substrate is annealed in an ambient including hydrogen gas. A dielectric layer lining at least the sidewalls of the trenches is formed. During the time between annealing and forming the dielectric layer, the semiconductor substrate is maintained in an inert environment to prevent formation of native oxide along sidewalls of the trenches prior to forming the dielectric layer.Type: ApplicationFiled: February 15, 2007Publication date: August 21, 2008Inventors: Debra Susan Woolsey, Joelle Sharp, Tony Lane Olsen, Gordon K. Madson
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Publication number: 20080194069Abstract: The invention relates to a method of manufacturing a semiconductor device (1.Type: ApplicationFiled: August 10, 2005Publication date: August 14, 2008Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Radu Surdeanu, Erwin Hijzen, Michael Antoine Zandt, Raymond Josephus Hueting
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Publication number: 20080185654Abstract: An electronic device can include a semiconductor fin with a first gate electrode adjacent to a first wall, and a second gate electrode adjacent to a second wall. In one embodiment, a conductive member can be formed overlying the semiconductor fin, and a portion of the conductive member can be reacted to form the first and second gate electrodes. In another embodiment, a patterned masking layer can be formed including a masking member over a gate electrode layer, and portion of the masking member overlying the semiconductor fin can be removed. In still another embodiment, a first fin-type transistor structure can include the semiconductor fin, the first and second gate electrodes, and a first insulating cap. The electronic device can also include a second fin-type transistor structure having a second insulating cap thicker than the first insulating cap.Type: ApplicationFiled: February 2, 2007Publication date: August 7, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Leo Mathew, Brian J. Goolsby, Tab A. Stephens
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Publication number: 20080169511Abstract: The invention relates to a method of fabricating a CMOS device, comprising providing a semiconductor substrate (101) having therein a layer of insulating material (102), the method comprising providing a layer (106) of a first material over the insulating layer (102), the thickness of the layer (106) of the first material being less in a first region (103) for supporting a first active device than in a second region (104) for supporting a second active device. A layer (107) of a second material is then deposited over the layer (106) of a first material, and the structure is then subjected to a thermal treatment to alloy the first and second materials. The portion of the layers over the first region is entirely alloyed, whereas the portion of the layers over the second region is not, so that a portion (109) of the layer (106) of the first material remains.Type: ApplicationFiled: August 1, 2005Publication date: July 17, 2008Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Markus Muller, Peter Stolk
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Publication number: 20080164528Abstract: A lateral double-gate FET structure with sub-lithographic source and drain regions is disclosed. The sub-lithographic source and drain regions are defined by a sacrificial spacer. Self-aligned metal-semiconductor alloy and metal contacts are made to the sub-lithographic source and drain using conventional silicon processing.Type: ApplicationFiled: January 10, 2007Publication date: July 10, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guy M. Cohen, Paul M. Solomon
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Publication number: 20080164535Abstract: A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer.Type: ApplicationFiled: January 9, 2007Publication date: July 10, 2008Inventors: Dureseti Chidambarrao, Shreesh Narasimha, Edward J. Nowak, John J. Pekarik, Jeffrey W. Sleight, Richard Q. Williams
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Publication number: 20080157182Abstract: Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.Type: ApplicationFiled: October 31, 2007Publication date: July 3, 2008Inventors: Seung-hwan Song, Suk-pil Kim, Yoon-dong Park, Won-joo Kim, June-mo Koo, Kyoung-Iae Cho, Jae-Woong Hyun, Sung-jae Byun