Abstract: A method for fabricating a semiconductor device includes forming first, second, and third device structures in a semiconductor substrate. Each device structure includes a first film, a second film over the first film, and a third film over the second film. The first and third device structures are device isolation structures. A portion of the second device structure is etched to define a bit line contact region, the bit line contact region extending from an upper surface of the second device structure to a lower surface of the second device structure. The second film of the second device structure is etched to define an under-cut space between the first and second films. A semiconductor layer is formed within the under-cut space and the bit line contact region. The third film of the second device structure is etched or removed to define a recess, the recess defining a gate region. A gate structure is formed at least partly within the recess.

Abstract: Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench.

Abstract: A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having a first active region and a second active region. The latter has a second recess region formed in a lower portion of the active region than the former. A step gate pattern is formed on a border region between the first active region and the second active region. The gate pattern has a step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.

Abstract: A nonvolatile memory device is provided which includes a floating gate having a lower portion formed in a trench defined in a surface of a substrate and an upper portion protruding above the surface of the substrate from the lower portion. A gate insulating layer is formed along an inner wall of the trench and interposed between the trench and the lower portion of the floating gate. A source region is formed in the substrate adjacent a first sidewall of the trench. A control gate having a first portion is formed over the surface of the substrate adjacent a second sidewall of the trench, and a second portion is formed over the upper portion of the floating gate and extending from the first portion. The first sidewall of the trench is opposite the second sidewall of the trench.

Abstract: A semiconductor device with a recessed channel and a method of fabricating the same are provided. The semiconductor device comprises a substrate, a gate, a source, a drain, and a reverse spacer. The substrate comprises a recessed trench. The gate is formed above the recessed trench and extends above the substrate. The gate further comprises a polysilicon layer and a conductive layer; wherein the polysilicon layer is formed inside the recessed trench of the substrate, and the conductive layer is formed above the polysilicon layer and extends above the substrate. Moreover, the width of the conductive layer increases gradually bottom-up. The source and the drain are formed respectively at two sides of the gate. The reverse spacer is formed above the polysilicon layer and against the sidewall of the conductive layer.

Abstract: A semiconductor device and a method of manufacturing the same capable of preventing a not open fail of a landing plug contact caused by the leaning of a gate. The method includes the steps of preparing a semiconductor substrate, forming first recesses by etching an active area of the semiconductor substrate, filling a conductive layer in the first recesses, forming a second recess by etching a predetermined part of the active area, forming under stepped gates, forming a gate insulating layer on a surface of the semiconductor substrate, forming a channel layer on the gate insulating layer, forming source/drain areas in the semiconductor substrate, forming an interlayer insulating film on an entire surface of the semiconductor substrate, and forming a landing plug in the interlayer insulating film such that the landing plug makes contact with the source/drain areas, respectively.

Abstract: A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.

Abstract: A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to form a plurality of recess structures each of which has a flat bottom portion with a critical dimension (CD) larger than that of a top portion; and sequentially forming a gate oxide layer and a metal layer on the recess structures; and patterning the gate oxide layer and the metal layer to form a plurality of gate structures.

Abstract: A semiconductor device, including a semiconductor region of the first conduction type which is formed on a semiconductor substrate; a gate electrode at least part of which is present within a trench which is selectively formed in part of the semiconductor region, and an extended top end portion of which is formed to have a wide width via a stepped portion; a gate insulating film which is formed between the trench and the gate electrode along a wall surface of the trench; a base layer of the second conduction type which is provided on the semiconductor region via the gate insulating film so as to enclose a side wall except a bottom portion of the trench; a source region of the first conduction type which is formed adjacent to the gate insulating film outside the trench in the vicinity of a top surface of the base layer; and an insulating film which is formed at least partially between a bottom surface of the top end portion and a top surface of the source region and which is formed so as to have a film thickne

Abstract: A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region.

Abstract: Embodiments of the invention include sequentially forming a pad oxide film and a mask film on a semiconductor substrate, and then forming an opening for partially exposing the pad oxide film. An undercut region is formed using the mask film as an etch mask, exposing a partial surface of the substrate. A spacer is formed surrounding both sidewalls of the mask film, and a recess is formed in the substrate. A gate oxide film, a gate electrode, a gate insulation film, a gate spacer, and source and drain regions are also formed. A resultant transistor structure has a small open critical dimension that improves process margin and provides uniformity to the recess depth, and removes a requirement that a bottom critical dimension of a subsequently formed self-aligned contact should be small. Degradation of the gate oxide film and increases in leakage current may also be prevented.

Abstract: Disclosed is a method for manufacturing a semiconductor device. The method includes the steps of preparing a semiconductor substrate, forming a buffer oxide layer, forming a hard mask layer on the buffer oxide layer, etching an exposed portion of the buffer oxide layer by using the hard mask layer, etching a substrate active area of an exposed recess channel forming area by using the isolation layer as an etching mask, removing a remaining buffer oxide layer, sequentially forming a gate oxide layer and a gate conductive layer on a resultant structure, etching the gate conductive layer and the gate oxide layer, thereby forming a gate, and forming a source/drain area in the substrate active area.

Abstract: A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.