Gate Comprising Layer With Ferroelectric Properties (epo) Patents (Class 257/E21.436)
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Patent number: 11424253Abstract: An illustrative device disclosed herein includes a semiconductor substrate. The substrate includes a source region, a drain region and a channel region. The channel region is arranged between the source region and the drain region. A gate insulation layer is provided over the channel region. A floating gate electrode is provided over the gate insulation layer. A layer of a ferroelectric material is provided over the floating gate electrode. A top electrode is provided over the layer of ferroelectric material. A projected area of the top electrode onto a plane that is perpendicular to a thickness direction of the semiconductor substrate is smaller than a projected area of the floating gate electrode onto the plane.Type: GrantFiled: January 8, 2018Date of Patent: August 23, 2022Assignees: NaMLab gGmbH, Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.Inventors: Johannes Mueller, Stefan Mueller, Stefan Flachowsky
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Patent number: 10707319Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. The method includes depositing a dielectric layer on a substrate, followed by deposition of a capping layer in-situ over the dielectric layer prior to any high temperature processing.Type: GrantFiled: March 10, 2016Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
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Patent number: 8822234Abstract: A method of fabricating a miniaturized semiconductor device so as to form MTJ elements therein include the steps of depositing a magnetic tunnel junction (MTJ) precursor layer on a substrate and planarizing the precursor layer; forming a sacrificial and patternable dielectric layer on the MTJ precursor layer; patterning the sacrificial dielectric layer in accordance with predetermined placements and shapes of a to-be-formed hard mask, the patterning forming corresponding openings in the sacrificial dielectric layer; depositing an etch-resistant conductive material such as Cu in the openings for example by way of plating, and selectively removing the sacrificial dielectric layer so as to leave behind the etch-resistant conductive material in the form of a desired hard mask. Using the hard mask to etch and thus pattern the MTJ precursor layer so as to form MTJ elements having desired locations, sizes and shapes.Type: GrantFiled: December 20, 2012Date of Patent: September 2, 2014Assignees: Semiconductor Manufacturing International (Beijing) CorporationInventors: Xinpeng Wang, Haiyang Zhang
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Patent number: 8809971Abstract: A semiconductor component comprising a semiconductor body, a channel zone in the semiconductor body, a channel control electrode adjacent to the channel zone, and a dielectric layer between the channel zone and the channel control electrode, wherein the dielectric layer has a relative dielectric constant ?r with a negative temperature coefficient.Type: GrantFiled: August 23, 2010Date of Patent: August 19, 2014Assignee: Infineon Technologies Austria AGInventors: Hans-Joachim Schulze, Frank Pfirsch
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Patent number: 8748957Abstract: A coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A magnetic oxide layer is formed on the cobalt by annealing at temperatures on the order of 1000° K to provide a few monolayer thick layer. Where the gate is cobalt, the resulting magnetic oxide is Co3O4(111). Other magnetic materials and oxides may be employed. A few ML field of graphene is deposited on the cobalt (III) oxide by molecular beam epitaxy, and a source and drain are deposited of base material. The resulting device is scalable, provides high on/off rates, is stable and operable at room temperature and easily fabricated with existing technology.Type: GrantFiled: January 5, 2012Date of Patent: June 10, 2014Assignee: Quantum Devices, LLCInventors: Jeffry Kelber, Peter Dowben
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Patent number: 8729614Abstract: The present disclosure relates to a flexible nonvolatile ferroelectric memory device, a 1T-1R (1Transistor-1Resistor) flexible ferroelectric memory device, and a manufacturing method for the same.Type: GrantFiled: May 25, 2011Date of Patent: May 20, 2014Assignee: Sungkyunkwan University Foundation for Corporate CollaborationInventors: Jong-Hyun Ahn, Jonghyun Rho
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Patent number: 8698218Abstract: A magnetoresistive memory element has a free layer, and a write current path aligned with a free layer plane. The memory element has a pinned layer with a magnetization direction aligned with that of the free layer. A barrier layer is disposed between the free layer and the pinned layer. The free, barrier and pinned layers together form a layer stack that has a read current path that extends through the layer stack and that is not aligned with the write current path in the free layer.Type: GrantFiled: October 13, 2010Date of Patent: April 15, 2014Assignee: Seagate Technology LLCInventor: Mark William Covington
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Publication number: 20130175588Abstract: A coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A magnetic oxide layer is formed on the cobalt by annealing at temperatures on the order of 1000° K to provide a few monolayer thick layer. Where the gate is cobalt, the resulting magnetic oxide is Co3O4 (111). Other magnetic materials and oxides may be employed. A few ML field of graphene is deposited on the cobalt (III) oxide by molecular beam epitaxy, and a source and drain are deposited of base material. The resulting device is scalable, provides high on/off rates, is stable and operable at room temperature and easily fabricated with existing technology.Type: ApplicationFiled: January 5, 2012Publication date: July 11, 2013Applicant: QUANTUM DEVICES CORP.Inventors: JEFFRY KELBER, PETER DOWBEN
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Patent number: 8476721Abstract: A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.Type: GrantFiled: April 18, 2011Date of Patent: July 2, 2013Assignee: Seagate Technology LLCInventors: Yang Li, Insik Jin, Harry Liu, Song S. Xue, Shuiyuan Huang, Michael X. Tang
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Patent number: 8455935Abstract: A ferroelectric film comprising polyaminodifluoroborane (PADFB). Also a memory device utilizing the ferroelectric film, a method of fabricating a ferroelectric polymer and a ferroelectric solution.Type: GrantFiled: May 29, 2009Date of Patent: June 4, 2013Assignees: Sony Corporation, Agency for Science, Technology, and ResearchInventors: Takehisa Ishida, Sunil Madhukar Bhangale, Han Hong, Christina Li Lin Chai
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Patent number: 8361858Abstract: The growth rate in a selective epitaxial growth process for depositing a threshold adjusting semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by performing a plasma-assisted etch process prior to performing the selective epitaxial growth process. For example, a mask layer may be patterned on the basis of the plasma-assisted etch process, thereby simultaneously providing superior device topography during the subsequent growth process. Hence, the threshold adjusting material may be deposited with enhanced thickness uniformity, thereby reducing overall threshold variability.Type: GrantFiled: January 25, 2010Date of Patent: January 29, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Stephan Kronholz, Andreas Naumann, Gunda Beernink
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Publication number: 20120056253Abstract: A semiconductor memory device according to the present embodiment includes a semiconductor substrate, a select transistor, a lower electrode, a magnetic tunnel junction element, a first protection film, an upper electrode, and a second protection film. The select transistor is formed on the semiconductor substrate. The lower electrode is electrically connected to one diffusion layer of the select transistor. The magnetic tunnel junction element is provided on the lower electrode. The first protection film is provided on a side surface of the magnetic tunnel junction element. The upper electrode is provided on the magnetic tunnel junction element and the first protection film. The second protection film is provided on side surfaces of the upper electrode, the first protection film, and the lower electrode.Type: ApplicationFiled: November 10, 2010Publication date: March 8, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masayoshi IWAYAMA, Hiroyuki Kanaya
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Publication number: 20110316059Abstract: The present disclosure relates to a flexible nonvolatile ferroelectric memory device, a 1T-1R (1Transistor-1Resistor) flexible ferroelectric memory device, and a manufacturing method for the same.Type: ApplicationFiled: May 25, 2011Publication date: December 29, 2011Applicant: Sungkyunkwan University Foundation for Corporate CollaborationInventors: Jong-Hyun Ahn, Jonghyun Rho
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Publication number: 20110207279Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations such as an LDD or a PKT implant, are carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx with a low wet etch rate in H3PO4 and dilute HF acid. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.Type: ApplicationFiled: February 25, 2010Publication date: August 25, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Pin LIN, Wen-Sheh HUANG, Tian-Choy GAN, Chia-Lung HUNG, Hsien-Chin LIN, Shyue-Shyh LIN
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Patent number: 7932547Abstract: A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a bottom word line formed in the insulating layer so as to be enclosed by the insulating layer, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.Type: GrantFiled: March 9, 2007Date of Patent: April 26, 2011Assignee: Hynix Semiconductor Inc.Inventor: Hee Bok Kang
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Patent number: 7825445Abstract: A magnetoresistive memory element has a free layer, and a write current path aligned with a free layer plane. The memory element has a pinned layer with a magnetization direction aligned with that of the free layer. A barrier layer is disposed between the free layer and the pinned layer. The free, barrier and pinned layers together form a layer stack that has a read current path that extends through the layer stack and that is not aligned with the write current path in the free layer.Type: GrantFiled: November 29, 2007Date of Patent: November 2, 2010Assignee: Seagate Technology LLCInventor: Mark William Covington
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Patent number: 7816150Abstract: A method for fabricating a semiconductor device includes the steps of forming a first ferroelectric film over a lower electrode, crystallizing the first ferroelectric film, forming a second ferroelectric film in an amorphous state over the first ferroelectric film so as to fill voids existing on a surface of the first ferroelectric film, and forming an upper electrode over the second ferroelectric film of the amorphous state, wherein the crystallizing step of the first ferroelectric film is conducted by a thermal annealing process at a temperature of 585° C. or higher.Type: GrantFiled: November 1, 2007Date of Patent: October 19, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Ko Nakamura
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Patent number: 7759713Abstract: A tunneling element includes a thin film layer of ferroelectric material and a pair of dissimilar electrically-conductive layers disposed on opposite sides of the ferroelectric layer. Because of the dissimilarity in composition or construction between the electrically-conductive layers, the electron transport behavior of the electrically-conductive layers is polarization dependent when the tunneling element is below the Curie temperature of the layer of ferroelectric material. The element can be used as a basis of compact 1R type non-volatile random access memory (RAM). The advantages include extremely simple architecture, ultimate scalability and fast access times generic for all ferroelectric memories.Type: GrantFiled: March 6, 2006Date of Patent: July 20, 2010Assignee: UT-Battelle, LLCInventors: Sergei V. Kalinin, Hans M. Christen, Arthur P. Baddorf, Vincent Meunier, Ho Nyung Lee
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Publication number: 20100178715Abstract: An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substantially zero in the absence of an external field, and in which magnetization is roughly proportional to an external field until reaching a saturation value. In one embodiment, a separate storage layer is formed above, below, or adjacent to the MTJ and has uniaxial anisotropy with a magnetization direction along its easy axis which parallels the first axis. In a second embodiment, the storage layer is formed on a non-magnetic conducting spacer layer within the MTJ and is patterned simultaneously with the MTJ. The SP free layer may be multiple layers or laminated layers of CoFeB. The storage layer may have a SyAP configuration and a laminated structure.Type: ApplicationFiled: March 16, 2010Publication date: July 15, 2010Inventors: Po-Kang Wang, Yimin Guo, Cheng T. Horng, Tai Min, Ru-Ying Tong
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Publication number: 20100176427Abstract: A method of manufacturing a semiconductor device. The method comprises fabricating a ferroelectric capacitor. The capacitor's fabrication includes forming conductive and ferroelectric material layers on a semiconductor substrate, forming a hardmask layer on the conductive and ferroelectric material layers, forming an organic bottom antireflective coating layer on the hardmask layer, and, patterning the organic bottom antireflective coating layer. Seasoning in a hardmask etching chamber is substantially unaffected by the patterning.Type: ApplicationFiled: January 13, 2009Publication date: July 15, 2010Applicant: Texas Instruments IncorporatedInventor: Francis Gabriel Celii
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Patent number: 7645617Abstract: A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.Type: GrantFiled: March 14, 2007Date of Patent: January 12, 2010Assignee: Hynix Semiconductor, Inc.Inventor: Hee Bok Kang
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Patent number: 7605436Abstract: A method contains the steps of (a) heating a silicon substrate in a reaction chamber; and (b) supplying film-forming gas containing source gas, nitridizing gas, and nitridation enhancing gas to a surface of the heated silicon substrate, to deposit on the silicon substrate an Hf1-xAlxO:N film (0.1<x<0.3) having a higher specific dielectric constant than that of silicon oxide, and incorporating N, by thermal CVD. The method can form an oxide film of Hf1-xAlxO (0<x<0.3) having desired characteristics, as a gate insulation film.Type: GrantFiled: July 3, 2008Date of Patent: October 20, 2009Assignee: Fujitsu LimitedInventor: Masaomi Yamaguchi
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Patent number: 7524727Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.Type: GrantFiled: December 30, 2005Date of Patent: April 28, 2009Assignee: Intel CorporationInventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
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Patent number: 7517702Abstract: A method for making an electronic device may include forming a poled superlattice comprising a plurality of stacked groups of layers and having a net electrical dipole moment. Each group of layers of the poled superlattice may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the poled superlattice.Type: GrantFiled: December 21, 2006Date of Patent: April 14, 2009Assignee: MEARS Technologies, Inc.Inventors: Samed Halilov, Xiangyang Huang, Ilija Dukovski, Jean Augustin Chan Sow Fook Yiptong, Robert J. Mears, Marek Hytha, Robert John Stephenson
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Patent number: 7449346Abstract: A method of manufacturing a ferroelectric thin film with good crystallinity and improved surface roughness includes: forming on a substrate a metal nitride-based precursor layer containing one selected from the group consisting of TiN, ZrxTi(1-x)N (0<x<1), FeN, and NbN; forming on the metal nitride-based precursor layer a mixed gas atmosphere containing oxygen (O2) and one reactive gas selected from the group consisting of PbO(g), Bi2O3(g), and K2O(g); annealing the metal nitride-based precursor layer in the mixed gas atmosphere and forming a ferroelectric thin film containing one selected from the group consisting of PbTiO3, PbZrxTi(1-x)O3 (0<x<1), Bi2Ti2O7, Bi4Ti3O12, BiFeO3, and KNbO3.Type: GrantFiled: September 8, 2006Date of Patent: November 11, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Simon Buehlmann
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Patent number: 7432150Abstract: A method of manufacturing a magnetoelectronic device includes providing an electrically conducting material and an electrically insulating material adjacent to at least a portion of the electrically conducting material, and implanting a magnetic material into the electrically insulating material. The magnetic material increases the magnetic permeability of the electrically insulating material. The implant may be a blanket or a targeted implant.Type: GrantFiled: February 10, 2006Date of Patent: October 7, 2008Assignee: EverSpin Technologies, Inc.Inventors: Mark A. Durlam, Gloria J. Kerszykowski, Nicholas D. Rizzo, Eric J. Salter, Loren J. Wise
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Patent number: 7410812Abstract: A method contains the steps of (a) heating a silicon substrate in a reaction chamber; and (b) supplying film-forming gas containing source gas, nitridizing gas, and nitridation enhancing gas to a surface of the heated silicon substrate, to deposit on the silicon substrate an Hf1-xAlxO:N film (0.1<x<0.3) having a higher specific dielectric constant than that of silicon oxide, and incorporating N, by thermal CVD. The method can form an oxide film of Hf1-xAlxO (0<x<0.3) having desired characteristics, as a gate insulation film.Type: GrantFiled: March 25, 2005Date of Patent: August 12, 2008Assignee: Fujitsu LimitedInventor: Masaomi Yamaguchi
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Patent number: 7390679Abstract: A method for manufacturing a ferroelectric capacitor, includes the steps of: forming a ferroelectric capacitor layer having a lower electrode layer, a ferroelectric layer and an upper electrode layer on a base substrate; forming a titanium oxide layer on the ferroelectric capacitor layer; patterning the titanium oxide layer by high-temperature etching between 200° C. and 500° C. to thereby form a mask pattern; and etching the ferroelectric capacitor layer by using the mask pattern as a mask, to thereby form a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode.Type: GrantFiled: March 1, 2007Date of Patent: June 24, 2008Assignee: Seiko Epson CorporationInventor: Mamoru Miyaji
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Patent number: 7329548Abstract: A method of fabricating a conductive metal oxide gate ferroelectric memory transistor includes forming an oxide layer a substrate and removing the oxide layer in a gate area; depositing a conductive metal oxide layer on the oxide layer and on the exposed gate area; depositing a titanium layer on the metal oxide layer; patterning and etching the titanium layer and the metal oxide layer to remove the titanium layer and the metal oxide layer from the substrate except in the gate area; depositing, patterning and etching an oxide layer to form a gate trench; depositing and etching a barrier insulator layer to form a sidewall barrier in the gate trench; removing the titanium layer from the gate area; depositing, smoothing and annealing a ferroelectric layer in the gate trench; depositing, patterning and etching a top electrode; and completing the conductive metal oxide gate ferroelectric memory transistor.Type: GrantFiled: August 30, 2005Date of Patent: February 12, 2008Assignee: Sharp Laboratories of America, Inc.Inventors: Tingkai Li, Sheng Teng Hsu, Bruce D. Ulrich
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Patent number: 7291530Abstract: A method of manufacturing a semiconductor storage device having a capacitive element having a dielectric layer having a perovskite-type crystal structure represented by general formula ABO3 and a lower electrode and an upper electrode disposed so as to sandwich the dielectric layer therebetween; in the method are carried out forming, on a lower electrode conductive layer, using a MOCVD method, an initial nucleus containing at least one metallic element the same as a metallic element in the dielectric layer, forming, on the initial nucleus, using a MOCVD method, a buffer layer containing at least one metallic element the same as the metallic element contained in both the initial nucleus and the dielectric layer, in a higher content than the content of this metallic element contained in the initial nucleus, and forming, on the buffer layer, using a MOCVD method, the dielectric layer having a perovskite-type crystal structure.Type: GrantFiled: August 12, 2005Date of Patent: November 6, 2007Assignee: NEC Electronics CorporationInventors: Takashi Nakagawa, Takashi Hase
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Publication number: 20070228432Abstract: The invention relates to a semiconductor element used for a nonvolatile semiconductor storage device or the like, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof and a manufacturing method of those, and has an object to provide a semiconductor element in which scaling and integration of cells are possible, storage characteristics of data are excellent, and reduction in power consumption is possible, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof, and a manufacturing method of those.Type: ApplicationFiled: January 9, 2007Publication date: October 4, 2007Applicant: FUJITSU LIMITEDInventors: Hiroshi Ishihara, Kenji Maruyama, Tetsuro Tamura, Hiromasa Hoko
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Publication number: 20070178637Abstract: A method of fabricating a gate of a semiconductor device using an oxygen-free ashing process is disclosed. The method includes forming a high-k dielectric film, having a dielectric constant higher than a silicon oxide film, on a semiconductor substrate including an NMOS region and a PMOS region, forming an etching target film on the high-k dielectric film, forming a photoresist pattern to expose any one region of the two regions, on the etching target film, etching the etching target film using the photoresist pattern as an etching mask, and removing the photoresist pattern using plasma formed in the presence of an oxygen-free reactive gas.Type: ApplicationFiled: January 30, 2007Publication date: August 2, 2007Inventors: Hyung-suk Jung, Cheol-kyu Lee, Jong-ho Lee, Sung-kee Han, Yun-seok Kim
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Publication number: 20070026547Abstract: A method and apparatus for process integration in manufacture of a gate structure of a field effect transistor are disclosed. The method includes assembling an integrated substrate processing system having a metrology module and a vacuumed processing platform to perform controlled and adaptive plasma processes without exposing the substrate to a non-vacuumed environment.Type: ApplicationFiled: September 13, 2006Publication date: February 1, 2007Applicant: Applied Materials, Inc.Inventors: Ajay Kumar, Ramesh Krishnamurthy
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Patent number: 7151001Abstract: A fabrication method of a self-aligned ferroelectric gate transistor using a buffer layer of high etching selectivity is disclosed. A stacked structure is formed with a buffer layer with high etching selectivity inserted between a silicon substrate and a ferroelectric layer, and etching is performed on a portion where a source and a drain will be formed and then stopped at the buffer layer, thereby fabricating a self-aligned ferroelectric gate transistor without damage to the silicon thin film, and thus, an integration degree of a chip can be improved.Type: GrantFiled: August 23, 2004Date of Patent: December 19, 2006Assignee: Korea Institute of Science and TechnologyInventors: Yong-Tae Kim, Seong-Il Kim, Chun-Keun Kim, Sun-Il Shim