Abstract: A semiconductor structure includes: a germanium layer; and a first insulating film that is formed on an upper surface of the germanium layer, primarily contains germanium oxide and a substance having an oxygen potential lower than an oxygen potential of germanium oxide, and has a physical film thickness of 3 nm or less; wherein a half width of frequency to height in a 1 ?m square area of the upper surface of the germanium layer is 0.7 nm or less.

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.

Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively.

Abstract: A high-k metal gate electrode is formed with reduced gate voids. An embodiment includes forming a replaceable gate electrode, for example of amorphous silicon, having a top surface and a bottom surface, the top surface being larger than the bottom surface, removing the replaceable gate electrode, forming a cavity having a top opening larger than a bottom opening, and filling the cavity with metal. The larger top surface may be formed by etching the bottom portion of the amorphous silicon at greater temperature than the top portion, or by doping the top and bottom portions of the amorphous silicon differently such that the bottom has a greater lateral etch rate than the top.

Abstract: A method of manufacturing a semiconductor device, in which an amorphous silicon layer is formed into a shape of a gate electrode of a MOS transistor, and then impurity is implanted to a surface of a silicon substrate from a diagonal direction using the amorphous silicon layer as a mask.

Abstract: An etching mask, comprising the delineation pattern of the gate electrode, of a source contact, a drain contact and a counter-electrode contact, is formed on a substrate of semi-conductor on insulator type. The substrate is covered by a layer of dielectric material and a gate material. The counter-electrode contact is located in the pattern of the gate electrode. The gate material is etched to define the gate electrode, the source contact and drain contacts and the counter-electrode contact. A part of the support substrate is released through the pattern of the counter-electrode contact area. An electrically conductive material is deposited on the free part of the support substrate to form the counter-electrode contact.

Abstract: There are provided a semiconductor device structure and a method for manufacturing the same. The method comprises: forming at least one continuous gate line on a semiconductor substrate; forming a gate spacer surrounding the gate line; forming source/drain regions in the semiconductor substrate on both sides of the gate line; forming a conductive spacer surrounding the gate spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gates of respective unit devices, and isolated portions of the conductive spacer form contacts of respective unit devices. Embodiments of the present disclosure are applicable to manufacture of contacts in integrated circuits.

Abstract: To provide a display device which can be manufactured with higher efficiency in the use of material through a simplified manufacturing process, and a method for manufacturing the display device. Another object is to provide a technique by which patterns of a wiring the like which constitutes the display device can be formed to a desired shape with good control. In a method for forming a pattern according to the present invention, a mask is formed over a light-transmitting substrate; a first region including a photocatalyst is formed over the substrate and the mask; the photocatalyst is irradiated with light through the substrate to modify a part of the first region; a second region is formed; and a composition containing a pattern forming material is discharged to the second region, thus, a pattern is formed. The mask does not transmit light.

Abstract: A self aligning memory device, with a memory element switchable between electrical property states by the application of energy, includes a substrate and word lines, at least the sides of the word lines covered with a dielectric material which defines gaps. An access device within a substrate has a first terminal under a second gap and second terminals under first and third gaps. First and second source lines are in the first and third gaps and are electrically connected to the second terminals. A first electrode in the second gap is electrically connected to the first terminal. A memory element in the second gap is positioned over and electrically connected to the first electrode. A second electrode is positioned over and contacts the memory element. The first contact, the first electrode, the memory element and the second electrode are self aligning. A portion of the memory element may have a sub lithographically dimensioned width.

Abstract: To provide a manufacturing method of a semiconductor memory device, the method including forming contact plugs to be connected to a drain region or a source region of each of transistors, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having a line-shaped opening provided across the contact plugs. Each of the transistors constituting a sense amplifier that amplifies a potential difference between bit lines is a ring-gate transistor.

Abstract: A method of manufacturing a semiconductor device includes: forming a lower electrode layer in contact with a surface of a nitride semiconductor layer; forming an Al layer on the lower electrode layer; performing a heat treatment after the formation of the Al layer; removing the Al layer after the heat treatment is performed; and forming an upper electrode layer on the lower electrode layer after the removal of the Al layer.

Abstract: A self-aligned contact includes a lower contact disposed in a dielectric layer of a substrate and an upper contact disposed in the dielectric layer and directly on the lower contact, and electrically connected to the lower contact. The profile of the upper contact and the lower contact is zigzag.

Abstract: A gate dielectric, an insulating layer and an etching mask are formed on substrate. The etching mask delineates at least the gate electrode and the source and drain contacts and the source, drain and gate output lines of the first metal level of a field effect device. The gate electrode and the future source and drain contacts are formed simultaneously by etching of the insulating layer. A gate material is deposited to form the gate electrode. The source and drain contacts are formed at least in the insulating layer. The source, drain and gate output lines of the first metal level are formed in the etching mask.

Abstract: A method for producing a transistor with metallic source and drain including the steps of: a) producing a gate stack, b) producing two portions of a material capable of being selectively etched relative to a second dielectric material and arranged at the locations of the source and of the drain of the transistor, c) producing a second dielectric material-based layer covering the stack and the two portions of material, d) producing two holes in the second dielectric material-based layer forming accesses to the two portions of material, e) etching of said two portions of material, f) depositing a metallic material in the two formed cavities, and also including, between steps a) and b), a step of deposition of a barrier layer on the stack, against the lateral sides of the stack and against the face of the first dielectric material-based layer.

Abstract: A component for an information display device has a transparent substrate having a surface that has a first refractive index. The surface is selectively coated in a pattern comprising a transparent electrically conductive layer disposed at least at a first region of the surface and at a second region of the surface. The first region of the surface is separated from the second region by a third region that is devoid of the transparent conductive layer. The transparent conductive layer has a second refractive index that is higher than the first refractive index. The first, second and third regions are commonly overcoated with a transparent layer comprising non-conductive nanoparticles, the overcoating layer being disposed over the transparent conductive layer at the first and second regions and also disposed over the third region that is devoid of the transparent conductive layer. The refractive index of the layer comprising nanoparticles is higher than the first refractive index.

Abstract: In one exemplary embodiment of the invention, a method (e.g., to fabricate a semiconductor device having a borderless contact) including: forming a first gate structure on a substrate; depositing an interlevel dielectric over the first gate structure; planarizing the interlevel dielectric to expose a top surface of the first gate structure; removing at least a portion of the first gate structure; forming a second gate structure in place of the first gate structure; forming a contact area for the borderless contact by removing a portion of the interlevel dielectric; and forming the borderless contact by filling the contact area with a metal-containing material.

Abstract: A semiconductor structure includes active multi-gate fin-type field effect transistor (MUGFET) structures and inactive MUGFET fill structures between the active MUGFET structures. The active MUGFET structures comprise transistors that change conductivity depending upon voltages within gates of the active MUGFET structures. Conversely, the inactive MUGFET fill structures comprise passive devices that do not change conductivity irrespective of voltages within gates of the inactive MUGFET fill structures. The gates of the active MUGFET structures are parallel to the gates of the inactive MUGFET fill structures, and the fins of the active MUGFET structures are the same size as the fins of the inactive MUGFET fill structures. The active MUGFET structures have the same pitch as the gates of the inactive MUGFET fill structures. The gates of the active MUGFET structures comprise active doping agents, but the inactive MUGFET fill structures do not contain the active doping agents.

Abstract: An area made from a compound of a metallic material and semi-conducting material is produced selectively in a substrate made from semi-conducting material by previously forming a germanium oxide layer with a thickness comprised between 3 nm and 5 nm over a predefined part of a surface of the substrate and a silicon oxide layer on the rest of the surface. A metallic layer is deposited on the oxide layers. The metallic material is chosen such that its oxide is thermodynamically more stable than germanium oxide and thermodynamically less stable than silicon oxide. Thermal annealing is then performed to obtain reduction of the germanium oxide by said metallic material followed by formation of the compound, at the level of said part of the surface of the substrate. The metallic layer is then removed.

Abstract: The present invention provides a method for manufacturing a display device which can reliably form electrodes in a thin film transistor.

Abstract: A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided or non-salicided. A dielectric layer is formed over the exposed polysilicon structures. A conventional contact process module is then used to form contact openings through the pre-metal dielectric layer. The mask used to form the contact openings is then removed, and conventional contact metal deposition steps are performed, thereby simultaneously filling the contact openings and the grooves with the contact (electrode) metal stack. A planarization step removes the upper portion of the metal stack, thereby leaving metal contacts in the contact openings, and metal electrodes in the grooves. The metal electrodes may form, for example, transistor gates, EEPROM control gates or capacitor plates.

Abstract: A semiconductor device is manufactured by forming a gate electrode layer over a substrate having a light transmitting property; forming a gate insulating layer over the gate electrode layer; forming a photocatalyst material over the gate insulating layer; immersing the photocatalyst material in a solution containing a plating catalyst material and selectively exposing the photocatalyst material to light transmitted through the substrate in the solution containing the plating catalyst material with the use of the gate electrode layer as a mask to adsorb or deposit the plating catalyst material onto the light-exposed photocatalyst material; immersing the plating catalyst material in a plating solution containing a metal material to form a source electrode layer and a drain electrode layer on the surface of the photocatalyst material adsorbing or depositing the plating catalyst material; and forming a semiconductor layer over the source electrode layer and the drain electrode layer.

Abstract: A packaging conductive structure for a semiconductor substrate and a method for forming the structure are provided. The dielectric layer of the packaging conductive structure partially overlays the metallic layer of the semiconductor substrate and has a receiving space. The lifting layer and conductive layer are formed in the receiving space, wherein the conductive layer extends for connection to a bump. The lifting layer is partially connected to the dielectric layer. As a result, the conductive layer can be stably deposited on the edge of the dielectric layer for enhancing the reliability of the packaging conductive structure.

Abstract: A method for manufacturing a semiconductor device according to the present invention includes the steps of providing a semiconductor substrate in which an element isolation region and active regions surrounded by the element isolation region are formed, forming a plurality of conductive lines disposed such that the conductive lines cross the active regions, forming an insulating film over the entire surface including the conductive lines, and etching away the insulating film situated over the active regions between the conductive lines so as to form contact holes. After an anti-etching film is formed to protect the surfaces in the contact holes, wet etching is conducted to remove the insulating film in the contact holes so as to form the contact holes.

Abstract: A method of hiding transparent electrodes on a transparent substrate coats a solution of non-conductive nanoparticles onto the transparent substrate and the transparent electrodes after forming a plurality of transparent electrodes on the transparent substrate, and both non-conductive nanoparticles and transparent electrodes have the same reflective index of light. After a high-temperature thermal processing is performed to the transparent substrate, an even mask is formed on the transparent substrate and the transparent electrodes, such that the non-conductive nanoparticles in the mask provide the same reflective index of light for the positions of the transparent substrate with and without the transparent electrodes, so as to effectively prevent a different reflective index of light at any position of the transparent substrate that will cause a poor image quality of the screen.

Abstract: An area made from a compound of a metallic material and semi-conducting material is produced selectively in a substrate made from semi-conducting material by previously forming a germanium oxide layer with a thickness comprised between 3 nm and 5 nm over a predefined part of a surface of the substrate and a silicon oxide layer on the rest of the surface. A metallic layer is deposited on the oxide layers. The metallic material is chosen such that its oxide is thermodynamically more stable than germanium oxide and thermodynamically less stable than silicon oxide. Thermal annealing is then performed to obtain reduction of the germanium oxide by said metallic material followed by formation of the compound, at the level of said part of the surface of the substrate. The metallic layer is then removed.

Abstract: The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed by etching a portion of the substrate disposed in the contact junction region with a predetermined thickness; a dopant diffusion barrier layer formed on sidewalls of the trench; and a contact plug filled into a space created between the gate structures and inside of the trench, wherein the dopant diffusion barrier layer prevents dopants within the contact plug from diffusing out.

Abstract: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of source and drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequality: (X/Y)>(X0/Y0).

Abstract: A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed on the hard mask layer and then the hard mask layer is patterned. A thermal treatment process is performed. The thermal treatment process is carried out at a temperature of more than 300° C. for a period of at least 3 minutes. Thereafter, the aluminum-copper alloy layer is etched using the patterned hard mask layer as an etching mask. Due to the thermal treatment, the metal precipitate (CuAl2) within the aluminum-copper alloy layer is eliminated and hence the metal etching process is improved.

Abstract: Embodiments of the invention provide a semiconductor component and a method of manufacture thereof. A semiconductor component comprises: a gate electrode layer adjacent a substrate, and a gate dielectric layer adjacent the gate electrode layer. The gate dielectric layer comprises a monolayer of at least one compound, wherein the compound has an aromatic or a condensed aromatic molecular group. The molecular group is capable of ?-? interactions, which stabilize the monolayer. In an embodiment, the semiconductor component is an organic field effect transistor (OFET). In an embodiment of the invention, a method includes forming the monolayer using a liquid phase immersion process.

Abstract: A method and apparatus for forming layers on a substrate comprising depositing a metal seed layer on a substrate surface having apertures, depositing a transition metal layer over the copper seed layer, and depositing a bulk metal layer over the transition metal layer. Also a method and apparatus for forming a via through a dielectric to reveal metal at the base of the via, depositing a transition metal layer, and depositing a first metal layer on the transition metal layer. Additionally, a method and apparatus for depositing a transition metal layer on an exposed metal surface, and depositing a layer thereover selected from the group consisting of a capping layer and a low dielectric constant layer.

Abstract: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of a source and a drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometaric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequity: (X/Y)>(X0/Y0).

Abstract: The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed by etching a portion of the substrate disposed in the contact junction region with a predetermined thickness; a dopant diffusion barrier layer formed on sidewalls of the trench; and a contact plug filled into a space created between the gate structures and inside of the trench, wherein the dopant diffusion barrier layer prevents dopants within the contact plug from diffusing out.

Abstract: The present invention relates to a method for manufacturing an optical transceiver that installs an optical transmitting assembly and an optical receiving assembly both are compact, inexpensive, and capable of operating at a high speed. The optical transmitting assembly of the present invention provides the metal bottom that installs the thermoelectric cooler thereon and the semiconductor optical device is mounted, via the insulating substrates, on the thermoelectric cooler. The first and second multi-layered ceramic substrates are provided to surround the thermoelectric cooler. The DC signal or the low-frequency signal for the thermoelectric cooler and the semiconductor optical device is supplied through the first ceramic substrate, while the high frequency signal for the semiconductor device, with the complementary signal having the opposite phase to the high frequency signal, is provided to the semiconductor device through the inner layer of the second ceramic substrate and the insulating substrate.