Abstract: A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces as appropriate for interconnection with the die (on the die attach side) and with other elements (such as other packages in a multi-package module). Interconnection with a die is made by wire bonding to exposed traces on a die attach side of the metal layer, and bond fingers and lands for access to testing the package are provided on the opposite (land) side of the metal layer.

Abstract: A semiconductor device includes a semiconductor substrate having a first main surface in which a recess is formed. Further, the semiconductor device includes an electrical interconnect structure which is arranged at a bottom of the recess. A semiconductor chip is located in the recess. The semiconductor chip includes a plurality of chip electrodes facing the electrical interconnect structure. Further, a plurality of electrically conducting elements is arranged in the electrical interconnect structure and electrically connected to the plurality of chip electrodes.

Abstract: A micro-electro-mechanical microphone and manufacturing method thereof are provided. The micro-electro-mechanical microphone includes a diaphragm, which is formed on a surface of one side of a semiconductor substrate, exposed to the outside surroundings, and can vibrate freely under the pressure generated by sound waves; an electrode plate with air holes, which is under the diaphragm; an isolation structure for fixing the diaphragm and the electrode plate; an air gap cavity between the diaphragm and the electrode plate, and a back cavity under the electrode plate and in the semiconductor substrate; and a second cavity formed on the surface of the same side of the semiconductor substrate and in an open manner The air gap cavity is connected with the back cavity through the air holes of the electrode plate The back cavity is connected with the second cavity through an air groove formed in the semiconductor substrate.

Abstract: Hybrid integrated components including an MEMS element and an ASIC element are described, whose capacitor system allows both signal detection with comparatively high sensitivity and sensitive activation of the micromechanical structure of the MEMS element. The hybrid integrated component includes an MEMS element having a micromechanical structure which extends over the entire thickness of the MEMS substrate. At least one structural element of this micromechanical structure is deflectable and is operationally linked to at least one capacitor system, which includes at least one movable electrode and at least one stationary electrode. Furthermore, the component includes an ASIC element having at least one electrode of the capacitor system. The MEMS element is mounted on the ASIC element, so that there is a gap between the micromechanical structure and the surface of the ASIC element.

Abstract: A semiconductor package may include a package substrate, a first semiconductor chip and a second semiconductor chip. The first semiconductor chip may be arranged on the package substrate. The first semiconductor chip may have a plug electrically connected to the package substrate and at least one insulating hole arranged around the plug. The second semiconductor chip may be arranged on the first semiconductor chip. The second semiconductor chip may be electrically connected to the plug. Thus, the insulating hole and the insulating member may ensure an electrical isolation between the plug and the first semiconductor chip, and between the plugs.

Abstract: One of objects is to provide a semiconductor film having stable characteristics. Further, one of objects is to provide a semiconductor element having stable characteristics. Further, one of objects is to provide a semiconductor device having stable characteristics. Specifically, a structure which includes a seed crystal layer (seed layer) including crystals each having a first crystal structure, one of surfaces of which is in contact with an insulating surface, and an oxide semiconductor film including crystals growing anisotropically, which is on the other surface of the seed crystal layer (seed layer) may be provided. With such a heterostructure, electric characteristics of the semiconductor film can be stabilized.

Abstract: Active or functional additives are embedded into surfaces of host materials for use as components in a variety of electronic or optoelectronic devices, including solar devices, smart windows, displays, and so forth. Resulting surface-embedded device components provide improved performance, as well as cost benefits arising from their compositions and manufacturing processes.

Abstract: Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.

Abstract: An assembly and method of making same are provided. The assembly can be formed by stacking a first semiconductor element atop a second semiconductor element and forming an electrically conductive element extending through openings of the semiconductor elements. The openings may be staged. The conductive element can conform to contours of the interior surfaces of the openings and can electrically connect conductive pads of the semiconductor elements. A dielectric region can be provided at least substantially filling the openings of the semiconductor elements, and the electrically conductive element can extend through an opening formed in the dielectric region.

Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.

Abstract: A semiconductor device includes: a first semiconductor element having a first terminal surface on which a first terminal is disposed and a first rear surface on which no terminal is disposed; a second semiconductor element having a second terminal surface on which a second terminal is disposed and a second rear surface on which no terminal is disposed, the second rear surface being bonded to the first rear surface; a terminal member having a surface set substantially flush with the second terminal surface; and a conductive wire connecting the terminal member and the first terminal.

Abstract: A device includes providing a silicon substrate; annealing the silicon substrate at a first temperature higher than about 900° C.; and lowering a temperature of the silicon substrate from the first temperature to a second temperature. A temperature lowering rate during the step of lowering the temperature is greater than about 1° C./second. A III-V compound semiconductor region is epitaxially grown on a surface of the silicon substrate using metal organic chemical vapor deposition (MOCVD).

Abstract: Embodiments include methods for forming a device comprising a conductive substrate, a micro electro-mechanical systems (MEMS) structure, and a plurality of bond pads. The conductive substrate has a first side and a second side, the second side opposite the first side. The MEMS structure is formed over the first side of the conductive substrate. The plurality of bond pads are formed over the first side of the conductive substrate and electrically coupled to the first side of the conductive substrate. The conductive substrate and plurality of bond pads function to provide electrostatic shielding to the MEMS structure.

Abstract: A method of growing an n-type III-nitride-based epitaxial layer includes providing a substrate in an epitaxial growth reactor, forming a masking material coupled to a portion of a surface of the substrate, and flowing a first gas into the epitaxial growth reactor. The first gas includes a group III element and carbon. The method further comprises flowing a second gas into the epitaxial growth reactor. The second gas includes a group V element, and a molar ratio of the group V element to the group III element is at least 5,000. The method also includes growing the n-type III-nitride-based epitaxial layer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a foldable segment, a base segment, and a stack segment; connecting a base substrate connector directly on the base segment; connecting a stack substrate connector directly on the stack segment; mounting a base integrated circuit over the base segment with the base substrate connector outside a perimeter of the base integrated circuit; and folding the package substrate with the stack segment over the base segment and the stack substrate connector directly on the base substrate connector.

Abstract: Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing.

Abstract: A package design is provided where a chip module is connected to a printed circuit board (PCB) via a land grid array (LGA) on the top surface of the PCB, and where a power supply is connected to the PCB via a second LGA on the bottom surface of the PCB. The stack of the chip module, power supply, and LGA is held in place and compressed with actuation hardware forming an adjustable frame. The package allows field replacibility of either the module, or the PS, and provides the shortest possible wiring distance from the PS to the module leading to higher performance.

Abstract: A method for fabricating a semiconductor device includes: forming a channel layer; forming an electron supply layer on the channel layer; forming a cap layer made of gallium nitride on the electron supply layer; and performing an oxygen plasma treatment to an upper surface of the cap layer at a power density of 0.0125˜0.15 W/cm2.

Abstract: A method for fabricating a semiconductor device includes forming ohmic electrodes on a source region and a drain region of a nitride semiconductor layer, forming a low-resistance layer between an uppermost surface of the nitride semiconductor layer and the ohmic electrodes by annealing the nitride semiconductor layer, removing the ohmic electrodes from at least one of the source region and the drain region after forming the low-resistance layer, and forming at least one of a source electrode and a drain electrode on the low-resistance layer, the at least one of a source electrode and a drain electrode having an edge, a distance between the edge and a gate electrode is longer than a distance between an edge of the low-resistance layer and the gate electrode.

Abstract: A method of manufacturing a semiconductor device includes: (a) half-dicing a semiconductor wafer including plural semiconductor chips, thereby forming dicing grooves in the semiconductor wafer, wherein each semiconductor chip includes a circuit and pads and wherein the semiconductor wafer includes: a first surface on which the circuit and the pads are formed; and a second surface opposite to the first surface, (b) connecting the pads to each other by conductive connectors; (c) sealing the first surface of the semiconductor wafer, the dicing grooves and the conductive connectors with a resin; (d) grinding the second surface of the semiconductor wafer, thereby forming a group of sealed chips; (e) dividing the group of sealed chips into individual sealed chips; (f) mounting and stacking the individual sealed chips on a wiring substrate having connection terminals thereon; and (g) electrically-connecting the conductive connectors and the connection terminals using a conductive member.

Abstract: A new structure of a semiconductor optical device and a method to produce the device are disclosed. One embodiment of the optical device of the invention provides a blocking region including, from the side close to the mesa, a p-type first layer and a p-type second layer. The first layer is co-doped with an n-type impurity and a p-type impurity. The doping concentration of the p-type impurity in the first layer is smaller than that in the second layer, so, the first layer performs a function of a buffer layer for the Zn diffusion from the second layer to the active layer in the mesa structure.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes attaching a plurality of covers to corresponding imaging dies, cutting the microfeature workpiece to singulate the imaging dies, and coupling the singulated dies to a support member. The covers can be attached to the imaging dies before or after the workpiece is cut.

Abstract: A nitride semiconductor device includes an active layer formed between an n-type cladding layer and a p-type cladding layer, and a current confining layer having a conductive area through which a current flows to the active layer. The current confining layer includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The second semiconductor layer is formed on and in contact with the first semiconductor layer and has a smaller lattice constant than that of the first semiconductor layer. The third semiconductor layer is formed on and in contact with the second semiconductor layer and has a lattice constant that is smaller than that of the first semiconductor layer and larger than that of the second semiconductor layer.

Abstract: In a manufacturing method of a thin film transistor (1), the oxide film forming step is performed whereby: a process-target substrate (2) having a surface on which a gate oxide film (4) should be formed is immersed in an oxidizing solution containing a; active oxidizing species; and a gate oxide film (4) is formed through direct oxidation of polycrystalline silicon (51) on the process-target substrate (2). With this step, a silicon dioxide film (42) is formed while growing a silicon dioxide film (41) on the process-target substrate 2. Accordingly, the interface between the polycrystalline silicon (51) and the gate oxide film (4) is kept clean. The gate oxide film (4) is uniformly formed with excellent quality in insulation tolerance and other properties. Therefore, the thin film transistor (1) contains a high quality oxide film with excellent insulation tolerance and other properties which can be formed at low temperature.

Abstract: A method for die attaching is disclosed. At first, at least one die and a die-attach preform are separately provided. The die-attach preform is picked and placed upon a die carrier. Then, the die is picked and placed upon the die-attach preform. The die and the die carrier are heated and clipped, so that the die-attach preform can adhere the die and the die carrier at the same time.

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract: A method for encapsulating an assembly with a methyl phenyl silicone rubber compound is provided. In various embodiments, the method can include exposing the assembly to a solvent, plasma etching the assembly, and producing a potting mixture, wherein the potting mixture comprises a methyl phenyl room temperature vulcanization silicone and a curing agent. The method can further include pouring the potting mixture over the assembly while under a vacuum until the assembly is encapsulated, pouring at least two control samples of the potting mixture while under the vacuum, curing the encapsulated assembly and the control samples in a first environment and monitoring the one of the control samples for hardness, and determining whether additional cure time in the first environment is needed based upon the results of the control sample hardness tests.