Abstract: In sophisticated semiconductor devices, a replacement gate approach may be applied, in which a channel semiconductor material may be provided through the gate opening prior to forming the gate dielectric material and the electrode metal. In this manner, specific channel materials may be provided in a late manufacturing stage for different transistor types, thereby providing superior transistor performance and superior flexibility in adjusting the electronic characteristics of the transistors.

Abstract: An embodiment according to the present invention comprises a method for providing a self-aligned conductive structure comprising providing a first structure on a surface, wherein the first structure comprises a first and a second layer, and providing an intermediate structure on the surface, wherein the intermediate structure at least partially abuts the first structure laterally at a first lateral edge of the first structure. The method further comprises removing at least a part of the second layer, the part being adjacent to the first lateral edge, and providing the conductive structure such that the conductive structure replaces at least the removed part of the second layer and abuts the first lateral edge.

Abstract: In a replacement gate approach, a top area of a gate opening may receive a superior cross-sectional shape after the deposition of a work function adjusting species on the basis of a polishing process, wherein a sacrificial material may protect the sensitive materials in the gate opening.

Abstract: By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors.

Abstract: A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric layer are etched thereby forming gate structures and dummy patterns, wherein at least one of the dummy patterns has at least a portion in the active region. The first photo resist is removed. A second photo resist is formed covering the gate structures. The dummy patterns unprotected by the second photo resist are removed. The second photo resist is then removed.

Abstract: A method for fabricating an electron device on a substrate includes the steps of forming a dummy film over the substrate such that the dummy film covers a device region of the substrate and an outer region of the substrate outside the device region, forming a dummy pattern by patterning the dummy film such that the dummy pattern has a first height in the device region and a second height smaller than the first height in the outer region, forming another film over the substrate such that the film covers the dummy pattern in the device region and in the outer region with a shape conformal to a cross-sectional shape of the dummy pattern, and applying an anisotropic etching process acting generally perpendicularly to the substrate such that a surface of the substrate is exposed in the device region and in the outer region.

Abstract: A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate, forming a transistor in the substrate, the transistor having a gate structure that includes a dummy gate structure, forming an inter-layer dielectric (ILD), performing a first chemical mechanical polishing (CMP) to expose a top surface of the dummy gate structure, removing a portion of the ILD such that a top surface of the ILD is at a distance below the top surface of the dummy gate structure, forming a material layer over the ILD and dummy gate structure, performing a second CMP on the material layer to expose the top surface of the dummy gate structure, removing the dummy gate structure thereby forming a trench, forming a metal layer to fill in the trench, and performing a third CMP that substantially stops at the top surface of the ILD.

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract: A semiconductor device has a structure of contacts whose size and pitch are finer that those that can be produced under the resolution provided by conventional photolithography. The contact structure includes a semiconductor substrate, an interlayer insulating layer disposed on the substrate, annular spacers situated in the interlayer insulating layer, first contacts surrounded by the spacers, and a second contact buried in the interlayer insulating layer between each adjacent pair of the first spacers. The contact structure is formed by forming first contact holes in the interlayer insulating layer, forming the spacers over the sides of the first contact holes to leave second contact holes within the first contact holes, etching the interlayer insulating layer from between the spacers using the first spacers as an etch mask to form third contact holes, and filling the first and second contact holes with conductive material. In this way, the pitch of the contacts can be half that of the first contact holes.

Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.

Abstract: A semiconductor device (10) comprises a substrate (11), a semiconductor layer (12), an insulation film (13), a protective film (15), a source electrode (21), a drain electrode (22), a gate electrode (23). The semiconductor device (10) comprises a protective film (15) formed so as to cover at least an upper surface of the insulation film (13). This enables preventing aluminum contained in the source electrode (21) and the drain electrode (22) from reacting with material contained in the insulation film (13). Accordingly, the increase of the resistance of the electrode and the increase of current collapse are prevented. Accordingly, the semiconductor device (10) has a satisfactory electric performance characteristics.

Abstract: The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) 100 located on a surface of a semiconductor substrate 12. The least one MOSFET 100 includes a gate stack including, from bottom to top, a high-k gate dielectric 28 and a metal-containing gate conductor 30. The metal-containing gate conductor 30 has gate corners 31 located at a base segment of the metal-containing gate conductor. Moreover, the metal-containing gate conductor 30 has vertically sidewalls 102A and 102B devoid of the high-k gate dielectric 28 except at the gate corners 31. A gate dielectric 18 laterally abuts the high-k gate dielectric 28 present at the gate corners 31 and a gate spacer 36 laterally abuts the metal-containing gate conductor 30.

Abstract: A semiconductor device capable of improving the efficiency of dispersing heat via a dummy pad. The semiconductor device may be included in a semiconductor package, stack module, card, or system. Also disclosed is a method of manufacturing the semiconductor device. In the semiconductor device, a semiconductor substrate has a first surface and a second surface opposite to the first surface, and at least one conductive pad is arranged on a predetermined region of the first surface. At least one dummy pad is arranged on the first or second surface, and is not electrically coupled to the at least one conductive pad. The dummy pad or pads may be used to disperse heat. Accordingly, it is possible to increase the efficiency of dispersing heat of a semiconductor device, thereby improving the yield of semiconductor devices.

Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask.

Abstract: Areas of a semiconductor substrate where semiconductor devices are not to be formed are filled in with dummy active areas. Whole dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, and partial dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, but where whole dummy active areas can not be accommodated. The dummy active areas are staggered so as to provide uniform parasitic capacitive coupling to overlying leads regardless of the placement of the leads. The dummy active areas are substantially evenly separated from one another by dividers. The dummy active areas and dividers are formed concurrently with formation of semiconductor devices in non-dummy active areas. The dummy active areas mitigate yield loss by, among other things, providing more uniformity across the substrate, at least with regard to parasitic capacitances and stress and subsequent processing.

Abstract: Provided is a semiconductor device having a high-frequency interconnect, first dummy conductor patterns, an interconnect, and second dummy conductor patterns. The first dummy conductor patterns are arranged in the vicinity of the high-frequency interconnect, and the second dummy conductor patterns are arranged in the vicinity of the interconnect. The minimum value of distance between the high-frequency interconnect and the first dummy conductor patterns is larger than the minimum value of distance between the interconnect and the second dummy conductor patterns.

Abstract: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.

Abstract: A method for manufacturing a semiconductor device includes the steps of (a) forming a first insulating film pattern, which has a first portion and a second portion separated from the first portion through a first space, above a semiconductor substrate, (b) selectively forming a first impurity diffusion layer in a portion of the semiconductor substrate located at least below the first space by conducting ion implantation of impurities into the semiconductor substrate by using at least the first insulating film pattern as a mask, (c) eliminating the second portion, and (d) forming a gate electrode having a functional portion above the semiconductor substrate.

Abstract: The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) 100 located on a surface of a semiconductor substrate 12. The least one MOSFET 100 includes a gate stack including, from bottom to top, a high-k gate dielectric 28 and a metal-containing gate conductor 30. The metal-containing gate conductor 30 has gate corners 31 located at a base segment of the metal-containing gate conductor. Moreover, the metal-containing gate conductor 30 has vertically sidewalls 102A and 102B devoid of the high-k gate dielectric 28 except at the gate corners 31. A gate dielectric 18 laterally abuts the high-k gate dielectric 28 present at the gate corners 31 and a gate spacer 36 laterally abuts the metal-containing gate conductor 30.

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A method for fabricating a flash memory device is disclosed that improves hot carrier injection efficiency by forming a gate after forming source and drain implants using a sacrificial insulating layer pattern, which includes forming a sacrificial insulating pattern layer over a flash memory channel region of a semiconductor substrate; forming source and drain regions in the semiconductor substrate by ion implantation using the sacrificial insulating pattern layer as a mask; removing portions of the sacrificial insulating pattern layer; sequentially forming an ONO-type dielectric layer and a gate material layer; selectively etching the gate material layer and at least part of the gate dielectric layer to form a gate; and forming gate sidewall spacers at sides of the gate.

Abstract: A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric layer are etched thereby forming gate structures and dummy patterns, wherein at least one of the dummy patterns has at least a portion in the active region. The first photo resist is removed. A second photo resist is formed covering the gate structures. The dummy patterns unprotected by the second photo resist are removed. The second photo resist is then removed.

Abstract: The present invention provides a method of manufacturing a gate electrode in which a fine gate electrode can effectively be manufactured by thickening a resist opening for gate electrodes formed by ordinary electron beam lithography so as to reduce opening dimensions. The method of manufacturing a gate electrode of the present invention includes a step of forming a laminated resist including at least an electron beam resist layer as a lowermost layer on a surface where a gate electrode is to be formed; a step of forming an opening in layer(s) other than the lowermost layer; a step of forming a gate electrode opening on the lowermost layer exposed from the opening; a step of reducing the gate electrode opening selectively; and a step of forming a gate electrode in the gate electrode opening.

Abstract: An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.

Abstract: The manufacturing stability can be improved while effectively inhibiting the short-channel effect in the transistor according to the present invention. A halo impurity having a conductivity type opposite to a first conductivity type of a first impurity is ion-implanted into the silicon substrate 101, and thereafter the first impurity having the first conductivity type, is ion-implanted and then a flash lamp annealing is conducted to form a p-type halo region 113 and a n-type extension region 111. Then, the second impurity having the first conductivity type is ion-implanted into the silicon substrate 101, and then a flash lamp annealing is conducted to form a n-type source/drain region 109. Then, the impurity contained in the silicon substrate 101 is activated via spike RTA.

Abstract: An embodiment of the present invention includes a gate dielectric layer, a polysilicon layer, and a gate electrode. The gate dielectric layer is on a substrate. The substrate has a gate area, a source area, and a drain area. The polysilicon layer is on the gate dielectric layer at the gate area. The gate electrode is on the polysilicon layer and has arc-shaped sidewalls.

Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.

Abstract: A method for fabricating a short channel field-effect transistor is presented. A sublithographic gate sacrificial layer is formed, as are spacers at the side walls of the gate sacrificial layer. The gate sacrificial layer is removed to form a gate recess and a gate dielectric and a control layer are formed in the gate recess. The result is a short channel field-effect transistor with minimal fluctuations in the critical dimensions in a range below 100 nanometers.