Abstract: A field effect transistor including: a support layer, a plurality of active zones based on a semiconductor, each active zone configured to form a channel and arranged between two gates adjacent to each other and consecutive, the active zones and the gates being arranged on the support layer, each gate including a first face on the side of the support layer and a second face opposite the first face. The second face of a first of the two gates is electrically connected to a first electrical contact made on the second face of the first of the two gates, and the first face of a second of the two gates is electrically connected to a second electrical contact passing through the support layer. The gates of the transistor are not electrically connected to each other.

Abstract: Disclosed herein is a thin film transistor, which includes a metal oxide semiconductor layer, an insulating layer, a gate electrode, a source electrode and a drain electrode. The metal oxide semiconductor layer includes a channel region having at least one first region and a second region. The first region has an oxygen vacancy concentration greater than an oxygen vacancy concentration of the second region. The second region surrounds the first region. A method for manufacturing the thin film transistor is disclosed as well.

Abstract: A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.

Abstract: According to one embodiment, a semiconductor device, including a semiconductor layer including a first region and a second region isolated from the first region, a source in a surface of the first region, a drain in a surface of the second region, a back-gate in the surface of the first region, an end of a drain side of the back-gate being located closer to the drain side than an end of the drain side of the source, a gate insulator on a surface of the semiconductor layer between the first region and the second region, a gate electrode on the gate insulator, a source electrode being contacted to both the source and the back-gate, and a drain electrode being contacted to the drain area.

Abstract: A transistor is provided that includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.

Abstract: A nonvolatile semiconductor memory device includes a first insulating layer, charge storage layers, element isolation insulating films, and a second insulating layer formed on the charge storage layers and the element isolation insulating films and including a stacked structure of a first silicon nitride film, first silicon oxide film, intermediate insulating film and second silicon oxide film. The first silicon nitride film has a nitrogen concentration of not less than 21×1015 atoms/cm2. Each element isolation insulating film includes a high-temperature oxide film formed along lower side surfaces of the charge storage layers between the charge storage layers and a coating type insulating film. The first silicon nitride film is formed on an upper surface of the high-temperature oxide film in upper surfaces of the element isolation insulating films and not on the upper surface of the coating type insulating film.

Abstract: The present invention relates to an image sensor applied with a device isolation technique for reducing dark signals and a fabrication method thereof. The image sensor includes: a logic unit; and a light collection unit in which a plurality of photodiodes is formed, wherein the photodiodes are isolated from each other by a field ion-implantation region formed under a surface of a substrate and an insulation layer formed on the surface of the substrate.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate layer over a substrate, forming a hard mask layer over a gate layer, forming a first material layer over the hard mask layer, forming a patterned photoresist layer having an opening over the first material layer, etching the first material layer through a cycle including forming a second material layer over the semiconductor device and etching the first and second material layers, repeating the cycle until the hard mask layer is exposed by a reduced opening, the reduced opening formed in a last cycle, etching the hard mask layer beneath the second opening to expose the gate layer, and patterning the gate layer using the hard mask layer. An etching selectivity of the first and second material layers is smaller than an etching selectivity of the second material layer and the photoresist layer.

Abstract: A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and overhang underlying portions of the recess. An electric contact has first portions thereof disposed on said adjacent portions of the dielectric film, second portions disposed on said underlying portions of the recess, with portions of the dielectric film being disposed between said first portion of the electric contact and the second portions of the electric contact, and third portions of the electric contact being disposed on and in contact with a bottom portion of the recess in the semiconductor structure. The electric contact is formed by atomic layer deposition of an electrically conductive material over the dielectric film and through the aperture in such dielectric film.

Abstract: There are provided a memory transistor having a select transistor with asymmetric gate electrode structure and an inverted T-shaped floating gates and a method for forming the same. A gate electrode of the select transistor adjacent to a memory transistor has substantially an inverted T-shaped figure, whereas the gate electrode of the select transistor opposite to the memory transistor has nearly a box-shaped figure. In order to form the floating gate of the memory transistor in shape of the inverted T, a region for the select transistor is closed when opening a region for the memory transistor.

Abstract: A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded.

Abstract: The present invention provides a MOS transistor device for providing ESD protection including at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further includes at least one isolation gate formed in at least one of the interleaved fingers. The device can further include a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A semiconductor device including: a first gate insulating film which is pattern-formed on an N type well region within a P type semiconductor substrate; a second gate insulating film which is formed on the semiconductor substrate except for this first gate insulating film; a gate electrode, which is formed in such a manner that this gate electrode is bridged over the first gate insulating film and the second gate insulating film; a P type body region which is formed in such a manner that this P type body region is located adjacent to the gate electrode; an N type source region and a channel region, which are formed within this P type body region; and an N type drain region which is formed at a position separated from the P type body region.