Abstract: A transfer transistor includes a pair of first diffusion regions and a gate electrode layer. The pair of first diffusion regions are formed in a surface of a semiconductor substrate, and are each connected to a contact. The gate electrode layer is formed on the semiconductor substrate via a gate insulating layer and has a pair of openings each surrounding the contact.

Abstract: A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.

Abstract: A display substrate includes a gate wire formed on an insulating substrate, a semiconductor pattern formed on the gate wire and containing a metal oxynitride compound, and a data wire formed on the semiconductor pattern to cross the gate wire. The semiconductor pattern has a carrier number density ranging from 1016/cm3 to 1019/cm3.

Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.

Abstract: A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a second polarity voltage on the gate of a transfer transistor during a charge integration period.

Abstract: A solid-state imaging device including a first transfer electrode portion and a second transfer electrode portion having a pattern area ratio higher than that of the first transfer electrode portion. The first transfer electrode portion includes a plurality of first transfer electrodes having a single-layer structure of metal material. The second transfer electrode portion includes a plurality of second transfer electrodes having a single-layer structure of polycrystalline silicon or amorphous silicon.

Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.

Abstract: A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a second polarity voltage on the gate of a transfer transistor during a charge integration period.

Abstract: This invention provides a type of solid-state image pickup device characterized by the fact that for a solid-state image pickup device with a broad dynamic range, it is possible to suppress the dark current than photoelectrons overflowing from the photodiode, as well as its driving method. Plural pixels are integrated in an array configuration on a semiconductor substrate. Each pixel has the following parts: photodiode (CPD), transfer transistor (?T), floating diffusion (CFD), accumulating capacitive element (CS), accumulating transistor (?S), and a reset transistor. During the accumulating period of photoelectric charge, voltage (?) over that applied on the semiconductor substrate, or ?0.6 V or lower than the voltage applied on the semiconductor substrate, is applied as an OFF potential on the gate electrode of at least one transfer transistor, the accumulating transistor and the reset transistor.

Abstract: A solid-state image pickup element 1 is structured so as to include: a semiconductor layer 2 having a photodiode formed therein, photoelectric conversion being carried out in the photodiode; a first film 21 having negative fixed charges and formed on the semiconductor layer 2 in a region in which at least the photodiode is formed; and a second film 22 having the negative fixed charges, made of a material different from that of the first film 21 having the negative fixed charges, and formed on the first film 21 having the negative fixed charges.

Abstract: Dielectric layers having an atomic layer deposited oxide containing titanium and zirconium and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Pulsing a titanium-containing precursor onto a substrate, and pulsing a zirconium-containing precursor to form an oxide containing Zr and Ti by atomic layer deposition provides a dielectric layer with a relatively high dielectric constant as compared with silicon oxide. A zirconium-containing precursor to form the oxide containing Zr and Ti can include zirconium tertiary-butoxide.

Abstract: A method for producing a sensor array including a monolithically integrated circuit is described as well as a sensor array. This sensor array has a micromechanical sensor structure, in which a first partial structure which is associated with the sensor structure is produced at the same time as a second partial structure which is associated with the circuit, a process variation of the first partial structure being performed in order to adjust a structure property of the sensor structure while the second partial structure remains the same.

Abstract: A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a second polarity voltage on the gate of a transfer transistor during a charge integration period.

Abstract: A piezo-TFT cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method comprises: providing a substrate, such as glass for example; forming thin-films overlying the substrate; forming a thin-film cantilever beam; and simultaneously forming a TFT within the cantilever beam. The TFT is can be formed least partially overlying a cantilever beam top surface, at least partially overlying a cantilever beam bottom surface, or embedded within the cantilever beam. In one example, forming thin-films on the substrate includes: selectively forming a first layer with a first stress level; selectively forming a first active Si region overlying the first layer; and selectively forming a second layer overlying the first layer with a second stress level. The thin-film cantilever beam is formed from the first and second layers, while the TFT source/drain (S/D) and channel regions are formed from the first active Si region.

Abstract: A solid state imaging apparatus comprises: a semiconductor substrate; a photoelectric converting portion on the semiconductor substrate; a light shielding film in a region excluding a light receiving surface of the photoelectric converting portion; and a P-type impurity layer between a lower surface of the light shielding film and the semiconductor substrate.

Abstract: A semiconductor device fabrication method in which when a semiconductor device with a built-in light receiving element is fabricated, a section for dividing the light receiving element is protected from damage caused by, for example, etching. An antireflection coating is formed not only on a light receiving area in a divided photodiode area but on a division area including a junction area between a division section outside the light receiving area for dividing a photodiode and a cathode. A polycrystalline silicon film is formed so as to cover the antireflection coating. Accordingly, the antireflection coating on the junction area between the division section outside the light receiving area and the cathode is protected against, for example, etching by the polycrystalline silicon film. As a result, the appearance of a crystal defect, a change in impurity concentration, or the like is suppressed in this area.

Abstract: An image sensor can include a gate insulation layer, a gate electrode, a photodiode, and a floating diffusion region. The gate insulation layer can be formed on and/or over a semiconductor substrate for a transfer transistor. The gate insulation layer includes a first gate insulation layer having a central opening and a second gate insulation layer formed on and/or over an uppermost surface of the first gate insulation layer including the opening. The gate electrode can be formed on and/or over the gate insulation layer. The photodiode can be formed in the semiconductor substrate at one side of the gate electrode so as to generate an optical charge. The floating diffusion region can be formed in the semiconductor at the other side of the gate electrode opposite to the photodiode. The floating diffusion region can be electrically connected to the photodiode through a channel so as to store the optical charge generated from the photodiode.

Abstract: A CMOS imager and non-volatile memory are integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. A protective layer covers the non-volatile memory contained on the substrate for blocking light received by the CMOS imager. The protective layer can be a metal layer used as an interconnect over other areas of the substrate or an opaque layer provided during the fabrication process. Integrating a CMOS imager, non-volatile memory and peripheral circuitry for decoding and processing optical information received by the CMOS imager allows for a single chip image sensing device, such as a digital camera.

Abstract: A solid image capturing element comprising a plurality of vertical shift registers arranged to each correspond to a column of a plurality of light receiving pixels in a matrix arrangement, a horizontal shift register provided on an output side of the plurality of vertical shift registers, and an output section provided on an output side of the horizontal shift register. In this solid image capturing element, a reverse conductive semiconductor region is formed over one major surface of one conductive semiconductor substrate, the plurality of light receiving pixels, the plurality of vertical shift registers, the horizontal shift register, and the output section are formed in the semiconductor region, and a portion of the semiconductor region where the output section is formed has a higher dopant concentration than the portion of the semiconductor region where the horizontal shift register is formed.

Abstract: A phase change memory device and a method of fabricating the same are disclosed. The phase change memory device includes a first conductor pattern having a first conductivity type and a sidewall. A second conductor pattern is connected to the sidewall of the first conductor pattern to form a diode. A phase change layer is electrically connected to the second conductor pattern and a top electrode is connected to the phase change layer.

Abstract: A semiconductor device, including: a semiconductor material and an electrode structure electrically coupled to the semiconductor material. The electrode structure includes: a first portion formed of a first conductive material and a second portion formed of a second conductive material. Both the first portion and the second portion of the electrode structure are in direct contact with the semiconductor material. The first conductive material has a first work function and the second conductive material has a second work function that is different from the first work function, so that the second portion of the electrode structure forms a junction with the first portion. The first portion and the second portion of the electrode structure are arranged such that the fringe field from the edge of this junction between the first portion and the second portion extends into the semiconductor material.

Abstract: A CCD containing circuit and method for making the same. The circuit includes a CCD array and a protection circuit. The CCD array is constructed on an integrated circuit substrate and includes a plurality of gate electrodes that are insulated from the substrate by an insulating layer. The gate electrodes are connected to a conductor bonded to the substrate. The protection circuit is also constructed on the substrate. The protection circuit is connected to the conductor and to the substrate and protects the CCD array from both negative and positive voltage swings generated by electrostatic discharge events and the like. The protection circuit and the CCD can be constructed in the same integrated circuit fabrication process.

Abstract: The present invention is directed to methods for transferring pre-formed electronic devices, such as transistors, resistors, capacitors, diodes, semiconductors, inductors, conductors, and dielectrics, and segments of materials, such as magnetic materials and crystalline materials onto a variety of receiving substrates using energetic beam transfer methods. Also provided is a consumable intermediate comprising a transfer substrate and a transfer material coated thereon, wherein the transfer material may be comprised of pre-formed electronic devices or magnetic materials and crystalline materials that may be transferred to a variety of receiving substrates. Aspects of the present invention may also be used to form multi-device electronic components such as sensor devices, electro-optical devices, communications devices, transmit-receive modules, and phased arrays using the consumable intermediates and transfer methods described herein.

Abstract: A solid state imaging apparatus comprises: a semiconductor substrate; a photoelectric converting portion on the semiconductor substrate; a light shielding film in a region excluding a light receiving surface of the photoelectric converting portion; and a P-type impurity layer between a lower surface of the light shielding film and the semiconductor substrate.

Abstract: Provided are methods for producing multiple distinct transistors from a single semiconductor layer, and apparatus incorporating transistors so produced.

Abstract: An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.

Abstract: In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein, and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer. Wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced.

Abstract: A method and structure of providing a doped plug to improve the performance of CCD gaps is discussed. A highly-doped region is implemented in a semiconductor, aligned beneath a gap. The plug provides a highly-conductive region at the semiconductor surface, therefore preventing the development of a region where potential is significantly influenced by surface charges.

Abstract: In a semiconductor device 10 including a structure where transfer electrodes 2a to 2c are disposed on a semiconductor substrate 1 via an insulation layer 3, a first semiconductor region 4 of a first conductivity type, a second semiconductor region 5 of a conductivity type opposite to the first conductivity type, and a third semiconductor region 6 of the first conductivity type in a position that overlaps a region of the semiconductor substrate 1 directly underneath the transfer electrodes 2a to 2c. The second semiconductor region 5 is formed on the first semiconductor region 4. The third semiconductor region 6 is formed on the second semiconductor region 5 so that a position of a maximal point 8 of electric potential of the second semiconductor region 5 when being depleted is deeper than a position of the maximal point 8 in a case where the third semiconductor region 6 does not exist.

Abstract: A piezo-TFT cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method comprises: providing a substrate, such as glass for example; forming thin-films overlying the substrate; forming a thin-film cantilever beam; and simultaneously forming a TFT within the cantilever beam. The TFT is can be formed least partially overlying a cantilever beam top surface, at least partially overlying a cantilever beam bottom surface, or embedded within the cantilever beam. In one example, forming thin-films on the substrate includes: selectively forming a first layer with a first stress level; selectively forming a first active Si region overlying the first layer; and selectively forming a second layer overlying the first layer with a second stress level. The thin-film cantilever beam is formed from the first and second layers, while the TFT source/drain (S/D) and channel regions are formed from the first active Si region.