Using Physical Deposition, E.g., Vacuum Deposition, Sputtering (epo) Patents (Class 257/E21.462)
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Patent number: 12125919Abstract: To provide a novel metal oxide. The metal oxide includes a first region and a second region. A third region is included between the first region and the second region. An interface of the first region is covered with the third region. The crystallinity of the third region is lower than the crystallinity of the first region. The crystallinity of the second region is lower than the crystallinity of the third region. The size of the first region measured from an image observed with a transmission electron microscope is greater than or equal to 1 nm and less than or equal to 3 nm.Type: GrantFiled: February 11, 2020Date of Patent: October 22, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Tomonori Nakayama, Masahiro Takahashi
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Patent number: 12027645Abstract: An optoelectronic semiconductor chip may have or include an x-doped region, a y-doped region, an active region arranged between the x-doped region and the y-doped region, and an x-contact region. The x-contact region may be arranged to the side of the x-doped region facing away from the active region. The x-contact region may include at least one first region and at least one second region. The x-contact region may be designed such that, during operation of the optoelectronic semiconductor chip, more charge carriers are injected into the x-doped region via the second region than via the first region.Type: GrantFiled: October 2, 2019Date of Patent: July 2, 2024Assignee: OSRAM OPTO SEMICONDUCTORS GMBHInventors: Ivar Tangring, Korbinian Perzlmaier
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Patent number: 11802340Abstract: A cooling chamber comprising a support plate connected to a cryo pump and turbo pump, a clamp ring with a plurality of clamp pads on the bottom thereof where each clamp pad has a beveled surface directed downward and a lift plate to move the clamp ring from a clamp position to a loading position are described. Cluster tools incorporating the cooling chamber and methods of using the cooling chamber are also described.Type: GrantFiled: December 12, 2017Date of Patent: October 31, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Bharath Swaminathan, John Mazzocco, Hanbing Wu, Ashish Goel, Anantha K. Subramani
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Patent number: 11233133Abstract: Methods of forming thin-film structures including one or more NbMC layers, and structures and devices including the one or more NbMC layers are disclosed. The NbMC layers enable tuning of various structure and device properties, including resistivity, current leakage, and work function.Type: GrantFiled: January 4, 2019Date of Patent: January 25, 2022Assignee: ASM IP Holding B.V.Inventors: Chiyu Zhu, Timo Asikainen, Robert Brennan Milligan
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Patent number: 10446690Abstract: A method of production of a semiconductor device comprising a semiconductor layer forming step of forming a semiconductor layer including an inorganic oxide semiconductor on a board, a passivation film forming step of forming a passivation film comprising an organic material so as to cover the semiconductor layer, a baking step of baking the passivation film, and a cooling step of cooling the passivation film after baking, herein, in the cooling step, a cooling speed from a baking temperature at the time of baking in the baking step to a temperature 50° C. lower than the baking temperature is substantially controlled to 0.5 to 5° C./min in range is provided.Type: GrantFiled: November 25, 2014Date of Patent: October 15, 2019Assignees: TOHOKU UNIVERSITY, ZEON CORPORATIONInventors: Tetsuya Goto, Makoto Takeshita
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Patent number: 10211308Abstract: Methods of forming thin-film structures including one or more NbMC layers, and structures and devices including the one or more NbMC layers are disclosed. The NbMC layers enable tuning of various structure and device properties, including resistivity, current leakage, and work function.Type: GrantFiled: October 21, 2015Date of Patent: February 19, 2019Assignee: ASM IP Holding B.V.Inventors: Chiyu Zhu, Timo Asikainen, Robert Brennan Milligan
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Patent number: 9368634Abstract: A thin film transistor (TFT) including a gate, a dielectric layer, a metal-oxide semiconductor channel, a source, and a drain is provided. The gate and the metal-oxide semiconductor channel are overlapped. The gate, the source, and the drain are separated by the dielectric layer. Besides, the source and the drain are respectively located on two opposite sides of the metal-oxide semiconductor channel. The metal-oxide semiconductor channel includes a metal-oxide semiconductor layer and a plurality of nano micro structures disposed in the metal-oxide semiconductor layer and separated from one another. In another aspect, a display panel including the TFT and a method of fabricating the TFT are also provided.Type: GrantFiled: March 15, 2013Date of Patent: June 14, 2016Assignee: E Ink Holdings Inc.Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Xue-Hung Tsai, Henry Wang, Wei-Tsung Chen
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Patent number: 8980686Abstract: An object is to provide a deposition technique for depositing an oxide semiconductor film. Another object is to provide a method for manufacturing a highly reliable semiconductor element using the oxide semiconductor film. A novel sputtering target obtained by removing an alkali metal, an alkaline earth metal, and hydrogen that are impurities in a sputtering target used for deposition is used, whereby an oxide semiconductor film containing a small amount of those impurities can be deposited.Type: GrantFiled: September 2, 2014Date of Patent: March 17, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8927330Abstract: Disclosed herein is a method for manufacturing a metal-oxide thin film transistor. The method includes the steps of: (a1) forming a gate electrode on a substrate; (a2) forming a gate insulating layer over the gate electrode; (a3) forming a metal-oxide semiconductor layer having a channel region on the gate insulating layer; (a4) forming a source electrode and a drain electrode on the metal-oxide semiconductor layer, wherein the source electrode is spaced apart from the drain electrode by a gap exposing the channel region; (a5) forming a mobility-enhancing layer on the channel region, wherein the mobility-enhancing layer is not in contact with the source electrode and the drain electrode; and (a6) annealing the metal-oxide semiconductor layer and the mobility-enhancing layer in an environment at a temperature of about 200° C. to 350° C.Type: GrantFiled: August 13, 2012Date of Patent: January 6, 2015Assignee: E Ink Holdings Inc.Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chun-Cheng Yeh, Liang-Hao Chen
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Patent number: 8877569Abstract: An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOX is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiOX. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.Type: GrantFiled: April 25, 2012Date of Patent: November 4, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiaki Oikawa, Hotaka Maruyama, Hiromichi Godo, Daisuke Kawae, Shunpei Yamazaki
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Patent number: 8828811Abstract: A semiconductor device using an oxide semiconductor, with stable electric characteristics and high reliability. In a process for manufacturing a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation is performed by heat treatment and oxygen doping treatment is performed. The transistor including the oxide semiconductor film subjected to the dehydration or dehydrogenation by the heat treatment and the oxygen doping treatment is a transistor having high reliability in which the amount of change in threshold voltage of the transistor by the bias-temperature stress test (BT test) can be reduced.Type: GrantFiled: April 21, 2011Date of Patent: September 9, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Publication number: 20140024172Abstract: Apparatus and method for vapor deposition of a sublimated source material are generally provided. The apparatus includes a deposition head with a first sublimation compartment and a second sublimation compartment, each configured for receipt and sublimation of a source material. A first distribution plate can be positioned at a first defined distance above a horizontal conveyance plane of an upper surface of substrates conveyed through a first deposition area of the apparatus, and a second distribution plate can be positioned at a second defined distance above a horizontal conveyance plane of an upper surface of substrates conveyed through a second deposition area of said apparatus. The first sublimation compartment and the second sublimation compartment can be isolated from each other such that the sublimated first source material is substantially prevented from mixing with the sublimated second source material, at least during sublimation.Type: ApplicationFiled: July 20, 2012Publication date: January 23, 2014Applicant: PRIMESTAR SOLAR, INC.Inventors: Christopher Rathweg, Scott Daniel Feldman-Peabody
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Patent number: 8633480Abstract: An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.Type: GrantFiled: November 3, 2010Date of Patent: January 21, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake
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Patent number: 8551884Abstract: A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film.Type: GrantFiled: March 22, 2012Date of Patent: October 8, 2013Assignee: Elpida Memory, Inc.Inventor: Katsuhiko Tanaka
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Publication number: 20130256653Abstract: A plural semiconductive oxides TFT (sos-TFT) provides improved electrical functionality in terms of charge-carrier mobility and/or threshold voltage variability. The sos-TFT may be used to form a thin film transistor array panel for display devices. An example sos-TFT includes: an insulated gate electrode; a first semiconductive oxide layer having a composition including a first semiconductive oxide; and a second semiconductive oxide layer having a different composition that also includes a semiconductive oxide. The first and second semiconductive oxide layers have respective channel regions that are capacitively influenced by a control voltage applied to the gate electrode. In one embodiment, the second semiconductive oxide layer includes at least one additional element that is not included in the first semiconductive oxide layer where the additional element is one of gallium (Ga), silicon (Si), niobium (Nb), hafnium (Hf), and germanium (Ge).Type: ApplicationFiled: July 23, 2012Publication date: October 3, 2013Applicant: SAMSUNG DISPLAY CO., LTD.Inventors: Byung Du AHN, Ji Hun LIM, Gun Hee KIM, Kyoung Won LEE, Je Hun LEE
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Patent number: 8461582Abstract: A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.Type: GrantFiled: February 24, 2010Date of Patent: June 11, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hajime Kimura
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Patent number: 8440906Abstract: A photovoltaic device having a first electrode layer, a high resistivity transparent film disposed on the first electrode, a second electrode layer, and an inorganic photoactive layer disposed between the first and second electrode layers, wherein the inorganic photoactive layer is disposed in at least partial electrical contact with the high resistivity transparent film, and in at least partial electrical contact with the second electrode. The photoactive layer has a first inorganic material and a second inorganic material different from the first inorganic material, wherein the first and second inorganic materials exhibit a type II band offset energy profile, and wherein the photoactive layer has a first population of nanostructures of a first inorganic material and a second population of nanostructures of a second inorganic material.Type: GrantFiled: October 20, 2006Date of Patent: May 14, 2013Assignee: The Regents of the University of CaliforniaInventors: A. Paul Alivisatos, Ilan Gur, Delia Milliron
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Patent number: 8426243Abstract: There is provided an amorphous oxide semiconductor including hydrogen and at least one element of indium (In) and zinc (Zn), the amorphous oxide semiconductor containing one of hydrogen atoms and deuterium atoms of 1×1020 cm?3 or more to 1×1022 cm?3 or less, and a density of bonds between oxygen and hydrogen except bonds between excess oxygen (OEX) and hydrogen in the amorphous oxide semiconductor being 1×1018 cm?3 or less.Type: GrantFiled: January 18, 2012Date of Patent: April 23, 2013Assignee: Canon Kabushiki KaishaInventors: Ryo Hayashi, Hideyuki Omura, Hideya Kumomi, Yuzo Shigesato
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Publication number: 20130056727Abstract: A semiconductor device which is miniaturized and has sufficient electrical characteristics to function as a transistor is provided. In a semiconductor device including a transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode layer are stacked in that order, an oxide semiconductor film which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and in which the percentage of the indium is twice or more as large as each of the percentage of the gallium and the percentage of the zinc when the composition of the four elements is expressed in atomic percentage is used as the semiconductor layer. In the semiconductor device, the oxide semiconductor film is a film to which oxygen is introduced in the manufacturing process and contains a large amount of oxygen, and an insulating layer including an aluminum oxide film is provided to cover the transistor.Type: ApplicationFiled: September 4, 2012Publication date: March 7, 2013Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Naoto YAMADE, Junichi KOEZUKA
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Publication number: 20130045567Abstract: Disclosed herein is a method for manufacturing a metal-oxide thin film transistor. The method includes the steps of: (a1) forming a gate electrode on a substrate; (a2) forming a gate insulating layer over the gate electrode; (a3) forming a metal-oxide semiconductor layer having a channel region on the gate insulating layer; (a4) forming a source electrode and a drain electrode on the metal-oxide semiconductor layer, wherein the source electrode is spaced apart from the drain electrode by a gap exposing the channel region; (a5) forming a mobility-enhancing layer on the channel region, wherein the mobility-enhancing layer is not in contact with the source electrode and the drain electrode; and (a6) annealing the metal-oxide semiconductor layer and the mobility-enhancing layer in an environment at a temperature of about 200° C. to 350° C.Type: ApplicationFiled: August 13, 2012Publication date: February 21, 2013Applicant: E INK HOLDINGS INC.Inventors: Hsiao-Wen ZAN, Chuang-Chuang TSAI, Chun-Cheng YEH, Liang-Hao CHEN
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Patent number: 8377729Abstract: A method of making II-VI core-shell semiconductor nanowires includes providing a support; depositing a layer including metal alloy nanoparticles on the support; and heating the support and growing II-VI core semiconductor nanowires where the metal alloy nanoparticles act as catalysts and selectively cause localized growth of the core nanowires. The method further includes modifying the growth conditions and shelling the core nanowires to form II-VI core-shell semiconductor nanowires.Type: GrantFiled: January 19, 2010Date of Patent: February 19, 2013Assignee: Eastman Kodak CompanyInventors: Keith B. Kahen, Matthew Holland
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Publication number: 20130011962Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.Type: ApplicationFiled: September 5, 2012Publication date: January 10, 2013Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Tetsunori MARUYAMA, Yuki IMOTO, Hitomi SATO, Masahiro WATANABE, Mitsuo MASHIYAMA, Kenichi OKAZAKI, Motoki NAKASHIMA, Takashi SHIMAZU
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Patent number: 8338249Abstract: A method for manufacturing a semiconductor device comprises: forming a lower electrode on a semiconductor substrate, sputtering a ferroelectric film on the lower electrode using a target, thermal treating the ferroelectric film in an atmosphere containing oxygen in accordance with an accumulated period of use of the target for fabricating the ferroelectric film, and forming an upper electrode on the ferroelectric film.Type: GrantFiled: February 15, 2008Date of Patent: December 25, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Makoto Takahashi, Mitsushi Fujiki, Kenkichi Suezawa, Wensheng Wang, Ko Nakamura
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Patent number: 8329506Abstract: It is an object to provide an oxide semiconductor which is suitable for use in a semiconductor device. Alternatively, it is another object to provide a semiconductor device using the oxide semiconductor. Provided is a semiconductor device including an In—Ga—Zn—O based oxide semiconductor layer in a channel formation region of a transistor. In the semiconductor device, the In—Ga—Zn—O based oxide semiconductor layer has a structure in which crystal grains represented by InGaO3(ZnO)m (m=1) are included in an amorphous structure represented by InGaO3(ZnO)m (m>0).Type: GrantFiled: November 16, 2009Date of Patent: December 11, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kengo Akimoto, Junichiro Sakata, Takuya Hirohashi, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga
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Publication number: 20120288994Abstract: Embodiments disclosed herein generally relate to TFTs and methods of fabricating the TFTs. In TFTs, the active channel carries the current between the source and drain electrodes. By tailoring the composition of the active channel, the current can be controlled. The active channel may be divided into three layers, a gate control layer, a bulk layer, and an interface control layer. The separate layers may have different compositions. Each of the gate control, bulk and interface control layers may additionally comprise multiple layers that may have different compositions. The composition of the various layers of the active channel comprise oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, indium, cadmium, tin, gallium and combinations thereof. By varying the composition among the layers, the mobility, carrier concentration and conductivity of the various layers may be controlled to produce a TFT having desired properties.Type: ApplicationFiled: July 24, 2012Publication date: November 15, 2012Applicant: APPLIED MATERIALS, INC.Inventor: YAN YE
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Patent number: 8293553Abstract: In a method for producing at least at least one area (8) with reduced electrical conductivity within an electrically conductive III-V semiconductor layer (3), a ZnO layer (1) is applied to the area (8) of the semiconductor layer (3) and subsequently annealed at a temperature preferably between 300° C. and 500° C. The ZnO layer (1) is preferably deposited on the III-V semiconductor layer (3) at a temperature of less than 150° C., preferably at a temperature greater than or equal to 25° C. and less than or equal to 120° C. The area (8) with reduced electrical conductivity is preferably located in a radiation emitting optoelectronic device between the active zone (4) and a connecting contact (7) in order to reduce current injection into the areas of the active zone (4) located opposite to the connecting contact (7).Type: GrantFiled: April 25, 2005Date of Patent: October 23, 2012Assignee: Osram Opto Semiconductors GmbHInventors: Stefan Illek, Wilhelm Stein, Robert Walter, Ralph Wirth
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Publication number: 20120214276Abstract: An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOX is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiOX. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.Type: ApplicationFiled: April 25, 2012Publication date: August 23, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yoshiaki OIKAWA, Hotaka MARUYAMA, Hiromichi GODO, Daisuke KAWAE, Shunpei YAMAZAKI
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Publication number: 20120208318Abstract: A semiconductor device includes a metal oxide channel and methods for forming the same. The metal oxide channel includes indium, gallium, and zinc.Type: ApplicationFiled: April 25, 2012Publication date: August 16, 2012Inventors: Randy L. Hoffman, Gregory S. Herman, Peter P. Mardilovich
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Publication number: 20120115276Abstract: There is provided an amorphous oxide semiconductor including hydrogen and at least one element of indium (In) and zinc (Zn), the amorphous oxide semiconductor containing one of hydrogen atoms and deuterium atoms of 1×1020 cm?3 or more to 1×1022 cm?3 or less, and a density of bonds between oxygen and hydrogen except bonds between excess oxygen (OEX) and hydrogen in the amorphous oxide semiconductor being 1×1018 cm?3 or less.Type: ApplicationFiled: January 18, 2012Publication date: May 10, 2012Applicant: CANON KABUSHIKI KAISHAInventors: RYO HAYASHI, HIDEYUKI OMURA, HIDEYA KUMOMI, YUZO SHIGESATO
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Patent number: 8148722Abstract: Provided are a method of manufacturing a transparent N-doped p-type ZnO semiconductor layer using a surface chemical reaction between precursors containing elements constituting thin layers, and a thin film transistor (TFT) including the p-type ZnO semiconductor layer. The method includes the steps of: preparing a substrate and loading the substrate into a chamber; injecting a Zn precursor and an oxygen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the oxygen precursor using an atomic layer deposition (ALD) technique to form a ZnO thin layer on the substrate; and injecting a Zn precursor and an nitrogen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the nitrogen precursor to form a doping layer on the ZnO thin layer.Type: GrantFiled: December 14, 2010Date of Patent: April 3, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Sang Hee Park, Chi Sun Hwang, Hye Yong Chu, Jeong Ik Lee
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Publication number: 20120056176Abstract: An object is to provide a deposition technique for depositing an oxide semiconductor film. Another object is to provide a method for manufacturing a highly reliable semiconductor element using the oxide semiconductor film. A novel sputtering target obtained by removing an alkali metal, an alkaline earth metal, and hydrogen that are impurities in a sputtering target used for deposition is used, whereby an oxide semiconductor film containing a small amount of those impurities can be deposited.Type: ApplicationFiled: August 30, 2011Publication date: March 8, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Shunpei Yamazaki
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Publication number: 20120032163Abstract: The electric characteristics of a semiconductor device including an oxide semiconductor change by irradiation with visible light or ultraviolet light. In view of the above problem, one object is to provide a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. Over an oxide insulating layer, a first oxide semiconductor layer is formed to a thickness greater than or equal to 1 nm and less than or equal to 10 nm and crystallized by heat treatment, so that a first crystalline oxide semiconductor layer is formed. A second crystalline oxide semiconductor layer with a greater thickness than the first crystalline oxide semiconductor layer is formed thereover.Type: ApplicationFiled: July 29, 2011Publication date: February 9, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Shunpei YAMAZAKI
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Patent number: 8093634Abstract: By repeatedly applying a process sequence comprising an etch process and a selective epitaxial growth process during the formation of drain and source areas in a transistor device, highly complex dopant profiles may be generated on the basis of in situ doping. Further-more, a strain material may be provided while stress relaxation mechanisms may be reduced due to the absence of any implantation processes.Type: GrantFiled: February 27, 2009Date of Patent: January 10, 2012Assignee: Globalfoundries Inc.Inventors: Anthony Mowry, Andy Wei, Andreas Gehring, Casey Scott
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Patent number: 8080484Abstract: A method for manufacturing a Group III nitride semiconductor layer according to the present invention includes a sputtering step of disposing a substrate and a target containing a Group III element in a chamber, introducing a gas for formation of a plasma in the chamber and forming a Group III nitride semiconductor layer added with Si as a dopant on the substrate by a reactive sputtering method, wherein a Si hydride is added in the gas for formation of a plasma.Type: GrantFiled: March 9, 2009Date of Patent: December 20, 2011Assignee: Showa Denko K.K.Inventors: Yasunori Yokoyama, Hisayuki Miki
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Patent number: 8076242Abstract: A method for forming an amorphous silicon thin film is disclosed. In some embodiments, a method includes loading a substrate into a reaction chamber; and conducting a plurality of deposition cycles on the substrate. Each of at least two of the cycles includes: supplying a silicon precursor to the reaction chamber during a first time period; applying radio frequency power to the reaction chamber at least partly during the first time period; stopping supplying of the silicon precursor and applying of the radio frequency power during a second time period between the first time period and an immediately subsequent deposition cycle; and supplying hydrogen plasma to the reaction chamber during a third time period between the second time period and the immediately subsequent deposition cycle. The method allows formation of an amorphous silicon film having an excellent step-coverage and a low roughness at a relatively low deposition temperature.Type: GrantFiled: April 30, 2009Date of Patent: December 13, 2011Assignee: ASM Genitech Korea Ltd.Inventors: Jong Su Kim, Hyung Sang Park, Yong Min Yoo, Hak Yong Kwon, Tae Ho Yoon
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Patent number: 8076220Abstract: A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer.Type: GrantFiled: May 13, 2010Date of Patent: December 13, 2011Assignee: Oki Semiconductor Co., Ltd.Inventors: Toshiyuki Nakamura, Satoshi Machida, Sachiko Yabe, Takashi Taguchi
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Patent number: 8076224Abstract: A process for coating a substrate at atmospheric pressure is disclosed, the process comprising the steps of vaporizing a mass of semiconductor material within a heated inert gas stream to create a fluid mixture having a temperature above the condensation temperature of the semiconductor material, directing the fluid mixture at the substrate, the substrate having a temperature below the condensation temperature of the semiconductor material thereby depositing a layer of the semiconductor material onto a surface of the substrate, extracting undeposited semiconductor material; and circulating the undeposited semiconductor material into the fluid mixture having a temperature above the condensation temperature.Type: GrantFiled: December 8, 2009Date of Patent: December 13, 2011Assignee: Calyxo GmbHInventor: Kenneth R. Kormanyos
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Publication number: 20110212571Abstract: A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit.Type: ApplicationFiled: May 10, 2011Publication date: September 1, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Jun KOYAMA
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Publication number: 20110177683Abstract: A method of making II-VI core-shell semiconductor nanowires includes providing a support; depositing a layer including metal alloy nanoparticles on the support; and heating the support and growing II-VI core semiconductor nanowires where the metal alloy nanoparticles act as catalysts and selectively cause localized growth of the core nanowires. The method further includes modifying the growth conditions and shelling the core nanowires to form II-VI core-shell semiconductor nanowires.Type: ApplicationFiled: January 19, 2010Publication date: July 21, 2011Inventors: Keith B. Kahen, Matthew Holland
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Patent number: 7958842Abstract: A substrate processing apparatus comprising: a processing chamber which is to accommodate at least one substrate; a gas supply system which is to supply processing gas into the processing chamber; an exhaust system which is to exhaust atmosphere in the processing chamber; and at least one pair of electrodes which are to bring the processing gas into an active state and which are accommodated in protection tubes such that the electrodes can be inserted into and pulled out from the protection tubes, wherein the electrodes are accommodated in the protection tube in a state where at least a portion of the electrodes is bent, and the electrodes are formed of flexible members, is disclosed.Type: GrantFiled: February 16, 2005Date of Patent: June 14, 2011Assignee: Hitachi Kokusai Electric Inc.Inventors: Shizue Ogawa, Kazuyuki Toyoda, Motonari Takebayashi, Tadashi Kontani, Nobuo Ishimaru
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Publication number: 20110097842Abstract: A method for preparing IGZO particles and a method for preparing an IGZO thin film by using the IGZO particles are disclosed. The method for preparing the IGZO particles comprises the following steps: (A) providing a solution of metal acid salts, which contains a zinc salt, an indium salt, and a gallium salt; (B) mixing the solution of the metal acid salts with a basic solution to obtain an oxide precursor; and (C) heating the oxide precursor to obtain IGZO particles.Type: ApplicationFiled: December 1, 2009Publication date: April 28, 2011Applicant: National Tsing Hua UniversityInventors: Ya-Hui Yang, Sueli Sidney Yang, Chen-Yu Kao, Kan-San Chou
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Patent number: 7902048Abstract: A method of forming a phase change layer may include providing a bivalent first precursor having germanium (Ge), a second precursor having antimony (Sb), and a third precursor having tellurium (Te) onto a surface on which the phase change layer is to be formed. The phase change layer may be formed by CVD (e.g., MOCVD, cyclic-CVD) or ALD. The composition of the phase change layer may be varied by modifying the deposition pressure, deposition temperature, and/or supply rate of reaction gas. The deposition pressure may range from about 0.001-10 torr, the deposition temperature may range from about 150-350° C., and the supply rate of the reaction gas may range from about 0-1 slm. Additionally, the above phase change layer may be provided in a via hole and bounded by top and bottom electrodes to form a storage node.Type: GrantFiled: October 22, 2007Date of Patent: March 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Woong-chul Shin, Jae-ho Lee, Youn-seon Kang
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Patent number: 7875559Abstract: Provided are a method of manufacturing a transparent N-doped p-type ZnO semiconductor layer using a surface chemical reaction between precursors containing elements constituting thin layers, and a thin film transistor (TFT) including the p-type ZnO semiconductor layer. The method includes the steps of: preparing a substrate and loading the substrate into a chamber; injecting a Zn precursor and an oxygen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the oxygen precursor using an atomic layer deposition (ALD) technique to form a ZnO thin layer on the substrate; and injecting a Zn precursor and an nitrogen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the nitrogen precursor to form a doping layer on the ZnO thin layer.Type: GrantFiled: January 8, 2008Date of Patent: January 25, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Sang Hee Park, Chi Sun Hwang, Hye Yong Chu, Jeong Ik Lee
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Patent number: 7833821Abstract: The present invention provides a method of making a Cu—In—Ga sputtering target by melting Cu, In and Ga, Cu and In or Cu and Ga to form a uniform melt with a pre-determined stoichiometry, which melt is sprayed to cause sprayed uniform melt particles to solidify into Cu—In—Ga particles with the pre-determined stoichiometry. The sputtering target is then made using the Cu—In—Ga particles.Type: GrantFiled: October 24, 2006Date of Patent: November 16, 2010Assignee: SoloPower, Inc.Inventor: Bulent M. Basol
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Publication number: 20100279462Abstract: An amorphous oxide containing hydrogen (or deuterium) is applied to a channel layer of a transistor. Accordingly, a thin film transistor having superior TFT properties can be realized, the superior TFT properties including a small hysteresis, normally OFF operation, a high ON/OFF ratio, a high saturated current, and the like. Furthermore, as a method for manufacturing a channel layer made of an amorphous oxide, film formation is performed in an atmosphere containing a hydrogen gas and an oxygen gas, so that the carrier concentration of the amorphous oxide can be controlled.Type: ApplicationFiled: July 9, 2010Publication date: November 4, 2010Applicant: CANON KABUSHIKI KAISHAInventor: Tatsuya Iwasaki
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Publication number: 20100264412Abstract: An object is to provide a transistor including an oxide layer which includes Zn and does not include a rare metal such as In or Ga. Another object is to reduce an off current and stabilize electric characteristics in the transistor including an oxide layer which includes Zn. A transistor including an oxide layer including Zn is formed by stacking an oxide semiconductor layer including insulating oxide over an oxide layer so that the oxide layer is in contact with a source electrode layer or a drain electrode layer with the oxide semiconductor layer including insulating oxide interposed therebetween, whereby variation in the threshold voltage of the transistor can be reduced and electric characteristics can be stabilized.Type: ApplicationFiled: April 13, 2010Publication date: October 21, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Hiromichi GODO, Hideyuki KISHIDA
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Publication number: 20100255660Abstract: A method of forming a solar cell incorporating a compound semiconductor is provided. The compound semiconductor is generally of the “II/VI” variety, and is formed by depositing one or more group II elements in a vapor deposition process, and then contacting the deposited layer with a liquid bath of the group VI elements. The liquid bath may comprise a pure element or a mixture of elements. The contacting is performed under a non-reactive atmosphere, or vacuum, and any fugitive vapors may be captured by a cold trap and recycled. The substrate may be subsequently annealed to remove any excess of the group VI elements, which may be similarly recycled.Type: ApplicationFiled: April 6, 2010Publication date: October 7, 2010Applicant: APPLIED MATERIALS, INC.Inventors: Kaushal K. Singh, Ralf Hofmann, Nety M. Krishna
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Publication number: 20100210065Abstract: A method of manufacturing a solar cell is provided, which can enhance the carrier concentration, so as to increase the open-circuit voltage, short-circuit current, and fill factor (F.F.), thereby raising the conversion efficiency. The method of manufacturing a solar cell in accordance with the present invention comprises a sputtering step of forming a layer containing Ib and IIIb group elements and Se on a substrate by sputtering with a target containing a Ib group element and a target containing a IIIb group element in an atmosphere containing Se; and a heat treatment step of heating the layer.Type: ApplicationFiled: February 9, 2010Publication date: August 19, 2010Applicant: TDK CORPORATIONInventors: Yasuhiro AIDA, Masato SUSUKIDA
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Publication number: 20100159640Abstract: A method and apparatus for manufacturing a semiconductor device is disclosed, which is capable of realizing an extension of a cleaning cycle for a processing chamber, the method comprising preheating a substrate; placing the preheated substrate onto a substrate-supporting unit provided in a susceptor while the preheated substrate is maintained at a predetermined height from an upper surface of the susceptor provided in a processing chamber; and forming a thin film on the preheated substrate, wherein a temperature of the preheated substrate is higher than a processing temperature for forming the thin film in the processing chamber.Type: ApplicationFiled: December 10, 2009Publication date: June 24, 2010Applicant: JUSUNG ENGINEERING CO., LTD.Inventors: Sang Ki PARK, Seong Ryong HWANG, Geun Tae CHO
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Publication number: 20100144130Abstract: A process for coating a substrate at atmospheric pressure is disclosed, the process comprising the steps of vaporizing a mass of semiconductor material within a heated inert gas stream to create a fluid mixture having a temperature above the condensation temperature of the semiconductor material, directing the fluid mixture at the substrate, the substrate having a temperature below the condensation temperature of the semiconductor material thereby depositing a layer of the semiconductor material onto a surface of the substrate, extracting undeposited semiconductor material; and circulating the undeposited semiconductor material into the fluid mixture having a temperature above the condensation temperature.Type: ApplicationFiled: December 8, 2009Publication date: June 10, 2010Inventor: Kenneth R. Kormanyos