Deposition Of Semiconductor Material On Substrate, E.g., Epitaxial Growth (epo) Patents (Class 257/E21.461)
  • Patent number: 10319861
    Abstract: The reliability of a transistor including an oxide semiconductor can be improved by suppressing a change in electrical characteristics. A transistor included in a semiconductor device includes a first oxide semiconductor film over a first insulating film, a gate insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the gate insulating film, and a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film includes a channel region in contact with the gate insulating film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: June 11, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Masami Jintyou, Yukinori Shima
  • Patent number: 10290808
    Abstract: A method and structure for providing uniform, large-area graphene by way of a transfer-free, direct-growth process. In some embodiments, a SAM is used as a carbon source for direct graphene synthesis on a substrate. For example, a SAM is formed on an insulating surface, and a metal layer is formed over the SAM. The metal layer may serve as a catalytic metal, whereby the SAM is converted to graphene following an annealing process. The SAM is deposited using a VPD process (e.g., an ALD process and/or an MLD process). In some embodiments, a CNT having a controlled diameter may be formed on the surface of a nanorod by appropriately tuning the geometry of the nanorod. Additionally, in some embodiments, a curved graphene transistor may be formed over a curved oxide surface, thereby providing a band gap in a channel region of the graphene transistor.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: May 14, 2019
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Miin-Jang Chen, Samuel C. Pan, Chung-Yen Hsieh
  • Patent number: 9837547
    Abstract: The reliability of a transistor including an oxide semiconductor can be improved by suppressing a change in electrical characteristics. A transistor included in a semiconductor device includes a first oxide semiconductor film over a first insulating film, a gate insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the gate insulating film, and a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film includes a channel region in contact with the gate insulating film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: December 5, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Masami Jintyou, Yukinori Shima
  • Patent number: 9653292
    Abstract: A method of manufacturing a thin film transistor substrate includes forming an amorphous silicon layer on a substrate, the substrate having a rectangular shape, and irradiating the amorphous silicon layer with a laser beam at a random pitch, such that the amorphous silicon layer is crystallizes into a polycrystalline silicon layer, wherein the laser beam has a major axis and a minor axis, the major axis being non-parallel with respect to sides of the substrate.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: May 16, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joonhwa Bae, Yoonho Khang
  • Patent number: 9472393
    Abstract: A silicon oxide film forming method includes: forming an amorphous silicon film, including: adsorbing an adsorbate containing silicon to a workpiece by supplying a source gas containing chlorine and silicon into a reaction chamber accommodating the workpiece, activating the source gas, and reacting the activated source gas with the workpiece; and removing chlorine contained in the adsorbate by supplying hydrogen gas into the reaction chamber and activating the hydrogen gas, and reacting the activated hydrogen gas with the adsorbate, wherein removing the chlorine is performed after adsorbing the adsorbate is performed, thereby forming the amorphous silicon film on the workpiece; and forming a silicon oxide film on the workpiece by supplying an oxidizing gas into the reaction chamber and oxidizing the amorphous silicon film, wherein forming the amorphous silicon film and forming the silicon oxide film are repeated in this order plural times.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: October 18, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toshiyuki Ikeuchi, Akira Shimizu
  • Patent number: 9472759
    Abstract: A manufacturing method of a phase change memory includes following steps. A first mask layer is formed on a dielectric layer, and a second mask layer is formed on the first mask layer. Then, the first mask layer and the second mask layer are patterned to expose a side surface of the first mask layer. A portion of the first mask layer is removed from the side surface of the first mask layer to form a columnar protrusion. After removing the second mask layer, a heating material layer is formed to conformally cover sidewalls and an upper surface of the columnar protrusion. The heating material layer on the upper surface of the columnar protrusion is removed, so as to form an annular heater from the heating material layer; and the annular heater surrounds the columnar protrusion.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: October 18, 2016
    Assignees: Ningbo Advanced Memory Technology Corporation, Being Advanced Memory Taiwan Limited
    Inventor: Shui-Chin Su
  • Patent number: 9006730
    Abstract: A metal oxide semiconductor structure and a production method thereof, the structure including: a substrate; a gate electrode, deposited on the substrate; a gate insulation layer, deposited over the gate electrode and the substrate; an IGZO layer, deposited on the gate insulation layer and functioning as a channel; a source electrode, deposited on the gate insulation layer and being at one side of the IGZO layer; a drain electrode, deposited on the gate insulation layer and being at another side of the IGZO layer; a first passivation layer, deposited over the source electrode, the IGZO layer, and the drain electrode; a second passivation layer, deposited over the first passivation layer; and an opaque resin layer, deposited over the source electrode, the second passivation layer, and the drain electrode.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: April 14, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Chin-Wen Lin, Chuan-I Huang, Chung-Chin Huang, Ted Hong Shinn
  • Patent number: 8969130
    Abstract: An amorphous region with low density is formed in an oxide insulating film containing zirconium. The amount of oxygen released from such an oxide insulating film containing zirconium by heating is large and a temperature at which oxygen is released is higher in the oxide insulating film than in a conventional oxide film (e.g., a silicon oxide film). When the insulating film is formed using a sputtering target containing zirconium in an oxygen atmosphere, the temperature of a surface on which the insulating film is formed may be controlled to be lower than a temperature at which a film to be formed starts to crystallize.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Erika Takahashi, Yuki Imoto, Yuhei Sato
  • Patent number: 8962386
    Abstract: To reduce oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film and to improve electric characteristics of a transistor including the oxide semiconductor film. A semiconductor device includes a gate electrode whose Gibbs free energy for oxidation is higher than that of a gate insulating film. In a region where the gate electrode is in contact with the gate insulating film, oxygen moves from the gate electrode to the gate insulating film, which is caused because the gate electrode has higher Gibbs free energy for oxidation than the gate insulating film. The oxygen passes through the gate insulating film and is supplied to the oxide semiconductor film in contact with the gate insulating film, whereby oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Tetsuhiro Tanaka
  • Patent number: 8937339
    Abstract: Si(1-v-w-x)CwAlxNv crystals in a mixed crystal state are formed. A method for manufacturing an easily processable Si(1-v-w-x)CwAlxNv substrate, a method for manufacturing an epitaxial wafer, a Si(1-v-w-x)CwAlxNv substrate, and an epitaxial wafer are provided. A method for manufacturing a Si(1-v-w-x)CwAlxNv substrate 10a includes the following steps. First, a Si substrate 11 is prepared. A Si(1-v-w-x)CwAlxNv layer 12 (0<v<1, 0?w<1, 0<x<1, and 0<v+w+x<1) is then grown on the Si substrate 11 by a pulsed laser deposition method.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: January 20, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Issei Satoh, Michimasa Miyanaga, Shinsuke Fujiwara, Hideaki Nakahata
  • Patent number: 8907333
    Abstract: Composite of layers which comprises a dielectric layer and a layer which comprises pyrogenic zinc oxide and is bonded to the dielectric layer. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to the dielectric layer in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm, and the zinc oxide layer is dried and then treated at temperatures of less than 200° C. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to a substrate layer or a composite of substrate layers in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm to form a zinc oxide layer, and then the zinc oxide layer and the substrate layer are treated at temperatures of less than 200° C., and then a dielectric layer is applied to the zinc oxide layer. Field-effect transistor which has the composite of layers.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: December 9, 2014
    Assignees: Evonik Degussa GmbH, Forschungszentrum Karlsruhe GmbH
    Inventors: Frank-Martin Petrat, Heiko Thiem, Sven Hill, Andre Ebbers, Koshi Okamura, Roland Schmechel
  • Patent number: 8889476
    Abstract: The present invention relates to formulations comprising a) at least two different ZnO cubanes of which at least one ZnO cubane is present in solid form under SATP conditions and at least one ZnO cubane is present in liquid form under SATP conditions, and b) at least one solvent, to processes for producing semiconductive ZnO layers from these formulations, to the use of the formulations for producing electronic components and to the electronic components themselves.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: November 18, 2014
    Assignee: Evonik Degussa GmbH
    Inventors: Heiko Thiem, Juergen Steiger, Alexey Merkulov, Duy Vu Pham, Yilmaz Aksu, Stefan Schutte, Matthias Driess
  • Patent number: 8884287
    Abstract: A semiconductor device including a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics and reliability. Film deposition is performed using an oxide semiconductor target containing an insulator (an insulating oxide, an insulating nitride, silicon oxynitride, aluminum oxynitride, or the like), typically SiO2, so that the semiconductor device in which the Si-element concentration in the thickness direction of the oxide semiconductor layer has a gradient which increases in accordance with an increase in a distance from a gate electrode is realized.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: November 11, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Takashi Shimazu, Hiroki Ohara, Toshinari Sasaki, Shunpei Yamazaki
  • Patent number: 8883555
    Abstract: A film formation is performed using a target in which a material which is volatilized more easily than gallium when heated at 400° C. to 700° C., such as zinc, is added to gallium oxide by a sputtering method with high mass-productivity which can be applied to a large-area substrate, such as a DC sputtering method or a pulsed DC sputtering method. This film is heated at 400° C. to 700° C., whereby the added material is segregated in the vicinity of a surface of the film. Another portion of the film has a decreased concentration of the added material and a sufficiently high insulating property; therefore, it can be used for a gate insulator of a semiconductor device, or the like.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: November 11, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8859402
    Abstract: A method for making epitaxial structure is provided. The method includes providing a substrate having an epitaxial growth surface, patterning the epitaxial growth surface; placing a graphene layer on the patterned epitaxial growth surface, and epitaxially growing an epitaxial layer on the epitaxial growth surface. The graphene layer includes a number of apertures to expose a part of the patterned epitaxial growth surface. The epitaxial layer is grown from the exposed part of the patterned epitaxial growth surface and through the aperture.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: October 14, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 8853059
    Abstract: A method for high temperature selenization of Cu—In—Ga metal precursor films comprises ramping the precursor film to a temperature between about 350 C and about 450 C in an inert gas and at a pressure between about 1 atmosphere and about 2 atmospheres. A partial selenization is performed at a temperature between about 350 C and about 450 C in a Se-containing atmosphere. The film is then ramped to a temperature between about 450 C and about 550 C in an inert gas and at a pressure between about 1 atmosphere and about 2 atmospheres, followed by an additional selenization step at a temperature between about 450 C and about 550 C in a Se-containing atmosphere. The film is then annealed at a temperature between about 550 C and about 650 C in an inert gas.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: October 7, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Haifan Liang, Jeroen Van Duren, Sandeep Nijhawan
  • Patent number: 8829586
    Abstract: In a miniaturized transistor, a gate insulating layer is required to reduce its thickness; however, in the case where the gate insulating layer is a single layer of a silicon oxide film, a physical limit on thinning of the gate insulating layer might occur due to an increase in tunneling current, i.e. gate leakage current. With the use of a high-k film whose relative permittivity is higher than or equal to 10 is used for the gate insulating layer, gate leakage current of the miniaturized transistor is reduced. With the use of the high-k film as a first insulating layer whose relative permittivity is higher than that of a second insulating layer in contact with an oxide semiconductor layer, the thickness of the gate insulating layer can be thinner than a thickness of a gate insulating layer considered in terms of a silicon oxide film.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Takayuki Saito, Shunpei Yamazaki
  • Patent number: 8829514
    Abstract: Disclosed herein is a thin film transistor, which includes a metal oxide semiconductor layer, an insulating layer, a gate electrode, a source electrode and a drain electrode. The metal oxide semiconductor layer includes a channel region having at least one first region and a second region. The first region has an oxygen vacancy concentration greater than an oxygen vacancy concentration of the second region. The second region surrounds the first region. A method for manufacturing the thin film transistor is disclosed as well.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: September 9, 2014
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chun-Hung Liao, Wei-Tsung Chen
  • Patent number: 8815711
    Abstract: A manufacturing apparatus for a semiconductor device, including: a reaction chamber configured to perform film formation on a wafer; a process gas supplying mechanism provided in an upper part of the reaction chamber and configured to introduce process gas to an interior of the reaction chamber; a gas discharging mechanism provided in a lower part of the reaction chamber and configured to discharge gas from the reaction chamber; a supporting member configured to hold the wafer; a cleaning gas supplying mechanism provided in an outer periphery of the supporting member and configured to emit cleaning gas in an outer periphery direction below an upper end of the supporting member; a heater configured to heat the wafer; and a rotary driving mechanism configured to rotate the wafer.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: August 26, 2014
    Assignees: NuFlare Technology, Inc., Denso Corporation, Toyota Jidosha Kabushiki Kaisha
    Inventors: Kunihiko Suzuki, Hideki Ito, Hidekazu Tsuchida, Isaho Kamata, Masahiko Ito
  • Patent number: 8809115
    Abstract: To provide a method for manufacturing a thin film transistor in which contact resistance between an oxide semiconductor layer and source and drain electrode layers is small, the surfaces of the source and drain electrode layers are subjected to sputtering treatment with plasma and an oxide semiconductor layer containing In, Ga, and Zn is formed successively over the source and drain electrode layers without exposure of the source and drain electrode layers to air.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Masashi Tsubuku
  • Patent number: 8802489
    Abstract: A device for depositing an organic material includes a substrate; a mask having an opening portion and a shield portion; a fixing member for fixing the substrate and the mask to each other; a deposition source comprising a plurality of nozzles arranged in a first direction and configured to spray the organic material; and a plurality of shield plates near the plurality of nozzles on the deposition source. An angle ? between the substrate and a line extended from a distal end of one of the nozzles to a center of a distal end of a corresponding one of the shield plates is greater than or equal to a taper angle ? of the shield portion of the mask.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: August 12, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Ho Choi, Hyun Choi, Sung-Gon Kim, Min-Gyu Seo
  • Patent number: 8796069
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: August 5, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 8790969
    Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. Several devices are, thus, provided. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: July 29, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Mondo, Markus Gerhard Andreas Muller, Thomas Kormann
  • Patent number: 8753920
    Abstract: Provided is a precursor composition for an oxide semiconductor. The precursor composition for the oxide semiconductor includes a metal complex compound formed by a metal ion and an organic ligand, wherein the precursor composition is represented by the following Formula 1. MAn ??(Formula 1) Herein, M is a metal ion, A is an organic ligand which includes ?-substituted carboxylate, and n is a natural number.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: June 17, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Bo Sung Kim, Doo-Hyoung Lee, Yeon-Taek Jeong, Ki-Beom Lee, Young-Min Kim, Tae-Young Choi, Seon-Pil Jang, Kang-Moon Jo
  • Patent number: 8753961
    Abstract: A method of nucleating and growing oxygen precipitates during a pad oxidation process. The nucleating is performed during in the oxidation furnace prior to the pad oxide growth. At least a portion of the growth of the oxygen precipitates occurs during the pad oxide growth. The oxygen precipitates are of sufficient concentration and size in lightly doped p-type wafers for effective gettering of heavy metals is deep submicron transistor, integrated circuit manufacturing flows.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Bradley David Sucher
  • Patent number: 8748222
    Abstract: A method for manufacturing oxide thin film transistors includes steps of: forming a gate, a drain electrode, a source electrode, and an oxide semiconductor layer respectively. The oxide semiconductor layer is formed on the gate electrode; the drain electrode and the source electrode are formed at two opposite sides of the oxide semiconductor layer. The method further includes a step of depositing a dielectric layer of silicon oxide, and a reacting gas for depositing the silicon oxide includes silane and nitrous oxide. A flow rate of nitrous oxide is in a range from 10 to 200 standard cubic centimeters per minute (SCCM). Oxide thin film transistors manufactured by above method has advantages of low leakage, high mobility, and other integrated circuit member can be directly formed on the thin film transistor array substrate of a display device.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: June 10, 2014
    Assignee: E Ink Holdings Inc.
    Inventors: Ted-Hong Shinn, Henry Wang, Fang-An Shu, Yao-Chou Tsai
  • Patent number: 8748215
    Abstract: One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming an oxide component over a base component; forming a first oxide crystal component which grows from a surface toward an inside of the oxide component by heat treatment, and leaving an amorphous component just above a surface of the base component; and stacking a second oxide crystal component over the first oxide crystal component. In particular, the first oxide crystal component and the second oxide crystal component have common c-axes. Same-axis (axial) growth in the case of homo-crystal growth or hetero-crystal growth is caused.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8748889
    Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Hitomi Sato, Kosei Noda, Yuta Endo, Mizuho Ikarashi, Keitaro Imai, Atsuo Isobe, Yutaka Okazaki
  • Patent number: 8716061
    Abstract: In a thin film transistor which uses an oxide semiconductor, buffer layers containing indium, gallium, zinc, oxygen, and nitrogen are provided between the oxide semiconductor layer and the source and drain electrode layers.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: May 6, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Tetsunori Maruyama, Yuki Imoto, Yuji Asano, Junichi Koezuka
  • Publication number: 20140120657
    Abstract: A method is provided for fabricating a back channel etching (BCE) oxide thin film transistor (TFT) for a liquid crystal display. The method includes forming a first metal layer having a first portion and a second portion over a substrate, depositing a gate insulator over the first metal layer, and disposing a semiconductor layer over the gate insulator. The method also includes depositing a half-tone photoresist to cover a first portion of the semiconductor layer and the first portion of the first metal layer. The half-tone photoresist has a first portion and a second portion thicker than the first portion. The first portion has a via hole above the second portion of the first metal layer. The second portion of the half-tone photoresist covers the first portion of the first metal layer.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: Apple Inc.
    Inventors: Ming-Chin Hung, Kyung Wook Kim, Chun-Yao Huang, Young Bae Park, Shih Chang Chang, John Z. Zhong
  • Patent number: 8691623
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: April 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 8652870
    Abstract: A method for high temperature selenization of Cu—In—Ga metal precursor films comprises a partial selenization at a temperature between about 350 C and about 450 C in a Se-containing atmosphere followed by a more fully selenization step at a temperature between about 550 C and about 650 C in a Se-containing atmosphere. The Se-containing component of the atmosphere is removed through a rapid gas exchange process and the CIGS film is annealed to influence the Ga distribution throughout the depth of the film.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: February 18, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Haifan Liang
  • Patent number: 8647929
    Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: February 11, 2014
    Assignee: Infineon Technologies AG
    Inventor: Jin-Ping Han
  • Patent number: 8647941
    Abstract: A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: February 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Publication number: 20140038344
    Abstract: Embodiments relate to a method including forming a layer of copper zinc tin sulfide (CZTS) on a first layer of molybdenum (Mo) and annealing the CZTS layer and the first Mo layer to form a layer of molybdenum disulfide (MoS2) between the layer of CZTS and the first layer of Mo. The method includes forming a back contact on a first surface of the CZTS layer opposite the first Mo layer and separating the first Mo layer and the MoS2 layer from the CZTS layer to expose a second surface of the CZTS layer opposite the first surface. The method further includes forming a buffer layer on the second surface of the CZTS layer.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 6, 2014
    Applicant: International Business Machines Corporation
    Inventors: Nestor A. Bojarczuk, Keith E. Fogel, Supratik Guha, Byungha Shin
  • Patent number: 8642452
    Abstract: Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
  • Publication number: 20140014943
    Abstract: Sol-gel-processed thin-film transistors (TFTs) with amorphours Y—In—Zn—O (YIZO) as an active layer are fabricated with various mole ratios of Y, which indicates that Y3+ could play the role of carrier suppressor in InZnO (IZO) systems and reduce off current of YIZO-TFT and its channel mobility, threshold voltage, subthreshold swing voltage, and on/off ratio.
    Type: Application
    Filed: July 16, 2012
    Publication date: January 16, 2014
    Applicant: NATIONAL CHUNG CHENG UNIVERSITY
    Inventors: Chu-Chi TING, Hsieh-Ping CHANG
  • Patent number: 8629432
    Abstract: A semiconductor device including a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics and reliability. Film deposition is performed using an oxide semiconductor target containing an insulator (an insulating oxide, an insulating nitride, silicon oxynitride, aluminum oxynitride, or the like), typically SiO2, so that the semiconductor device in which the Si-element concentration in the thickness direction of the oxide semiconductor layer has a gradient which increases in accordance with an increase in a distance from a gate electrode is realized.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: January 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Takashi Shimazu, Hiroki Ohara, Toshinari Sasaki, Shunpei Yamazaki
  • Patent number: 8617966
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: December 31, 2013
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Patent number: 8610119
    Abstract: A plasma hydrogenated region in the dielectric layer of a semiconductor thin film transistor (TFT) structure improves the stability of the TFT. The TFT is a multilayer structure including an electrode, a dielectric layer disposed on the electrode, and a metal oxide semiconductor on the dielectric. Exposure of the dielectric layer to a hydrogen containing plasma prior to deposition of the semiconductor produces a plasma hydrogenated region at the semiconductor-dielectric interface. The plasma hydrogenated region incorporates hydrogen which decreases in concentration from semiconductor/dielectric interface into the bulk of one or both of the dielectric layer and the semiconductor layer.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: December 17, 2013
    Assignee: 3M Innovative Properties Company
    Inventors: Steven D. Theiss, David H. Redinger
  • Patent number: 8610120
    Abstract: A photolithography step and an etching step for forming an island-shaped semiconductor layer is omitted, and a liquid crystal display device is manufactured through the following four photolithography steps: a step for forming a gate electrode (including a wiring or the like formed from the same layer), a step for forming a source electrode and a drain electrode (including a wiring or the like formed from the same layer), a step for forming a contact hole (including removal of an insulating layer or the like in a region other than the contact hole), and a step for forming a pixel electrode (including a wiring or the like formed from the same layer). In the step of forming the contact hole, a groove portion in which the semiconductor layer is removed is formed, so that formation of parasitic channels is prevented.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: December 17, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Miyake, Ryo Arasawa, Koji Kusunoki
  • Patent number: 8597977
    Abstract: In a thin film transistor which uses an oxide semiconductor, buffer layers containing indium, gallium, zinc, oxygen, and nitrogen are provided between the oxide semiconductor layer and the source and drain electrode layers.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 3, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Tetsunori Maruyama, Yuki Imoto, Yuji Asano, Junichi Koezuka
  • Patent number: 8598018
    Abstract: The present invention provides a method of forming an electrode having reduced corrosion and water decomposition on a surface thereof. A conductive layer is deposited on a substrate. The conductive layer is partially oxidized by an oxygen plasma process to convert a portion thereof to an oxide layer thereby forming the electrode. The oxide layer is free of surface defects and the thickness of the oxide layer is from about 0.09 nm to about 10 nm and ranges therebetween, controllable with 0.2 nm precision.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Azdakani, Shafaat Ahmed, Hariklia Deligianni, Dario L. Goldfarb, Stefan Harrer, Hongbo Peng, Stanislav Polonsky, Stephen Rossnagel, Xiaoyan Shao, Gustavo A. Stolovitzky
  • Publication number: 20130316519
    Abstract: Techniques for enhancing energy conversion efficiency in chalcogenide-based photovoltaic devices by improved grain structure and film morphology through addition of urea into a liquid-based precursor are provided. In one aspect, a method of forming a chalcogenide film includes the following steps. Metal chalcogenides are contacted in a liquid medium to form a solution or a dispersion, wherein the metal chalcogenides include a Cu chalcogenide, an M1 and an M2 chalcogenide, and wherein M1 and M2 each include an element selected from the group consisting of: Ag, Mn, Mg, Fe, Co, Cd, Ni, Cr, Zn, Sn, In, Ga, Al, and Ge. At least one organic additive is contacted with the metal chalcogenides in the liquid medium. The solution or the dispersion is deposited onto a substrate to form a layer. The layer is annealed at a temperature, pressure and for a duration sufficient to form the chalcogenide film.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 28, 2013
    Applicant: International Business Machines Corporation
    Inventors: David Brian Mitzi, Xiaofeng Qiu
  • Patent number: 8586457
    Abstract: A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25?0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: November 19, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Haifan Liang, Sang Lee, Wei Liu, Sandeep Nijhawan, Jeroen Van Duren
  • Publication number: 20130295748
    Abstract: A method for high temperature selenization of Cu—In—Ga metal precursor films comprises ramping the precursor film to a temperature between about 350 C and about 450 C in an inert gas and at a pressure between about 1 atmosphere and about 2 atmospheres. A partial selenization is performed at a temperature between about 350 C and about 450 C in a Se-containing atmosphere. The film is then ramped to a temperature between about 450 C and about 550 C in an inert gas and at a pressure between about 1 atmosphere and about 2 atmospheres, followed by an additional selenization step at a temperature between about 450 C and about 550 C in a Se-containing atmosphere. The film is then annealed at a temperature between about 550 C and about 650 C in an inert gas.
    Type: Application
    Filed: May 1, 2012
    Publication date: November 7, 2013
    Applicant: Intermolecular Inc.
    Inventors: Haifan Liang, Jeroen Van Duren, Sandeep Nijhawan
  • Publication number: 20130256652
    Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.
    Type: Application
    Filed: July 19, 2012
    Publication date: October 3, 2013
    Inventors: Yong Su LEE, Yoon Ho Khang, Dong Jo Kim, Hyun Jae Na, Sang Ho Park, Se Hwan Yu, Chong Sup Chang
  • Publication number: 20130260536
    Abstract: A method is provided for controlling printed ink horizontal cross-sectional areas using fluoropolymer templates. The method initially forms a fluoropolymer template overlying a substrate. The fluoropolymer template has a horizontal first cross-sectional dimension. Then, a primary ink is printed overlying the fluoropolymer template having a horizontal second cross-sectional dimension less than the first cross-sectional dimension. In the case of a fluoropolymer line having a template length greater than a template width, where the template width is the first cross-sectional dimension, printing the primary ink entails printing a primary ink line having an ink length greater than an ink width, where the ink width is the second cross-sectional dimension. In one aspect, the method prints a plurality of primary ink layers, each primary ink layer having an ink width less than the template width. Each overlying primary ink layer can be printed prior to solvents in underlying primary ink layers evaporating.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 3, 2013
    Inventors: Kurt ULMER, Kanan PUNTAMBEKAR, Lisa H. STECKER
  • Patent number: 8541803
    Abstract: Disclosed re-emitting semiconductor constructions (RSCs) may provide full-color RGB or white-light emitting devices that are free of cadmium. Some embodiments may include a potential well that comprises a III-V semiconductor and that converts light of a first photon energy to light of a smaller photon energy, and a window that comprises a II-VI semiconductor having a band gap energy greater than the first photon energy. Some embodiments may include a potential well that converts light having a first photon energy to light having a smaller photon energy and that comprises a II-VI semiconductor that is substantially Cd-free. Some embodiments may include a potential well that comprises a first III-V semiconductor and that converts light having a first photon energy to light having a smaller photon energy, and a window that comprises a second III-V semiconductor and that has a band gap energy greater than the first photon energy.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: September 24, 2013
    Assignee: 3M Innovative Properties Company
    Inventors: Terry L. Smith, Michael A. Haase, Thomas J. Miller, Xiaoguang Sun
  • Patent number: RE44657
    Abstract: A circuit with a large load driving capability, which is structured by single polarity TFTs, is provided. With a capacitor (154) formed between a gate electrode and an output electrode of a TFT (152), the electric potential of the gate electrode of the TFT (152) is increased by a boot strap and normal output with respect to an input signal is obtained without amplitude attenuation of an output signal due to the TFT threshold value. In addition, a capacitor (155) formed between a gate electrode and an output electrode of a TFT (153) compensates for increasing the electric potential of the gate electrode of the TFT (152), and a larger load driving capability is obtained.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: December 24, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Miyake, Yutaka Shionoiri