Using Liquid Deposition (epo) Patents (Class 257/E21.464)
  • Patent number: 11746290
    Abstract: A nanocrystal particle including at least one semiconductor material and at least one halogen element, the nanocrystal particle including: a core comprising a first semiconductor nanocrystal; and a shell surrounding the core and comprising a crystalline or amorphous material, wherein the halogen element is present as being doped therein or as a metal halide.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: September 5, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunki Kim, Shin Ae Jun, Eun Joo Jang, Yongwook Kim, Tae Gon Kim, Yuho Won, Taekhoon Kim, Hyo Sook Jang
  • Patent number: 8945980
    Abstract: A method is provided for forming an alkali metal-doped solution-processed metal chalcogenide. A first solution is formed that includes a first material group of metal salts, metal complexes, or combinations thereof, dissolved in a solvent. The first material group may include one or more of the following elements: copper (Cu), indium (In), and gallium (Ga). An alkali metal-containing material is added to the first solution, and the first solution is deposited on a conductive substrate. The alkali metal-containing material may be sodium (Na). An alkali metal-doped first intermediate film results, comprising metal precursors from corresponding members of the first material group. Then, thermally annealing is performed in an environment of selenium (Se), Se and hydrogen (H2), hydrogen selenide (H2Se), sulfur (S), S and H2, hydrogen sulfide (H2S), or combinations thereof. The metal precursors in the alkali metal-doped first intermediate film are transformed, and an alkali metal-doped chalcogenide layer is formed.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: February 3, 2015
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Sean Vail, Gary Foley, Alexey Koposov
  • Patent number: 8907333
    Abstract: Composite of layers which comprises a dielectric layer and a layer which comprises pyrogenic zinc oxide and is bonded to the dielectric layer. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to the dielectric layer in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm, and the zinc oxide layer is dried and then treated at temperatures of less than 200° C. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to a substrate layer or a composite of substrate layers in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm to form a zinc oxide layer, and then the zinc oxide layer and the substrate layer are treated at temperatures of less than 200° C., and then a dielectric layer is applied to the zinc oxide layer. Field-effect transistor which has the composite of layers.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: December 9, 2014
    Assignees: Evonik Degussa GmbH, Forschungszentrum Karlsruhe GmbH
    Inventors: Frank-Martin Petrat, Heiko Thiem, Sven Hill, Andre Ebbers, Koshi Okamura, Roland Schmechel
  • Patent number: 8907337
    Abstract: Inorganic semiconducting compounds, composites and compositions thereof, and related device structures.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: December 9, 2014
    Assignee: Northwestern University
    Inventors: Tobin J. Marks, Antonio Facchetti, Lian Wang, Myung-Han Yoon, Yu Yang
  • Patent number: 8883617
    Abstract: One aspect in the present disclosure relates to a method for manufacturing an amorphous metal oxide semiconductor. In an exemplary embodiment, a film is deposited on a substrate from a mixed solution as a starting element. For example, the mixed solution includes at least an indium alkoxide and a zinc alkoxide in a solvent. The film made from the mixed solution on the substrate is cured by thermal-annealing in a water vapor atmosphere, at a temperature range of, for example, 210 to 275 degrees Celsius, inclusive.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: November 11, 2014
    Assignees: Panasonic Corporation, Cambridge Enterprise Ltd.
    Inventors: Yoshihisa Yamashita, Kulbinder Kumar Banger, Henning Sirringhaus
  • Patent number: 8778731
    Abstract: A method of manufacturing silver (Ag)-doped zinc oxide (ZnO) nanowires and a method of manufacturing an energy conversion device are provided. In the method of manufacturing Ag-doped ZnO nanowires, the Ag-doped nanowires are grown by a low temperature hydrothermal synthesis method using a Ag-containing aqueous solution.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: July 15, 2014
    Assignees: Samsung Electronics Co., Ltd., Industry-University Cooperation Foundation Hanyang University
    Inventors: Hyun-jin Kim, Young-jun Park, Sang-hyo Lee, Jin-pyo Hong, Jun-seok Lee
  • Patent number: 8772762
    Abstract: Provided is an organic electroluminescent device including: a substrate (11, 101); a first electrode (12, 102) formed on the substrate (11, 101) and including a pixel region; a partition wall (23, 203) formed on the substrate (11, 101), partitioning the first electrode (12, 102), and including a surface with a recessed and projected form; a luminescent medium layer (19, 109) formed on the pixel region and the partition wall (23, 203), a film thickness of the partition wall (23, 203) being uneven according to the recessed and projected form; and a second electrode (17, 107) formed on the luminescent medium layer (19, 109).
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 8, 2014
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Shingo Kaneta, Yuki Yasu, Ryo Syoda, Noriko Morikawa, Eiichi Kitazume
  • Patent number: 8753920
    Abstract: Provided is a precursor composition for an oxide semiconductor. The precursor composition for the oxide semiconductor includes a metal complex compound formed by a metal ion and an organic ligand, wherein the precursor composition is represented by the following Formula 1. MAn ??(Formula 1) Herein, M is a metal ion, A is an organic ligand which includes ?-substituted carboxylate, and n is a natural number.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: June 17, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Bo Sung Kim, Doo-Hyoung Lee, Yeon-Taek Jeong, Ki-Beom Lee, Young-Min Kim, Tae-Young Choi, Seon-Pil Jang, Kang-Moon Jo
  • Patent number: 8685779
    Abstract: A method is provided for forming a Group VA-doped solution-processed metal chalcogenide. The method forms a first solution including a first material group, dissolved in solvent. A Group VA-containing material is added to the first solution. The Group VA-containing material may include arsenic (As), antimony (Sb), bismuth (Bi), or combinations thereof. The first solution is deposited on a conductive substrate, and a Group VA-doped first intermediate film is formed comprising metal precursors from corresponding members of the first material group. Thermal annealing is performed in an environment of selenium (Se), Se and hydrogen (H2), hydrogen selenide (H2Se), sulfur (S), S and H2, hydrogen sulfide (H2S), or combinations thereof. As a result, the metal precursors in the Group VA-doped first intermediate film are transformed, forming a Group VA-doped metal chalcogenide layer. In one aspect, an antimony-doped Cu—In—Ga—Se chalcogenide (CIGS) is formed.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 1, 2014
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Sean Vail, Alexey Koposov, Gary Foley
  • Patent number: 8673752
    Abstract: A method of growing an epitaxial semiconductor structure is disclosed. The growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: March 18, 2014
    Assignee: Athenaeum, LLC
    Inventor: Eric Ting-Shan Pan
  • Publication number: 20140017884
    Abstract: In the present invention, copper(I) selenide (Cu2-xSe) nanoparticles are fabricated by pyrolysis in an inert atmosphere. Uniformly dispersed Cu2-xSe particles are synthesized by altering Cu/Se ratio, the concentration of Se Precursors (TOP Se), reaction time and temperature. Analysis by inductively coupled plasma atomic emission spectroscopy (ICP-AES) of said Cu2-xSe nanoparticles reveals that the composition of the nanoparticles is Cu 1.95Se, wherein x=0.05. In addition, Cu2-xSe is dissolved in ethanol to deposit thin films by electrophoretical deposition (EPD) in an inert atmosphere, wherein a positive electrode and a negative electrode are employed. The positive electrode is made of stainless steel plate and the negative electrode is made of indium tin oxide on a glass substrate. Investigations on properties and surface morphology thereof in different electrophoretical conditions are carried out. The rate of EPD is found to significantly influence the quality of thin films.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: National Chung Cheng University
    Inventors: Chu-Chi Ting, Wen-Yuan Lee
  • Patent number: 8541294
    Abstract: A method of growing an epitaxial film and transferring it to an assembly substrate is disclosed. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: September 24, 2013
    Assignee: Athenaeum LLC
    Inventor: Eric Ting-Shan Pan
  • Patent number: 8530342
    Abstract: A method of growing an epitaxial film and transferring it to an assembly substrate is disclosed. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: September 10, 2013
    Assignee: Athenaeum, LLC
    Inventor: Eric Ting-Shan Pan
  • Patent number: 8507370
    Abstract: A method of growing an epitaxial film and transferring it to an assembly substrate is disclosed. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: August 13, 2013
    Assignee: Athenaeum LLC
    Inventor: Eric Ting-Shan Pan
  • Patent number: 8507371
    Abstract: A method of growing an epitaxial semiconductor structure is disclosed. The growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: August 13, 2013
    Assignee: Athenaeum LLC
    Inventor: Eric Ting-Shan Pan
  • Patent number: 8486753
    Abstract: Disclosed are a patterning method of a metal oxide thin film using nanoimprinting, and a manufacturing method of a light emitting diode (LED). The method for forming a metal oxide thin film pattern using nanoimprinting includes: coating a photosensitive metal-organic material precursor solution on a substrate; preparing a mold patterned to have a protrusion and depression structure; pressurizing the photosensitive metal-organic material precursor coating layer with the patterned mold; forming a cured metal oxide thin film pattern by heating the pressurized photosensitive metal-organic material precursor coating layer or by irradiating ultraviolet rays to the pressurized photosensitive metal-organic material precursor coating layer while being heated; and removing the patterned mold from the metal oxide thin film pattern, and selectively further includes annealing the metal oxide thin film pattern.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: July 16, 2013
    Assignee: Korea Institute of Machinery and Materials
    Inventors: Hyeong Ho Park, Jun Ho Jeong, Ki Don Kim, Dae Geun Choi, Jun Hyuk Choi, Ji Hye Lee, Soon Won Lee
  • Publication number: 20130112969
    Abstract: A method of manufacturing silver (Ag)-doped zinc oxide (ZnO) nanowires and a method of manufacturing an energy conversion device are provided. In the method of manufacturing Ag-doped ZnO nanowires, the Ag-doped nanowires are grown by a low temperature hydrothermal synthesis method using a Ag-containing aqueous solution.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 9, 2013
    Applicants: Industry-University Cooperation Foundation Hanyang University, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Samsung Electronics Co., Ltd., Industry-University Cooperation Foundation Hany
  • Patent number: 8395150
    Abstract: Inorganic semiconducting compounds, composites and compositions thereof, and related device structures.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: March 12, 2013
    Assignee: Northwestern University
    Inventors: Tobin J. Marks, Antonio Facchetti, Lian Wang, Myung-Han Yoon, Yu Yang
  • Publication number: 20130005124
    Abstract: One aspect in the present disclosure relates to a method for manufacturing an amorphous metal oxide semiconductor. In an exemplary embodiment, a film is deposited on a substrate from a mixed solution as a starting element. For example, the mixed solution includes at least an indium alkoxide and a zinc alkoxide in a solvent. The film made from the mixed solution on the substrate is cured by thermal-annealing in a water vapor atmosphere, at a temperature range of, for example, 210 to 275 degrees Celsius, inclusive.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 3, 2013
    Applicants: CAMBRIDGE ENTERPRISE LTD., PANASONIC CORPORATION
    Inventors: Yoshihisa YAMASHITA, Kulbinder Kumar BANGER, Henning SIRRINGHAUS
  • Publication number: 20120329209
    Abstract: Disclosed are a method for forming a metal oxide pattern and a method of manufacturing a thin film transistor using the patterned metal oxide. The method for forming a metal oxide pattern includes: preparing an ink composition including at least one metal oxide precursor or metal oxide nanoparticle, and a solvent; ejecting the ink composition on a substrate to form a pattern on the substrate; and photosintering the formed pattern. Herein, the metal oxide precursor is ionic.
    Type: Application
    Filed: June 20, 2012
    Publication date: December 27, 2012
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Yong-Won SONG, Jae-Min HONG, Jung Ah LIM, Hak-Sung KIM, Seong-Ji KWON
  • Publication number: 20120306053
    Abstract: This invention discloses a solution-based synthesis of cesium tin tri-iodide (CsSnI3) film. More specifically, the invention is directed to a solution-based drop-coating synthesis of cesium tin tri-iodide (CsSnI3) films. CsSnI3 films are ideally suited for a wide range of applications such as light emitting and photovoltaic devices.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 6, 2012
    Inventors: Kai Shum, Zhuo Chen, Yuhang Ren
  • Publication number: 20120288988
    Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor layer, a method for manufacturing a photoelectric conversion device, and a semiconductor layer forming solution which are able to easily manufacture a good semiconductor layer having a desired thickness. To accomplish this object, a starting solution containing a metallic element, a chalcogen organic compound and a Lewis base organic compound is initially produced. Next, heating the starting solution produces fine particles. The fine particles contain a metal chalcogenide which is a compound of the metallic element and a chalcogen element included in the chalcogen organic compound. A semiconductor layer is formed by using a semiconductor layer forming solution in which the fine particles are dispersed.
    Type: Application
    Filed: December 16, 2010
    Publication date: November 15, 2012
    Applicant: KYOCERA CORPORATION
    Inventors: Seiichiro Inai, Daisuke Nishimura, Isamu Tanaka
  • Publication number: 20120280228
    Abstract: The present invention relates to a method for producing an electronic component, in particular a field-effect transistor (FET), comprising at least one substrate, at least one dielectric, and at least one semiconducting metal oxide, wherein the dielectric or a precursor compound thereof based on organically modified silicon oxide compounds, in particular based on silsequioxanes and/or siloxanes, can be processed out of solution, and is thermally treated at a low temperature from room temperature to 350° C., and the semiconductive metal oxide, in particular ZnO or a precursor compound thereof, can also be processed from solution at a low temperature from room temperature to 350° C.
    Type: Application
    Filed: December 3, 2010
    Publication date: November 8, 2012
    Applicant: BASF SE
    Inventors: Friederike Fleischhaker, Veronika Wloka, Thomas Kaiser
  • Publication number: 20120282730
    Abstract: An ink composition includes a solvent system, a plurality of metal chalcogenide nanoparticles, at least one of metal ions and metal complex ions and a sodium source. The at least one of the metal ions and the metal complex ions are distributed on the surface of the metal chalcogenide nanoparticles and adapted to disperse the metal chalcogenide nanoparticles in the solvent system. The sodium source is dispersed in the solvent system and/or is included in at least one of the metal chalcogenide nanoparticle, the metal ions and the metal complex ions. The metals of the metal chalcogenide nanoparticles, the metal ions and the metal complex ions are selected from a group consisted of group I, group II, group III, group IV elements of periodic table, and sodium and include all metal elements of a chalcogenide semiconductor material.
    Type: Application
    Filed: April 3, 2012
    Publication date: November 8, 2012
    Inventors: Yueh-Chun Liao, Feng-Yu Yang, Ching Ting
  • Patent number: 8273669
    Abstract: A method for forming a passivated densified nanoparticle thin film on a substrate in a chamber is disclosed. The method includes depositing a nanoparticle ink on a first region on the substrate, the nanoparticle ink including a set of Group IV semiconductor particles and a solvent. The method also includes heating the nanoparticle ink to a first temperature between about 30° C. and about 400° C., and for a first time period between about 1 minute and about 60 minutes, wherein the solvent is substantially removed, and a porous compact is formed. The method further includes flowing an oxidizer gas into the chamber; and heating the porous compact to a second temperature between about 600° C. and about 1000° C., and for a second time period of between about 5 seconds and about 1 hour; wherein the passivated densified nanoparticle thin film is formed.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: September 25, 2012
    Assignee: Innovalight, Inc.
    Inventors: Dmitry Poplavskyy, Maxim Kelman, Mason Terry
  • Publication number: 20120227811
    Abstract: The present invention describes a method of producing a photovoltaic solar cell with stoichiometric p-type copper indium gallium diselenide (CuInxGa1-xSe2) (abbreviated CIGS) as its absorber layer and II-IV semiconductor layers as the n-type layers with electrodeposition of all these layers. The method comprises a sequence of novel procedures and electrodeposition conditions with an ionic liquid approach to overcome the technical challenges in the field for low-cost and large-area production of CIGS solar cells with the following innovative advantages over the prior art: (a) low-cost and large-area electrodeposition of CIGS in one pot with no requirement of post-deposition thermal sintering or selenization; (b) low-cost and large-area electrodeposition of n-type II-VI semiconductors for the completion of the CIGS solar cell production; and (c) low-cost and large-area deposition of a buffer layer of CdS or other compounds with a simple chemical bath method.
    Type: Application
    Filed: September 8, 2010
    Publication date: September 13, 2012
    Applicant: THE UNIVERSITY OF WESTERN ONTARIO
    Inventors: Leo W. M. Lau, Zhifeng Ding, David Anthony Love, Mohammad Harati, Jun Yang
  • Publication number: 20120214293
    Abstract: Aspects of the present inventions include an electrodeposition solution for deposition of a thin film that includes a Group VA material, a method of electroplating to deposit a thin film that includes a Group VA material, among others.
    Type: Application
    Filed: June 3, 2011
    Publication date: August 23, 2012
    Inventors: Serdar Aksu, Sarah Lastella, Mustafa Pinarbasi
  • Publication number: 20120153295
    Abstract: Radiation detector. The detector includes an ionic junction having an ionically bonded wide band gap material having a first region dominated by positively charged ionic defects in intimate contact with a second region dominated by negatively charged ionic defects forming depleted regions on both sides of the junction resulting in a built-in electric field. The detector also includes an ionic junction having a first ionically bonded wide band gap material dominated by positively charged ionic defects in intimate contact with a second ionically bonded wide band gap material dominated by negatively charged ionic defects forming depleted regions on both sides of the junction resulting in a built-in electric field. Circuit means are provided to establish a voltage across the junction so that radiation impinging upon the junction will cause a current to flow in the circuit.
    Type: Application
    Filed: February 25, 2011
    Publication date: June 21, 2012
    Applicant: Massachusetts Institute of Technology
    Inventors: Harry L. Tuller, Sean R. Bishop
  • Patent number: 8193078
    Abstract: A method of growing an epitaxial film and transferring it to an assembly substrate is disclosed. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: June 5, 2012
    Assignee: Athenaeum, LLC
    Inventor: Eric Ting-Shan Pan
  • Publication number: 20120115276
    Abstract: There is provided an amorphous oxide semiconductor including hydrogen and at least one element of indium (In) and zinc (Zn), the amorphous oxide semiconductor containing one of hydrogen atoms and deuterium atoms of 1×1020 cm?3 or more to 1×1022 cm?3 or less, and a density of bonds between oxygen and hydrogen except bonds between excess oxygen (OEX) and hydrogen in the amorphous oxide semiconductor being 1×1018 cm?3 or less.
    Type: Application
    Filed: January 18, 2012
    Publication date: May 10, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: RYO HAYASHI, HIDEYUKI OMURA, HIDEYA KUMOMI, YUZO SHIGESATO
  • Patent number: 8158517
    Abstract: An object of the present invention is to provide a method for manufacturing a display device by improving the utilization efficiency of materials and simplifying manufacturing process. Another object of the invention is to provide a technique for forming a pattern such as a wiring having a predetermined shape included in a display device with good controllability. A method for manufacturing a wiring substrate of the invention includes the steps of: forming a first region having a subject material; modifying the surface of the subject material partly to form a second region having a boundary with respect to the first region; continuously discharging a composition containing a conductive material to a part of the first region across the boundary and the second region; solidifying the composition to form a conductive layer; and removing the conductive layer formed in a part of the first region across the boundary.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: April 17, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroko Yamamoto, Ryo Tokumaru
  • Publication number: 20120060928
    Abstract: This invention relates to processes for preparing films of CTS and CZTS and their selenium analogues on a substrate. Such films are useful in the preparation of photovoltaic devices. This invention also relates to processes for preparing coated substrates and for making photovoltaic devices.
    Type: Application
    Filed: May 21, 2010
    Publication date: March 15, 2012
    Applicant: E.I. DU PONT DE NEMOURS AND COMPANY
    Inventors: Lynda Kaye Johnson, Meijun Lu, John W. Catron, JR., Daniela Rodica Radu
  • Patent number: 8097877
    Abstract: Inorganic semiconducting compounds, composites and compositions thereof, and related device structures.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: January 17, 2012
    Assignee: Northwestern University
    Inventors: Tobin J. Marks, Antonio Facchetti, Lian Wang, Myung-Han Yoon, Yu Yang
  • Publication number: 20110315982
    Abstract: The present invention relates to a process for producing semiconductive indium oxide layers, in which a substrate is coated with a liquid, anhydrous composition comprising a) at least one indium alkoxide and b) at least one solvent, optionally dried and thermally treated at temperatures greater than 250° C., to the layers producible by this process, and to the use thereof.
    Type: Application
    Filed: February 5, 2010
    Publication date: December 29, 2011
    Applicant: EVONIK DEGUSSA GmbH
    Inventors: Arne Hoppe, Alexey Merkulov, Juergen Steiger, Duy Vu Pham, Yvonne Damaschek, Heiko Thiem
  • Publication number: 20110233536
    Abstract: A thin film transistor array panel including an oxide semiconductor layer realizing excellent stability and electrical characteristics and an easy method of manufacturing the same are provided. A thin film transistor array panel includes: a substrate; an oxide semiconductor layer disposed on the substrate and including a metal oxide selected from the group consisting of zinc oxide, tin oxide, and hafnium oxide; a gate electrode overlapping the oxide semiconductor layer; a gate insulating film disposed between the oxide semiconductor layer and the gate electrode; and a source electrode and a drain electrode disposed to at least partially overlap the oxide semiconductor layer and separated from each other.
    Type: Application
    Filed: July 20, 2010
    Publication date: September 29, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Min KIM, Yeon-Taek JEONG, Seon-Pil JANG, Seung-Hwan CHO, Bo-Sung KIM, Tae-Young CHOI
  • Patent number: 8008192
    Abstract: Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention includes forming a via in a substrate, with the via having a width and a length generally transverse to the width, and with a length being approximately 100 microns or more. The method can further include disposing a conductive material in the via while the via is exposed to a supercritical fluid. For example, copper can be disposed in the via by introducing a copper-containing precursor into the supercritical fluid and precipitating the copper from the supercritical fluid. Interconnect structures can be formed using this technique in a single generally continuous process, and can produce conductive structures having a generally uniform grain structure across the width of the via.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: August 30, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Marc Sulfridge
  • Publication number: 20110207303
    Abstract: Methods for fabricating a semiconductor device are provided. In the methods, first material layers and second material layers may be alternatingly and repeatedly stacked on a substrate. An opening penetrating the first material layers and the second material layers may be formed. A semiconductor solution may be formed in the opening by using a spin-on process.
    Type: Application
    Filed: February 18, 2011
    Publication date: August 25, 2011
    Inventors: Jin Ha Jeong, Jung Ho Kim, Kihyun Hwang, Yong-Hoon Son
  • Patent number: 7998789
    Abstract: A method and a system for forming a copper indium gallium sulfur selenide (CIGSSe) absorption layer and a cadmium sulfide (CdS) buffer layer under non-vacuum condition is disclosed. A coating layer is formed on the back electrode layer on the substrate by mixing the slurry on the back electrode layer, and the coating layer formed on the back electrode layer is densified by a densification device after initially dried, and then a primary selenization/sulfurization reaction process is carried out to form a primary CIGSSe layer, and then a thermal process is carried out to improve the lattice match of the primary CIGSSe layer, and then an impurity cleaning process is carried out by using potassium cyanide or bromide to remove the impurities of cuprous selenide and copper sulfide, and then a rear-stage selenization/sulfurization reaction process is carried out to produce the required rear-stage CIGSSe absorption layer.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: August 16, 2011
    Assignee: Jenn Feng New Energy Co., Ltd.
    Inventor: Chuan-Lung Chuang
  • Patent number: 7972960
    Abstract: A method for manufacturing a thin film includes: applying a liquid to a surface of a processing target member having at least one of a trench and a concave portion. The liquid includes a solvent and at least one of fine particles of a metal, fine particles of a semiconductor, fine particles containing a metal oxide, and fine particles containing a semiconductor oxide. A first heat treatment is included for volatilizing the solvent of the liquid applied to the surface of the processing target member. The fine particles are remained on the surface of the processing target member. A second heat treatment is also included for heating the fine particles by using microwave irradiation. At least one of the trench and the concave portion is filled with the thin film containing the fine particles or a component of the fine particles.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: July 5, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kyoichi Suguro, Yoshitaka Tsunashima
  • Publication number: 20110138882
    Abstract: Provided are a structure and operating method of a semiconductor gas sensor having low power consumption. The semiconductor gas sensor is adapted to adsorb gas to a low-dimensional semiconductor nanomaterial at room temperature, output a change in resistance of the low-dimensional semiconductor nanomaterial, apply power to a heater, desorb the gas adsorbed to the low-dimensional semiconductor nanomaterial, and return the resistance of the low-dimensional semiconductor nanomaterial back to initial resistance. The semiconductor gas sensor senses the gas at room temperature using the low-dimensional semiconductor nanomaterial having a high-sensitivity characteristic at room temperature, and drives the heater only when the adsorbed gas is desorbed. Thereby, it is possible to improve a gas sensing characteristic, reduce power consumption, and provide a rapid response speed.
    Type: Application
    Filed: December 10, 2010
    Publication date: June 16, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Seung Eon Moon, Jong Hyurk Park, Jae Woo Lee, Hong Yeol Lee, Kang Ho Park, Jong Dae Kim
  • Patent number: 7947524
    Abstract: A method for processing a thin film photovoltaic module. The method includes providing a plurality of substrates, each of the substrates having a first electrode layer and an overlying absorber layer composed of copper indium gallium selenide (CIGS) or copper indium selenide (CIS) material. The absorber material comprises a plurality of sodium bearing species. The method maintains the plurality of substrates in a controlled environment after formation of at least the absorber layer through one or more processes up to a lamination process. The controlled environment has a relative humidity of less than 10% and a temperature ranging from about 10 Degrees Celsius to about 40 Degrees Celsius. The method subjects the plurality of substrates to a liquid comprising water at a temperature from about 10 Degrees Celsius to about 80 Degrees Celsius to process the plurality of substrates after formation of the absorber layer.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: May 24, 2011
    Assignee: Stion Corporation
    Inventor: Robert D. Wieting
  • Patent number: 7939393
    Abstract: Different performance MOSFET Fully Depleted devices can be achieved on a single chip by varying the Vt through ion implantation. The integration of multiple Vt can be achieved through the selection of a metal gate stack with suitable effective WF for one semiconductor device to be included on a chip. Then, an ion implantation, with a dopant such as F, can be selectively performed to achieve proper Vt for other semiconductor devices on the chip.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: May 10, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Weize Xiong, Cloves Rinn Cleavelin
  • Patent number: 7851336
    Abstract: A method for forming a passivated densified nanoparticle thin film on a substrate in a chamber is disclosed. The method includes depositing a nanoparticle ink on a first region on the substrate, the nanoparticle ink including a set of Group IV semiconductor particles and a solvent. The method also includes heating the nanoparticle ink to a first temperature between about 30° C. and about 400° C., and for a first time period between about 1 minute and about 60 minutes, wherein the solvent is substantially removed, and a porous compact is formed. The method further includes flowing an oxidizer gas into the chamber; and heating the porous compact to a second temperature between about 600° C. and about 1000° C., and for a second time period of between about 5 seconds and about 1 hour; wherein the passivated densified nanoparticle thin film is formed.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: December 14, 2010
    Assignee: Innovalight, Inc.
    Inventors: Dmitry Poplavskyy, Maxim Kelman, Mason Terry
  • Patent number: 7851803
    Abstract: A semiconductor device includes a substrate and a channel region which is formed above the substrate by printing, wherein a relationship L?2a is satisfied where L is a channel length of the channel region and a is a minimum dimension among pattern dimensions and inter-pattern dimensions in the same layer as patterns that define the channel length L; and a relationship W?2b is satisfied where W is a channel width of the channel region and b is a minimum dimension among pattern dimensions and inter-pattern dimensions in the same layer as a pattern that defines the channel width W.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: December 14, 2010
    Assignee: FUJIFILM Corporation
    Inventors: Atsushi Tanaka, Ken-Ichi Umeda, Kohei Higashi, Maki Nangu
  • Publication number: 20100237272
    Abstract: A method is disclosed for making semiconductor films from a eutectic alloy comprising a metal and a semiconductor. Through heterogeneous nucleation said film is deposited at a deposition temperature on relatively inexpensive buffered substrates, such as glass. Specifically said film is vapor deposited at a fixed temperature in said deposition temperature where said deposition temperature is above a eutectic temperature of said eutectic alloy and below a temperature at which the substrate softens. Such films could have widespread application in photovoltaic and display technologies.
    Type: Application
    Filed: May 5, 2010
    Publication date: September 23, 2010
    Inventors: Praveen Chaudhari, Karin Chaudhari, Ashok Chaudhari, Pia Chaudhari
  • Patent number: 7799597
    Abstract: A thin film transistor includes: a gate electrode; source and drain electrodes insulated from the gate electrode; an organic semiconductor layer that is insulated from the gate electrode and electrically connected to the source and drain electrodes; an insulating layer that insulates the gate electrode from the source and drain electrodes or the organic semiconductor layer; a hydrophobic layer which covers the source and drain electrodes or insulating layer and has an opening that defines a region corresponding to the organic semiconductor layer; and a hydrophilic layer formed in the opening of the hydrophobic layer, wherein the organic semiconductor layer is formed on the hydrophilic layer. The thin film transistor includes the organic semiconductor layer having a highly precise pattern that is formed without an additional patterning process.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: September 21, 2010
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Taek Ahn, Min-Chul Suh, Jin-Seong Park
  • Patent number: 7795125
    Abstract: The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally includes separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into a electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: September 14, 2010
    Assignee: Nanosys, Inc.
    Inventors: Mihai A. Buretea, Jian Chen, Calvin Y. H. Chow, Chunming Niu, Yaoling Pan, J. Wallace Parce, Linda T. Romano, David P. Stumbo
  • Patent number: 7795134
    Abstract: Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention includes forming a via in a substrate, with the via having a width and a length generally transverse to the width, and with a length being approximately 100 microns or more. The method can further include disposing a conductive material in the via while the via is exposed to a supercritical fluid. For example, copper can be disposed in the via by introducing a copper-containing precursor into the supercritical fluid and precipitating the copper from the supercritical fluid. Interconnect structures can be formed using this technique in a single generally continuous process, and can produce conductive structures having a generally uniform grain structure across the width of the via.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: September 14, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Marc Sulfridge
  • Publication number: 20100120236
    Abstract: The present invention provides a single-electron device composed of a necklace of about 5000 nanoparticles. The linear necklace is self-assembled by interfacial phenomena along a triple-phase line of fiber, a substrate and electrolyte containing nanoparticles. A variety of combinations of nanoparticles, such as Au and CdS nanoparticles, may be used to form a necklace. The I-V measurements on the system show both coulomb blockade and staircase, with high currents and high threshold voltage of 1-3 V. The present invention also provides methods for constructing such a device.
    Type: Application
    Filed: July 24, 2006
    Publication date: May 13, 2010
    Applicant: University of Nebraska at Lincoln
    Inventors: Ravi F. Saraf, Sanjun Niu, Vikas Berry, Vivek Maheshwari
  • Patent number: RE42283
    Abstract: A TFT liquid crystal display device is disclosed, which includes two substrates and a liquid crystal layer provided in between the substrates, one substrate having a surface providing with a plurality of data signal lines, a plurality of scan lines, a plurality of pixel electrodes, and a plurality of functional components having source electrode, gate electrodes and drain electrodes. Moreover, the projection of one of the signal electrode and the drain electrode on the gate electrode having at least one bridging zone and one conducting zone. The width of the bridging zone in the direction in parallel to one side of the gate electrode is smaller than the width of the conducting zone in the direction in parallel to the side of the gate electrode.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: April 12, 2011
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Hung-Jen Chu, Ming-Hsuan Chang, Chien-Kuo Ho, Nai-Jen Hsiao