Using Mask (epo) Patents (Class 257/E21.474)
  • Patent number: 8980732
    Abstract: The present invention provides a method for manufacturing a silicon carbide Schottky barrier diode. In the method, an n? epitaxial layer is deposited on an n+ substrate. A sacrificial oxide film is formed on the n? epitaxial layer by heat treatment, and then a portion where a composite oxide film is to be formed is exposed by etching. Nitrogen is implanted into the n? epitaxial layer and the sacrificial oxide film using nitrogen plasma. A silicon nitride is deposited on the n? epitaxial layer and the sacrificial oxide film. The silicon nitride is thermally oxidized to form a composite oxide film. An oxide film in a portion where a Schottky metal is to be deposited is etched, and then the Schottky metal is deposited, thereby forming a silicon carbide Schottky barrier diode.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: March 17, 2015
    Assignee: Hyundai Motor Company
    Inventors: Kyoung Kook Hong, Jong Seok Lee
  • Publication number: 20130137251
    Abstract: A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the first material is different from the second material. A third material is formed on treated first surface of the first material and on treated second surface of the second material. The first, the second, and the third materials may include a hard mask, a semiconductor material, and an oxide, respectively.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ling Liou, Chih-Tang Peng, Pei-Ren Jeng, Hao-Ming Lien, Tze-Liang Lee
  • Patent number: 8399347
    Abstract: Integrated circuits and methods for forming conductive lines and conductive pads of integrated circuits are disclosed. One such integrated circuit includes circuitry, a first conductor coupled to the circuitry, a conductive pad coupled to the first conductor, and a second conductor spaced apart from the first conductor and coupled to the conductive pad. The second conductor would be floating but for its coupling to the conductive pad.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: March 19, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Roger W Lindsay
  • Publication number: 20120244690
    Abstract: According to certain embodiments, a resist is placed over the surface of a semiconductor structure, wherein the resist covers a portion of the semiconductor structure. Dopants are implanted into the semiconductor structure using an ion implantation beam in regions of the semiconductor structure not covered by the resist. Due to exposure to the ion implantation beam, at least a portion of the resist is converted by exposure to the ion beam to contain an inorganic carbonized material. The semiconductor structure with resist is contacted with a superacid composition containing a superacid species to remove the resist containing inorganic carbonized materials from the semiconductor structure.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 27, 2012
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Yoshihiro Uozumi
  • Publication number: 20120043661
    Abstract: Integrated circuits and methods for forming conductive lines and conductive pads of integrated circuits are disclosed. One such integrated circuit includes circuitry, a first conductor coupled to the circuitry, a conductive pad coupled to the first conductor, and a second conductor spaced apart from the first conductor and coupled to the conductive pad. The second conductor would be floating but for its coupling to the conductive pad.
    Type: Application
    Filed: August 23, 2010
    Publication date: February 23, 2012
    Inventor: Roger W. Lindsay
  • Patent number: 7883973
    Abstract: A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate. A first dopant is implanted into the first unprotected region through the first opening in the dielectric layer, and into the protected region through the dielectric layer.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: February 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Seetharaman Sridar, Marie Denison, Sameer Pendharkar
  • Patent number: 7858458
    Abstract: A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: December 28, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Suraj Mathew
  • Publication number: 20100297782
    Abstract: Herein, an improved technique for processing a substrate is disclosed. In one particular exemplary embodiment, the technique may be realized with a system for processing one or more substrates. The system may comprise an ion source for generating ions of desired species, the ions generated from the ion source being directed toward the one or more substrates along an ion beam path; a substrate support for supporting the one or more substrates; a mask disposed between the ion source and the substrate support, the mask comprising a finger defining one or more apertures through which a portion of the ions traveling along the ion beam path pass; and a first detector for detecting ions, the first detector being fixedly positioned relative to the one or more substrates.
    Type: Application
    Filed: May 20, 2010
    Publication date: November 25, 2010
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Benjamin B. Riordon, Kevin M. Daniels, William T. Weaver, Steven M. Anella
  • Patent number: 7799630
    Abstract: A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer exposing one of the conductive type transistor, performing a first etching process to remove a portion of a gate of the conductive type transistor, reforming a metal gate, removing the patterned blocking layer, performing a second etching process to remove a portion of a gate of the other conductive type transistor, and reforming a metal gate.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: September 21, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Hao Yu, Li-Wei Cheng, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ting Lin, Che-Hua Hsu, Guang-Hwa Ma
  • Publication number: 20100197124
    Abstract: A semiconductor integrated circuit device with enhanced reliability is provided. The semiconductor integrated circuit device includes a semiconductor substrate; a gate insulation film that is provided on the semiconductor substrate; a gate electrode that is provided on the gate insulation film; and a sidewall spacer that is provided on side walls of the gate insulation film and the gate electrode and includes, wherein the sidewall spacer has a first sidewall spacer in contact with the gate electrode and a second sidewall spacer formed on the side walls of the first sidewall spacer, and a ratio of an Si—OH area to an Si—O area in at least one of the first and second sidewall spacers is 0.05 or less, as measured by Fourier Transform InfraRed (FTIR).
    Type: Application
    Filed: February 2, 2009
    Publication date: August 5, 2010
    Inventors: Yong-kuk Jeong, Dong-hee Yu, Jong-ho Yang, Seong-dong Kim
  • Publication number: 20100148271
    Abstract: The present invention relates to a method for gate leakage reduction and Vt shift control, in which a first ion implantation is performed on PMOS region and NMOS region of a substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate, and a second ion implantation is performed only on the NMOS region of the substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate in the NMOS region, with the PMOS region being covered by a mask layer. Thus, the doping concentrations obtained by the PMOS region and the NMOS region are different to compensate the side effect caused by the different equivalent oxide thickness and to avoid the Vt shift.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 17, 2010
    Inventors: Chien-Liang Lin, Yu-Ren Wang, Wu-Chun Kao, Ying-Hsuan Li, Ying-Wei Yen, Shu-Yen Chan
  • Patent number: 7682915
    Abstract: The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second gate on a substrate. Next, an oxide layer is formed on the first and second gates; and, a nitride layer is formed on the oxide layer. Portions of the nitride layer proximate the first gate, portions of the oxide layer proximate the first gate, and portions of the substrate proximate the first gate are removed so as to form source and drain recesses proximate the first gate. Following this, the method removes remaining portions of the nitride layer, including exposing remaining portions of the oxide layer. The removal of the remaining portions of the nitride layer only exposes the remaining portions of the oxide layer and the source and drain recesses.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Huajie Chen, Judson R. Holt, Kern Rim, Dominic J. Schepis
  • Patent number: 7659187
    Abstract: A method of forming transistors on a wafer includes forming gates over gate insulators on a surface of the wafer and ion implanting dopant impurity atoms into the wafer to form source and drain regions aligned on opposite sides of each gate. The wafer is then annealed by pre-heating the bulk of the wafer to an elevated temperature over 350 degrees C. but below a temperature at which the dopant atoms tend to cluster. Meanwhile, an intense line beam is produced having a narrow dimension along a fast axis from an array of coherent CW lasers of a selected wavelength. This line beam is scanned across the surface of the heated wafer along the direction of the fast axis, so as to heat, up to a peak surface temperature near a melting temperature of the wafer, a moving localized region on the surface of the wafer having (a) a width corresponding to the narrow beam width and (b) an extremely shallow below-surface depth.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: February 9, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Philip Allan Kraus, Vijay Parihar
  • Publication number: 20090325355
    Abstract: In extremely scaled semiconductor devices, an asymmetric transistor configuration may be established on the basis of tilted implantation processes with increased resist height and/or tilt angles during tilted implantation processes by providing an asymmetric mask arrangement for masked transistor elements. For this purpose, the implantation mask may be shifted by an appropriate amount so as to enhance the overall blocking effect for the masked transistors while reducing any shadowing effect of the implantation masks for the non-masked transistors. The shift of the implantation masks may be accomplished by performing the automatic alignment procedure on the basis of “shifted” target values or by providing asymmetrically arranged photolithography masks.
    Type: Application
    Filed: April 3, 2009
    Publication date: December 31, 2009
    Inventors: Andre Poock, Jan Hoentschel
  • Publication number: 20090325356
    Abstract: Provided are methods of forming a low temperature deposition layer and methods of manufacturing a semiconductor device using the same. The method of manufacturing a semiconductor device comprises forming a mask layer exposing a gate pattern on a substrate on which the gate pattern is formed, forming a sacrifice layer on the mask layer and on a substrate not covered by the mask layer using a plasma ion immersion implantation and deposition (PIIID), and doping a substrate adjacent to both sidewalls of the gate pattern with an impurity.
    Type: Application
    Filed: April 29, 2009
    Publication date: December 31, 2009
    Inventors: Dong-Woon SHIN, Si-Young Choi, Tai-Su Park, Jong-Ryeol Yoo, Jong-Hoon Kang
  • Publication number: 20090186471
    Abstract: A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.
    Type: Application
    Filed: January 20, 2009
    Publication date: July 23, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Ho Jung, Makoto Yoshida, Jae-Rok Kahng, Chul Lee, Joon-Seok Moon, Cheol-Kyu Lee, Sung-Il Cho
  • Publication number: 20090181506
    Abstract: An embedded memory device and method of forming MOS transistors having reduced masking requirements and defects using a single drain sided halo implant in the NMOS FLASH or EEPROM memory regions is discussed. The memory device comprises a memory region and a logic region. Logic transistors within the logic region have halos implanted at an angle underlying the channel from both drain and source region sides. Asymmetric memory cell transistors within the memory region receive a selective halo implant only from the drain side of the channel and not from the source side to form a larger halo on the drain side and leave a higher dopant concentration more deeply into the source side.
    Type: Application
    Filed: March 19, 2009
    Publication date: July 16, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Jihong Chen, Eddie Hearl Breashears, Xin Wang, John Howard Macpeak
  • Publication number: 20090170271
    Abstract: According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.
    Type: Application
    Filed: March 3, 2009
    Publication date: July 2, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Man YOON, Choong-Ho LEE, Dong-Gun PARK, Chul LEE
  • Publication number: 20090166777
    Abstract: Embodiments relate to an image sensor and a method of manufacturing an image sensor. According to embodiments, an image sensor may include a gate over a semiconductor substrate, a first impurity region over the semiconductor substrate, a second impurity region over the semiconductor substrate, the second impurity region being shallower than the first impurity region, and a third impurity region formed in the first impurity region, and bent toward the gate at a predetermined angle. According to embodiments, the third impurity region may be an n-type impurity region. According to embodiments, an area of a photodiode may be increased and a transfer efficiency of electrons generated from a photodiode may be increased.
    Type: Application
    Filed: December 27, 2008
    Publication date: July 2, 2009
    Inventor: Joung-Ho Lee
  • Publication number: 20090081858
    Abstract: Methods of implanting dopants into a silicon substrate using a predeposited sacrificial material layer with a defined thickness that is removed by sputtering effect is provided.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 26, 2009
    Inventors: Shu Qin, Li Li
  • Publication number: 20090042377
    Abstract: Methods include utilizing a single mask layer to form tightly spaced, adjacent first-type and second-type well regions. The mask layer is formed over a substrate in a region in which the second-type well regions will be formed. The first-type well regions are formed in the exposed portions of the substrate. Then, the second-type well-regions are formed through the resist mask.
    Type: Application
    Filed: August 8, 2007
    Publication date: February 12, 2009
    Inventor: Seetharaman Sridhar
  • Publication number: 20080286954
    Abstract: A method of forming a pattern of a semiconductor device comprises forming a first hard mask film, a first resist film, and a second hard mask film over an underlying layer of a semiconductor substrate; forming a second resist pattern over the second hard mask film; etching the second hard mask film using the second resist pattern as an etching mask to form a second hard mask pattern; performing an ion-implanting process on the first resist film with the second hard mask pattern as an ion implanting mask to form an ion implanting layer in a portion of the first resist film, and selectively etching the first resist film with the second hard mask pattern and an ion implanting layer as an etching mask to form a first resist pattern.
    Type: Application
    Filed: November 29, 2007
    Publication date: November 20, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Seo Min Kim, Chang Moon Lim
  • Patent number: 7439163
    Abstract: Methods for fabricating fluid injection devices. A patterned sacrificial layer is formed on a substrate. A patterned first structural layer is formed on the substrate covering the sacrificial layer. At least one fluid actuator is formed on the structural layer. A first passivation layer is formed on the first structural covering the at least one fluid actuator. An under bump metal (UBM) layer is conformably formed on the first passivation layer. A patterned first photoresist is formed at a predetermined nozzle site and a contact opening site exposes the UBM layer. A second structural layer is formed on the UBM layer. An etching protective layer is formed on the second structural layer. The first photoresist is removed creating an opening at the nozzle site exposing the UBM layer. The UBM layer in the opening is removed.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: October 21, 2008
    Assignees: Qisda Corporation, Benq Corporation
    Inventors: Hung-Sheng Hu, Wei-Lin Chen, Tsung-Ping Hsu, Der-Rong Shyn
  • Publication number: 20080166862
    Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 10, 2008
    Inventors: Gayle W. Miller, Bryan D. Sendelweck
  • Publication number: 20080160729
    Abstract: Resist masks exposed to high-dose implantation processes may be efficiently removed on the basis of a combination of a plasma-based etch process and a wet chemical etch recipe, wherein both etch steps may include a highly selective etch chemistry in order to minimize substrate material loss and thus dopant loss in sophisticated semiconductor devices. The first plasma-based etch step may provide under-etched areas of the resist mask, which may then be efficiently removed on the basis of the wet chemical etch process.
    Type: Application
    Filed: July 25, 2007
    Publication date: July 3, 2008
    Inventors: Christian Krueger, Volker Grimm, Lutz Eckart
  • Publication number: 20080108209
    Abstract: A method of forming transistors on a wafer includes forming gates over gate insulators on a surface of the wafer and ion implanting dopant impurity atoms into the wafer to form source and drain regions aligned on opposite sides of each gate. The wafer is then annealed by pre-heating the bulk of the wafer to an elevated temperature over 350 degrees C. but below a temperature at which the dopant atoms tend to cluster. Meanwhile, an intense line beam is produced having a narrow dimension along a fast axis from an array of coherent CW lasers of a selected wavelength. This line beam is scanned across the surface of the heated wafer along the direction of the fast axis, so as to heat, up to a peak surface temperature near a melting temperature of the wafer, a moving localized region on the surface of the wafer having (a) a width corresponding to the narrow beam width and (b) an extremely shallow below-surface depth.
    Type: Application
    Filed: April 16, 2007
    Publication date: May 8, 2008
    Inventors: PHILIP ALLAN KRAUS, Vijay Parihar
  • Publication number: 20080042229
    Abstract: An image sensor is provided incorporating a first conductive type semiconductor substrate including an active area defined by a device isolation layer; a second conductive type first ion implant area formed as multiple regions in the active area; a second conductive type second ion implant area connecting the multiple regions of the second conductive type first ion implant area; and a first conductive type ion implant area formed on the second conductive type second ion implant area. The multiple regions of the second conductive type first ion implant area can be formed deeply in the substrate. The second conductive type second ion implant can be formed in the substrate at an upper region of the first ion implant area, a middle region of the first ion implant area, or a lower region of the first ion implant area.
    Type: Application
    Filed: July 25, 2007
    Publication date: February 21, 2008
    Inventor: Keun Hyuk Lim