Producing Ion Implantation (epo) Patents (Class 257/E21.473)
  • Patent number: 9035305
    Abstract: Reducing hydrogen concentration in a channel formation region of an oxide semiconductor is important in stabilizing threshold voltage of a transistor including an oxide semiconductor and improving reliability. Hence, hydrogen is attracted from the oxide semiconductor and trapped in a region of an insulating film which overlaps with a source region and a drain region of the oxide semiconductor. Impurities such as argon, nitrogen, carbon, phosphorus, or boron are added to the region of the insulating film which overlaps with the source region and the drain region of the oxide semiconductor, thereby generating a defect. Hydrogen in the oxide semiconductor is attracted to the defect in the insulating film. The defect in the insulating film is stabilized by the presence of hydrogen.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: May 19, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Yusuke Nonaka, Noritaka Ishihara, Masashi Oota, Hideyuki Kishida
  • Patent number: 8921215
    Abstract: An ion injection simulation method includes: calculating a reinjection dose injected into a substrate and a structure formed on the substrate and reinjected from a side face of the structure; and calculating concentration distribution of impurities injected into the substrate from a distribution function and reinjection conditions of the reinjection dose.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: December 30, 2014
    Assignee: Sony Corporation
    Inventor: Jun Komachi
  • Patent number: 8883620
    Abstract: A novel process for using enriched and highly enriched dopant gases is provided herein that eliminates the problems currently encountered by end-users from being able to realize the process benefits associated with ion implanting such dopant gases. For a given flow rate within a prescribed range, operating at a reduced total power level of the ion source is designed to reduce the ionization efficiency of the enriched dopant gas compared to that of its corresponding non-enriched or lesser enriched dopant gas. The temperature of the source filament is also reduced, thereby mitigating the adverse effects of fluorine etching and ion source shorting when a fluorine-containing enriched dopant gas is utilized. The reduced levels of total power in combination with a lower ionization efficiency and lower ion source temperature can interact synergistically to improve and extend ion source life, while beneficially maintaining a beam current that does not unacceptably deviate from previously qualified levels.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: November 11, 2014
    Assignee: Praxair Technology, Inc.
    Inventors: Ashwini K. Sinha, Ching I Li
  • Patent number: 8878301
    Abstract: A semiconductor device includes core transistors for forming a logic circuit, and I/O transistors for forming an input/output circuit. A distance from the main surface to a lowermost part of an n-type impurity region NR of the I/O n-type transistor is longer than that from the main surface to a lowermost part of an n-type impurity region NR of the core n-type transistor. A distance from the main surface to a lowermost part of a p-type impurity region PR of the I/O p-type transistor is longer than that from the main surface to a lowermost part of a p-type impurity region of the core p-type transistor. A distance from the main surface to the lowermost part of the n-type impurity region of the I/O n-type transistor is longer than that from the main surface to the lowermost part of the p-type impurity region of the I/O p-type transistor.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: November 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Yuichi Hirano
  • Patent number: 8860023
    Abstract: Reducing hydrogen concentration in a channel formation region of an oxide semiconductor is important in stabilizing threshold voltage of a transistor including an oxide semiconductor and improving reliability. Hence, hydrogen is attracted from the oxide semiconductor and trapped in a region of an insulating film which overlaps with a source region and a drain region of the oxide semiconductor. Impurities such as argon, nitrogen, carbon, phosphorus, or boron are added to the region of the insulating film which overlaps with the source region and the drain region of the oxide semiconductor, thereby generating a defect. Hydrogen in the oxide semiconductor is attracted to the defect in the insulating film. The defect in the insulating film is stabilized by the presence of hydrogen.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Yusuke Nonaka, Noritaka Ishihara, Masashi Oota, Hideyuki Kishida
  • Patent number: 8828794
    Abstract: In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed. The transistor formed using the oxide semiconductor film can have high reliability because the amount of change in the threshold voltage of the transistor by a bias-temperature stress test (BT test) is reduced.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuhei Sato, Keiji Sato, Tetsunori Maruyama, Junichi Koezuka
  • Patent number: 8742505
    Abstract: One or more embodiments relate to an apparatus comprising: a first transistor including a channel in a fin; and a second transistor including a channel in a fin, the channel of the first transistor being doped with a first dopant of a first polarity and counter-doped with a second dopant of a second polarity opposite to the first polarity, a concentration of the first dopant being approximately equal to a concentration of the second dopant, wherein the first transistor and the second transistor are of a same conductivity type.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: June 3, 2014
    Assignee: Infineon Technologies AG
    Inventors: Joerg Berthold, Christian Pacha, Klaus von Arnim
  • Publication number: 20140117502
    Abstract: A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Johannes Laven, Hans-Joachim Schulze
  • Patent number: 8697555
    Abstract: The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 3 made of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece 61, which is a generating source other than the wafer 3.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: April 15, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Shin Harada, Yasuo Namikawa, Takeyoshi Masuda
  • Publication number: 20140084351
    Abstract: A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lien HUANG, Ming-Huan TSAI, Clement Hsingjen WANN
  • Publication number: 20140077274
    Abstract: Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure including a first region and a second region and a structure surface formed by the first region and the second region. The first region is formed by a first material and the second region is formed by a second material. In the method, the structure surface is exposed to a gas cluster ion beam (GCIB) and an irradiated layer is formed in the structure in both the first region and the second region. The irradiated layer is etched to form a recess.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 8669608
    Abstract: According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: March 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuru Sato, Megumi Ishiduki, Masaru Kidoh, Atsushi Konno, Yoshihiro Akutsu, Masaru Kito, Yoshiaki Fukuzumi, Ryota Katsumata
  • Publication number: 20140055024
    Abstract: An ion source includes a chamber defining an interior cavity for ionization, an electron beam source at a first end of the interior cavity, an inlet for introducing ionizable gas into the chamber, and an arc slit for extracting ions from the chamber. The chamber includes an electrically conductive ceramic.
    Type: Application
    Filed: August 22, 2012
    Publication date: February 27, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Frank Goerbing
  • Publication number: 20140035619
    Abstract: According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode.
    Type: Application
    Filed: September 18, 2012
    Publication date: February 6, 2014
    Inventors: Koichiro Zaitsu, Kosuke Tatsumura, Mari Matsumoto
  • Patent number: 8598022
    Abstract: An isotopically-enriched, boron-containing compound comprising two or more boron atoms and at least one fluorine atom, wherein at least one of the boron atoms contains a desired isotope of boron in a concentration or ratio greater than a natural abundance concentration or ratio thereof. The compound may have a chemical formula of B2F4. Synthesis methods for such compounds, and ion implantation methods using such compounds, are described, as well as storage and dispensing vessels in which the isotopically-enriched, boron-containing compound is advantageously contained for subsequent dispensing use.
    Type: Grant
    Filed: November 19, 2011
    Date of Patent: December 3, 2013
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Robert Kaim, Joseph D. Sweeney, Oleg Byl, Sharad N. Yedave, Edward E. Jones, Peng Zou, Ying Tang, Barry Lewis Chambers, Richard S. Ray
  • Publication number: 20130307150
    Abstract: A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 21, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Edelstein, Takeshi Nogami, Christopher Parks, Tsong-Lin Tai
  • Patent number: 8581329
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Megumi Ishiduki, Ryota Katsumata, Tomo Ohsawa, Mitsuru Sato, Masaru Kidoh, Hiroyasu Tanaka
  • Publication number: 20130288468
    Abstract: One illustrative method disclosed herein involves forming an etch stop layer above a plurality of sacrificial gate structures, performing an angled ion implant process to implant an etch-inhibiting species into less than an entirety of the etch stop layer, and forming a layer of insulating material above the etch stop layer. The method further includes removing the sacrificial gate structures, forming replacement gate structures, forming a hard mask layer above the replacement gate structures and layer of insulating material, forming a patterned hard mask layer, performing another etching process through the patterned hard mask layer to define an opening in the layer of insulating material to expose a portion of the etch stop layer, performing another etching process on the exposed portion to define a contact opening therethrough that exposes a doped region and forming a conductive contact in the opening that is conductively coupled to the doped region.
    Type: Application
    Filed: April 25, 2012
    Publication date: October 31, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: Min-Hwa Chi
  • Patent number: 8563408
    Abstract: A spin-on formulation that is useful in stripping an ion implanted photoresist is provided that includes an aqueous solution of a water soluble polymer containing at least one acidic functional group, and at least one lanthanide metal-containing oxidant. The spin-on formulation is applied to an ion implanted photoresist and baked to form a modified photoresist. The modified photoresist is soluble in aqueous, acid or organic solvents. As such one of the aforementioned solvents can be used to completely strip the ion implanted photoresist as well as any photoresist residue that may be present. A rinse step can follow the stripping of the modified photoresist.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Mahmoud Khojasteh, Ronald W. Nunes, George G. Totir
  • Publication number: 20130183817
    Abstract: Disclosed herein are various methods of reducing gate leakage in semiconductor devices such as transistors. In one example, a method disclosed herein includes performing an etching process to define a gate insulation layer of a transistor, wherein the gate insulation layer has an etched edge, performing an angled ion implantation process to implant ions into the gate insulation layer proximate the etched edge of the gate insulation layer and, after performing the angled ion implantation process, performing an anneal process.
    Type: Application
    Filed: January 16, 2012
    Publication date: July 18, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ricardo P. Mikalo, Stefan Flachowsky
  • Publication number: 20130183816
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device is provided. In the method of manufacturing a semiconductor device, a first layer containing Si is formed on a semiconductor substrate. An impurity region and a non-impurity region are formed in the first layer by selectively diffusing an impurity into the first layer. A second layer containing a metal material is formed on the first layer. The metal material is diffused into the non-impurity region by annealing the second layer.
    Type: Application
    Filed: September 14, 2012
    Publication date: July 18, 2013
    Inventor: Shuichi TANIGUCHI
  • Publication number: 20130171810
    Abstract: Methods of fabricating a semiconductor device, and related devices, include forming a gate electrode on a substrate, forming a first buffer layer, a second buffer layer and a third buffer layer on side surfaces of the gate electrode and on the substrate near the gate electrode, forming a spacer covering the side surfaces of the gate electrode on the third buffer layer, the third buffer layer on the substrate being exposed, exposing the second buffer layer on the substrate by removing the exposed third buffer layer, exposing the first buffer layer on the substrate by removing the exposed second buffer layer, forming deep junction in the substrate using the spacer as a mask, and removing the spacer. The third buffer layer is a material layer having a higher dielectric constant than the second buffer layer. The spacer includes a material layer different than the third, second and first buffer layers.
    Type: Application
    Filed: July 6, 2012
    Publication date: July 4, 2013
    Applicants: SNU R&DB FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Chul Sun, Byung-Gook Park
  • Publication number: 20130161767
    Abstract: A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern.
    Type: Application
    Filed: September 13, 2012
    Publication date: June 27, 2013
    Applicant: SK HYNIX INC.
    Inventors: Kyong Bong ROUH, Yong Seok EUN, Young Jin SON
  • Publication number: 20130161725
    Abstract: A semiconductor memory device includes conductive films and insulating layers alternately stacked on a substrate, substantially vertical channel layers penetrating the conductive films and the insulating layers, multilayer films including a charge storage film interposed between the conductive films and the substantially vertical channel layers, and a first anti-diffusion film formed on etched surfaces of the conductive films.
    Type: Application
    Filed: September 13, 2012
    Publication date: June 27, 2013
    Applicant: SK HYNIX INC.
    Inventors: Yong Dae PARK, Ga Hee LEE
  • Publication number: 20130149848
    Abstract: The present invention belongs to the technical field of semiconductors and specifically relates to a method for manufacturing a vertical-channel tunneling transistor. In the present invention, the surrounding gate gate structure improves the control capacity of the gate and the source of narrow band gap material can enhance the device driving current. The method for manufacturing a vertical-channel tunneling transistor put forward by the present invention capable of controlling the channel length precisely features simple process, easy control and reduction of production cost.
    Type: Application
    Filed: June 29, 2012
    Publication date: June 13, 2013
    Applicant: FUDAN UNIVERSITY
    Inventors: PENGFEI WANG, XI LIN, WEI LIU, QINGQING SUN, WEI ZHANG
  • Publication number: 20130140567
    Abstract: Crack formation and propagation in a silicon substrate may be reduced by forming a crack reducing portion. The silicon substrate includes a silicon main portion and a silicon edge portion formed around the silicon main portion. The crack reducing portion is formed on the silicon edge portion of the silicon substrate such that the directions of crystal faces in the crack reducing portion are randomly oriented.
    Type: Application
    Filed: September 13, 2012
    Publication date: June 6, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-youn KIM, Jae-Kyun KIM, Su-hee CHAE, Hyun-gi HONG
  • Patent number: 8441068
    Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an active region formed to be sloped or tilted by ?° (where 0°<?°<90°) from the bottom of a semiconductor substrate, at least one gate that is formed over the sloped active region and has a surface parallel to the bottom of the semiconductor substrate, and a landing plug that is coupled to the active region and is located between the gates. As a result, the area of the active region is increased thus increasing a channel width, so that the operation of the semiconductor device can be improved as the integration degree of the semiconductor device is rapidly increased.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: May 14, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Wan Kim
  • Publication number: 20130084685
    Abstract: Methods for ion implantation. A method comprises forming a layer of non-crosslinking mask material over a semiconductor region; forming a patterned photoresist layer over the non-crosslinking mask layer; removing the photoresist layer and the non-crosslinking mask layer from the exposed regions, while the masked regions remain covered; and implanting dopant ions into the exposed regions, the dopant ions being blocked from the masked regions. The non-crosslinking mask layer and any remaining photoresist material may be removed. In additional embodiments, the non-crosslinking material comprises carbon. In another embodiment, the non-crosslinking material comprises an oxide. Ion implantations for source and drain, lightly doped drain, and well regions are performed.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Buh-Kuan Fang
  • Publication number: 20130075805
    Abstract: According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.
    Type: Application
    Filed: March 14, 2012
    Publication date: March 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mitsuru SATO, Megumi ISHIDUKI, Masaru KIDOH, Atsushi KONNO, Yoshihiro AKUTSU, Masaru KITO, Yoshiaki FUKUZUMI, Ryota KATSUMATA
  • Publication number: 20130062688
    Abstract: According to an embodiment, a semiconductor device includes a semiconductor layer, a first semiconductor region provided on the semiconductor layer, a second semiconductor region, a first control electrode and a second control electrode. The first control electrode faces the first and second semiconductor regions through an insulating film in a trench, the trench piercing through the first semiconductor region, the trench having a bottom face at a position deeper than the first semiconductor region. The second control electrode extends to the bottom face of the trench and has a portion between the bottom face and the first control electrode. The semiconductor layer includes a first portion between an end of the first semiconductor region and an end of the second control electrode, a first conductive type carrier concentration in the first portion being lower than a first conductive type carrier concentration in other portions in the semiconductor layer.
    Type: Application
    Filed: March 14, 2012
    Publication date: March 14, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hitoshi KOBAYASHI
  • Publication number: 20130052813
    Abstract: Provided is a method and structure for utilizing advance channel substrate materials in semiconductor manufacturing. Advanced channel substrate materials such as germanium and Group III-V channel substrate materials, are advantageously utilized. One or more capping films including at least a nitride layer are formed over the channel substrate prior to patterning, ion implantation and the subsequent stripping and wet cleaning operations. With the capping layers intact during these operations, attack of the channel substrate material is prevented and the protective films are easily removed subsequently. The films are dimensioned in conjunction with the ion implantation operation to enable the desired dopant profile and concentration to be formed in the channel substrate material.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hsi YEH, Chun-Yi LEE, Chi-Ming YANG, Chin-Hsiang LIN
  • Publication number: 20130049098
    Abstract: In one embodiment, a nonvolatile semiconductor memory device includes a substrate, and a plurality of cell transistors, each of which includes a first insulating layer, a charge storage layer, a second insulating layer, and a control electrode successively provided on the substrate, side surfaces of the charge storage layer including inclined surfaces. The device further includes at least one insulator including a first insulator part provided on side surfaces of the cell transistors and on a top surface of the semiconductor substrate between the cell transistors, and a second insulator part continuously provided on an air gap between the cell transistors and on the cell transistors. A first distance from the top surface of the semiconductor substrate between the cell transistors to a bottom end of the air gap is greater than a thickness of the at least one insulator provided on the side surfaces of the cell transistors.
    Type: Application
    Filed: March 6, 2012
    Publication date: February 28, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo IZUMI, Tohru Ozaki
  • Publication number: 20130045589
    Abstract: A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 21, 2013
    Inventors: Seokhoon Kim, Sangsu Kim, Chung Geun Koh, Byeongchan Lee, Sunghil Lee, Jinyeong Joe
  • Publication number: 20130043563
    Abstract: According to one embodiment, there is provided a method of manufacturing a semiconductor device. In the method, a substrate portion and a fin portion on the substrate portion are formed. A first silicon oxide film is formed on each side surface of the fin portion. A polysilazane film having an upper surface lower than the upper surface of the first silicon oxide film is formed on each side surface of the first silicon oxide film. The polysilazane film is converted into a silicon oxynitride film. The first silicon oxide film is etched to make the upper surface of the first silicon oxide film not higher than the upper surface of the silicon oxynitride film. A heavily doped semiconductor layer is formed in the fin portion.
    Type: Application
    Filed: March 19, 2012
    Publication date: February 21, 2013
    Inventor: Keisuke NAKAZAWA
  • Publication number: 20130026607
    Abstract: A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material.
    Type: Application
    Filed: July 25, 2011
    Publication date: January 31, 2013
    Applicant: SYNOPSYS, INC.
    Inventors: Victor Moroz, Lars Bomholt
  • Publication number: 20130009149
    Abstract: An object of an embodiment of the present invention is to provide a semiconductor device which includes a transistor including an oxide semiconductor with high field-effect mobility, a small variation in threshold voltage, and high reliability. The semiconductor device includes a transistor which includes an insulating substrate from which oxygen is released by heat treatment and an oxide semiconductor film over the insulating substrate. A channel is formed in the oxide semiconductor film. The insulating substrate from which oxygen is released by heat treatment can be manufactured by implanting oxygen ions into at least a region of an insulating substrate on the side provided with the oxide semiconductor film.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 10, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuta ENDO, Junichi KOEZUKA, Yuichi SATO
  • Publication number: 20130005126
    Abstract: Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.
    Type: Application
    Filed: September 10, 2012
    Publication date: January 3, 2013
    Applicant: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Dae-Gyu Park, Haizhou Yin
  • Publication number: 20120326277
    Abstract: A power semiconductor device and a manufacturing method thereof are provided. The method of manufacturing a power semiconductor device includes the steps: (a) forming a cell structure on a first conductivity type semiconductor substrate; (b) implanting second conductivity type ions onto the rear surface of the first conductivity type semiconductor substrate and activating to form an electrode region; and (c) implanting ions creating first conductivity type with a doping concentration higher than that of the semiconductor substrate and activating to form a high-concentration ion implanted region at a position below the cell structure and on the electrode region. Accordingly, it is possible to form a field stop layer regardless of conditions for forming an electrode region (for example, a P-type collector region) and thus to optimize stable breakdown voltage characteristics and device characteristics.
    Type: Application
    Filed: April 20, 2012
    Publication date: December 27, 2012
    Inventors: Seung-Chul LEE, Eun-Taek KIM
  • Publication number: 20120329226
    Abstract: There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory cells having a memory element and a JFET access device electrically coupled to the memory element. The memory cells may be isolated using diffusion based isolation.
    Type: Application
    Filed: September 5, 2012
    Publication date: December 27, 2012
    Applicant: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Publication number: 20120282729
    Abstract: A method for manufacturing a semiconductor apparatus includes the first step of forming a silicon oxide film including a main portion on a second portion and a sub portion between a first portion and a silicon nitride film, the second step of forming a first conductivity type impurity region under the silicon oxide film, and the third step of forming a semiconductor element including a second conductivity type impurity region having an opposite conductivity to the first conductivity type impurity region in the first portion. In the second step, angled ion implantation is performed into a region under the sub portion at an implantation angle using the silicon nitride film as a mask.
    Type: Application
    Filed: April 25, 2012
    Publication date: November 8, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Yasuhiro Kawabata
  • Publication number: 20120276723
    Abstract: An ion injection simulation method includes: calculating a reinjection dose injected into a substrate and a structure formed on the substrate and reinjected from a side face of the structure; and calculating concentration distribution of impurities injected into the substrate from a distribution function and reinjection conditions of the reinjection dose.
    Type: Application
    Filed: March 9, 2012
    Publication date: November 1, 2012
    Applicant: SONY CORPORATION
    Inventor: Jun Komachi
  • Publication number: 20120248576
    Abstract: An undoped semiconductor substrate is doped by applying stress at a side of the undoped semiconductor substrate to release self interstitials in the substrate and implanting chalcogen atoms into the side of the substrate. The substrate is annealed to form a first semiconductor region containing the chalcogen atoms and a second semiconductor region devoid of the chalcogen atoms. The first semiconductor region has a doping concentration higher than the doping concentration of the second semiconductor region. The indiffusion of chalcogen atoms into a semiconductor material in the presence of self interstitials can also be used to form field stop regions in power semiconductor devices.
    Type: Application
    Filed: March 30, 2011
    Publication date: October 4, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gerhard Schmidt, Hans-Joachim Schulze, Bernd Kolbesen
  • Publication number: 20120235221
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body.
    Type: Application
    Filed: September 20, 2011
    Publication date: September 20, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Megumi ISHIDUKI, Ryota Katsumata, Tomo Ohsawa, Mitsuru Sato, Masaru Kidoh, Hiroyasu Tanaka
  • Publication number: 20120225529
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
    Type: Application
    Filed: May 7, 2012
    Publication date: September 6, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
  • Publication number: 20120219921
    Abstract: The present invention provides a temperature control method for a substrate heat treatment apparatus that achieves high throughput while securing stability in rapid heating where a large-diameter silicon carbide (SiC) substrate having impurity ions implanted thereinto is subjected to an activation annealing treatment. A temperature control method for a substrate heat treatment apparatus (1) that includes a heating element includes: increasing the treatment temperature; continuing the temperature increase by reducing the value of power in a stepwise manner after the treatment temperature reaches a preset temperature (T1) before reaching the annealing temperature, the power being applied to heat the heating element; and maintaining the treatment temperature at a fixed value until an annealing treatment is completed after the treatment temperature reaches the annealing temperature (TA).
    Type: Application
    Filed: December 21, 2010
    Publication date: August 30, 2012
    Applicant: CANON ANELVA CORPORATION
    Inventors: Masami Shibagaki, Kaori Mashimo
  • Patent number: 8252673
    Abstract: A spin-on formulation that is useful in stripping an ion implanted photoresist is provided that includes an aqueous solution of a water soluble polymer containing at least one acidic functional group, and at least one lanthanide metal-containing oxidant. The spin-on formulation is applied to an ion implanted photoresist and baked to form a modified photoresist. The modified photoresist is soluble in aqueous, acid or organic solvents. As such one of the aforementioned solvents can be used to completely strip the ion implanted photoresist as well as any photoresist residue that may be present. A rinse step can follow the stripping of the modified photoresist.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: August 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Mahmoud Khojasteh, Ronald W. Nunes, George G. Totir
  • Publication number: 20120202340
    Abstract: ZnTe is implanted with a first species selected from Group III and a second species selected from Group VII. This may be performed using sequential implants, implants of the first species and second species that are at least partially simultaneous, or a molecular species comprising an atom selected from Group III and an atom selected from Group VII. The implants may be performed at an elevated temperature in one instance between 70° C. and 800° C.
    Type: Application
    Filed: February 4, 2011
    Publication date: August 9, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Xianfeng LU, Ludovic GODET, Anthony RENAU
  • Publication number: 20120202341
    Abstract: ZnTe is implanted with a first species selected from Group III and a second species selected from Group VII. This may be preformed using sequential implants, implants of the first species and second species that are at least partially simultaneous, or a molecular species comprising an atom selected from Group III and an atom selected from Group VII. The implants may be performed at an elevated temperature in one instance between 70° C. and 800° C.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 9, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Xiangfeng LU, Ludovic GODET, Anthony RENAU
  • Publication number: 20120190181
    Abstract: Methods and carbon ion precursor compositions for implanting carbon ions generally includes vaporizing and ionizing a gas mixture including carbon oxide and methane gases in an ion source to create a plasma and produce carbon ions. The ionized carbon within the plasma is then extracted to form an ion beam. The ion beam is mass analyzed with a mass analyzer magnet to permit the ionized carbon to pass therethrough and implant into a workpiece.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 26, 2012
    Applicant: AXCELIS TECHNOLOGIES, INC.
    Inventors: WILLIAM D. LEE, DANIEL R. TIEGER, TSEH-JEN HSIEH
  • Publication number: 20120161125
    Abstract: A semiconductor device capable of high speed operation is provided. Further, a highly reliable semiconductor device is provided. An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed in the semiconductor layer. The source region and the drain region are formed in such a manner that one or more of elements selected from rare gases and hydrogen are added to the semiconductor layer by an ion doping method or an ion implantation method with the use of a channel protective layer as a mask.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 28, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei YAMAZAKI