Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

Abstract: A method for fabricating an image sensor is provided. In the image sensor fabrication method, an interconnection and a dielectric interlayer are formed on a semiconductor substrate including a readout circuit. An image sensing unit is formed on a carrier substrate of one side of a dielectric layer. The carrier substrate and the dielectric interlayer are bonded to each other. The dielectric layer and the carrier substrate are removed to leave the image sensing unit on the dielectric interlayer.

Abstract: Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.

Abstract: The invention provides a aqueous slurry useful for chemical mechanical polishing a semiconductor substrate having copper interconnects. The slurry comprises by weight percent, 0 to 25 oxidizing agent, 0.1 to 50 abrasive particles, 0.001 to 10 inhibitor for decreasing static etch of the copper interconnects, 0.001 to 5 poly(methyl vinyl ether) having a formula as follows: and the poly(methyl vinyl ether) is water soluble and n has a value of at least 5, 0.005 to 1 aminobutyric acid, 0.01 to 5 phosphorus-containing compound, 0 to 10 copper complexing agent formed during polishing and balance water.

Abstract: A chemical mechanical polishing method includes employing a topologically selective slurry or an abrasive trapped or abrasive mounted pad in an initial polishing operation to provide a substantially planar topology of a polysilicon layer of a semiconductor wafer, and performing a second polishing operation to remove a portion of the polysilicon layer to expose discrete elements of the semiconductor wafer.

Abstract: A semiconductor structure is fabricated with a void such as a line, contact, via or zia. To prevent slurry particles from falling into and remaining in a void during a chemical-mechanical planarization process, a protective coat is provided in the void to trap the slurry particles and limit an extent to which they can enter the void. A metal layer is provided above the protective coat. Subsequently, the protective coat and trapped slurry particles are removed by cleaning, leaving a void which is substantially free of slurry particles. This is beneficial such as when the void is used as an alignment mark. The protective coat can be an organic layer such as spin-on carbon or i-line photoresist, an ashable material such as amorphous carbon, or a dissolvable and selective material such as SiN.

Abstract: According to one embodiment, a manufacturing method includes performing lithography processes for manufacturing a semiconductor device that includes a three-dimensional stacked device. The stacked device includes layers stacked above a substrate. Each of the layers includes a device circuit. The lithography processes include a lithography process for forming a lower layer of the layers by using a first original plate that has quality not less than a certain level. The first original plate is selected from original plates. Each of the original plates includes a pattern corresponding to the device circuit. The original plates are ranked according to quality based on defect. The lithography processes further include a lithography process for forming a higher layer of the layers by using a second original plate that has quality lower than the certain level. The second original plate is selected from the original plates.

Abstract: A composition for polishing surfaces comprises the following components: a) at least one inorganic abrasive component (S) comprising a lanthanide oxide, b) at least one organic dispersing-agent component based on polymer (P), c) at least one organic gelling agent (G) such as gellan gum, d) water as solution or dispersing medium, and e) if appropriate further auxiliary and additive materials and has high stability.

Abstract: A slurry composition for a chemical mechanical processing process includes about 0.05 to about 0.3 percent by weight of a ceria abrasive, about 0.005 to about 0.04 percent by weight of an anionic surfactant, about 0.0005 to about 0.003 percent by weight of a polyoxyethylene-based nonionic surfactant, about 0.2 to about 1.0 percent by weight of a salt of polyacrylic acid having an average molecular weight substantially greater than a molecular weight of the anionic surfactant, and a remainder of water. In addition, a method of polishing an object layer and a method of manufacturing a semiconductor device using the slurry composition are also provided.

Abstract: To provide a polishing composition which has a high removal rate and enables to suppress occurrence of dishing and erosion, in polishing of a surface to be polished in the production of a semiconductor integrated circuit device. A chemical mechanical polishing composition for polishing a surface to be polished of a semiconductor integrated circuit device comprises (A) fine oxide particles, (B) pullulan, and (C) water. The polishing composition further contains (D) an oxidizing agent, and (E) a compound represented by the formula 1: wherein R is a hydrogen atom, a C1-4 alkyl group, a C1-4 alkoxy group or a carboxylic acid group.

Abstract: A CMP composition containing a rheology agent, e.g., in combination with oxidizing agent, chelating agent, inhibiting agent, abrasive and solvent. Such CMP composition advantageously increases the materials selectivity in the CMP process and is useful for polishing surfaces of copper elements on semiconductor substrates, without the occurrence of dishing or other adverse planarization deficiencies in the polished copper.

Abstract: A semiconductor device fabricating method may include forming an insulating layer on a semiconductor substrate; forming a through hole with a first depth in the insulating layer and the semiconductor substrate; forming a metal layer thereon, thereby forming a through electrode in the through hole; and exposing the through electrode by polishing the bottom surface of the semiconductor substrate.

Abstract: The invention provides a metal polishing slurry containing a compound represented by the general formula (1): (X1)n-L wherein X1 represents a heterocycle containing at least one nitrogen atom, n represents an integer of 2 or more, and L represents a linking group having a valence of 2 or more, provided that X1s whose number is n may be the same or different, an oxidizer and an organic acid; and a method of chemical mechanical polishing using such slurry. The metal polishing slurry and the chemical mechanical polishing method are used in chemical mechanical polishing in the step of manufacturing semiconductor devices and enable a high polishing rate to be achieved while causing minimal dishing in polishing an object (wafer).

Abstract: A method of machining a wafer is disclosed, in which the wafer is held by sucking its back-side surface directly onto a suction surface of a chuck table, and the tips of protruding electrodes and a resist layer are cut to make them flush with each other (appendant part cutting step). Next, the wafer is held by sucking the surface of the cut appendant part directly onto the suction surface of the chuck table, and the back-side surface of the wafer is ground (back-side surface grinding step), followed by removing the resist layer. The wafer is held onto the chuck table without using any protective tape but by directly holding the wafer, whereby the wafer can be ground to have a uniform thickness.

Abstract: A method of manufacturing a semiconductor wafer, including a step of differentiating the glossiness of a front surface from that of a rear surface of the wafer by holding the semiconductor wafer in a wafer holding hole formed in a carrier plate, and simultaneously polishing a front and back surface of said semiconductor wafer by driving said carrier plate to make a circular motion associated with no rotation on its own axis within a plane parallel with a surface of said carrier plate between a pair of polishing members disposed to face to each other, by using an abrasive body with a semiconductor wafer sink rate different in polishing from that of an abrasive body for one of a polishing member on an upper surface plate and a polishing member on a lower surface plate so as to simultaneously polish both the front and rear surfaces of the semiconductor wafer, or differentiating by differentiating the rotating speed of the upper surface plate from that of the lower surface plate.

Abstract: A polishing slurry used in chemical mechanical polishing of a barrier layer and an interlayer dielectric film in a semiconductor integrated circuit includes an abrasive, an oxidizer, an anticorrosive, an acid, a surfactant and an inclusion compound. The polishing slurry has a pH of less than 5. The resulting polishing slurry contains a solid abrasive used in barrier CMP for polishing a barrier layer made of a metallic barrier material, has excellent storage stability, achieves a good polishing rate in various films to be polished such as the barrier layer, and is capable of independently controlling the polishing rate with respect to the various films to be polished while further suppressing agglomeration of the abrasive particles.

Abstract: The present invention relates to a novel slurry composition for copper polishing, comprising zeolite which is a porous crystalline material for CMP of copper film in a semiconductor manufacturing process. The slurry composition according to the present invention comprises zeolite, an oxidant and a polish promoting agent and may further comprise a corrosion inhibitor, a surfactant, an aminoalcohol, an antiseptic and a dispersion agent and pH is in a range of 1 to 7. The zeolite slurry according to the present invention has advantages of absorbing and removing metal cation generated in CMP process by using zeolite and having a low level of scratches as the zeolite has micropores therein and thus its hardness is low. The slurry composition using zeolite of the present invention is usable to both first and second step polishing of copper damascene process and particularly useful as the first step polishing slurry for copper.

Abstract: Chamfer correction is performed to a chamfered portion at least on a front side of a silicon wafer after an incoming inspection. Thereby, a thickness of the chamfered portion on the front side of the wafer is restored, and thus the number of reclamation cycles of the silicon wafer can be increased. In addition, the chamfered portion is not deformed even after reclamation is repeated for a plurality of times.

Abstract: Microelectronic dies are thinned according to a variety of approaches, which may include bonding the dies to a substrate under vacuum, disposing a film over the dies and the substrate, and/or changing a center of pressure during thinning.

Abstract: Disclosed herein is a method for manufacturing a semiconductor device that includes: etching a semiconductor substrate to form a recess region; forming a device isolation trench in a portion of the etched semiconductor substrate including a portion of the recess region; and forming a device isolation film in the device isolation trench. The recess region is formed before the device isolation film, which can prevent a gate subsequently formed over the device isolation film from leaning. As a result, a subsequent landing plug contact hole is opened, which can improve process defects.

Abstract: A thin, planar semiconductor device having electrodes on both surfaces is disclosed. This semiconductor device is provided with an IC chip and a wiring layer having one side that is electrically connected to surface electrodes of the IC chip. On this surface of the wiring layer, conductive posts are provided on wiring of the wiring layer, and an insulating resin covers all portions not occupied by the IC chip and conductive posts. The end surfaces of the conductive posts are exposed from the insulating resin and are used as first planar electrodes. In addition, a resist layer is formed on the opposite surface of the wiring layer. Exposed portions are formed in the resist layer to expose desired wiring portions of the wiring layer. These exposed portions are used as second planar electrodes. Stacking semiconductor devices of this construction enables an improvement in the integration of semiconductor integrated circuits.

Abstract: A method for transferring a thin layer from an initial substrate includes forming an assembly of the initial substrate with one face of a silicone type polymer layer, this face having been treated under an ultraviolet radiation, and processing the initial substrate to form the thin layer on the silicone type polymer layer.

Abstract: In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will stop on the dielectric etch stop layer, limiting overetch. In a second embodiment, a plurality of conductive features is formed in a subtractive pattern and etch process, filled with a dielectric fill, and then a surface formed coexposing the conductive features and dielectric fill. A dielectric etch stop layer is deposited on the surface, then a third dielectric covers the dielectric etch stop layer. When a contact is etched through the third dielectric, this selective etch stops on the dielectric etch stop layer. A second etch makes contact to the conductive features.

Abstract: In one embodiment, a method includes providing two structures with a spacing therebetween over a semiconductor substrate, providing a conformal first layer over the two structures and within the space therebetween, depositing a conformal protective layer over the first layer, planarizing the protective layer until a top surface of the first layer is exposed, and planarizing the first layer and the protective layer until a top surface of the two structures is exposed and a portion of the protective layer is between the two structures.

Abstract: A photoelectric device grinding process comprising the following steps is disclosed. A wafer comprising a plurality of chip units is provided. Each chip unit has at least a photoelectric device disposed on a surface layer. A dielectric substrate is attached to the wafer with glue having a plurality of spacers therein such that the photoelectric devices face the dielectric layer. The spacers maintain a gap between the dielectric substrate and the wafer. Thereafter, the dielectric substrate surface away from the wafer or the wafer surface away from the dielectric substrate or both is ground. The grinding process is particularly suitable for preventing any possible damage to the photoelectric devices on a wafer.

Abstract: A system and method for improved dry etching system. According to an embodiment, the present invention provides a partially completed integrated circuit device. The partially completed integrated circuit device includes a semiconductor substrate having a surface region. The partially completed integrated circuit device also includes an etch stop layer overlying the surface region. The etch stop layer is characterized by a thickness having at least a first thickness portion and a second thickness portion. The second thickness portion includes an etch stop surface region. The partially completed integrated circuit device additionally includes a silicon dioxide material provided within the first thickness portion of the etch stop layer. The partially completed integrated circuit device includes a silicon nitride material provided within the second thickness portion of the etch stop layer.

Abstract: Disclosed are a method of and system for fabricating a semiconductor wafer. The method comprises the steps of providing a silicon wafer having a front side an a back side, building an integrated circuit on the front side of the wafer, and thereafter removing substrate from the back side of the silicon wafer. The building step includes the steps of forming a desired structure in the wafer, and forming an end structure in the wafer, said end structure extending to a greater depth, toward the back side of the wafer, than the desired structure. Also, the removing step includes the step of removing said substrate only to the end structure, whereby no part of the desired structure is removed during the removing step.

Abstract: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.

Abstract: Quality of one-surface planar processed group 3 nitride wafers depends upon a direction of pasting of wafers on a polishing plate. Low surface roughness and high yield are obtained by pasting a plurality of group 3 nitride as-grown wafers on a polishing plate with OFs or notches facing forward (f), backward (b) or inward (u) with thermoplastic wax having a thickness of 10 ?m or less, grinding the as-grown wafers, lapping the ground wafers, polishing the lapped wafers into mirror wafers with a bevel of a horizontal width of 200 ?m or less and a vertical depth of 100 ?m or less.

Abstract: To improve the reliability and yield of a thin-type semiconductor device as used for a stack-type flash memory, the semiconductor device is manufactured by upheaving each of semiconductor chips (semiconductor devices) obtained by dicing a semiconductor wafer on an adhesive sheet from a backside via the adhesive sheet using an upthrow jig to which ultrasonic vibration is applied so as not to break through the adhesive sheet, and by picking up each semiconductor chip.

Abstract: An anti-warpage backgrinding tape (11) is secured to the circuit side (12) of a semiconductor wafer (14). The backside (16) of the wafer is background. The backside of the wafer is secured to dicing tape (18) so that the anti-warpage backgrinding tape is exposed. The wafer is diced to create individual die structure (34). The die structure comprises semiconductor die (22) with anti-warpage tape elements (36) on circuit sides of the semiconductor die. A die structure is removed from the dicing tape. The backside of the die of the die structure is adhered to a substrate (24). The anti-warpage tape element is removed from the die. The anti-warpage backgrinding tape is preferably partially or fully transparent to permit sensing of guide markings on the wafer during wafer dicing. The adhesive is preferably a curable adhesive. The adhesion between the anti-warpage tape element and the chosen die may be reduced by the application of heat (38).

Abstract: A method used to form a semiconductor device comprises processing a semiconductor wafer to include one or more vias or through-holes only partially etched into the wafer, and scribe marks only partially etched into the wafer which define a plurality of semiconductor devices. Wafer material is removed from the back of the wafer to the level of the vias and scribe marks to form a via opening through the wafer while simultaneously dicing the wafer into individual semiconductor dice.

Abstract: A method of manufacturing a semiconductor wafer wherein a film is formed on a back surface of a starting semiconductor wafer formed with circuits in a front surface thereof.

Abstract: Cassettes for holding thin semiconductor wafers for safe handling are provided, along with an improved methodology for reducing the thickness of semiconductor wafers. Embodiments include a cassette for holding thin semiconductor wafers, having a plurality of sets of center and edge supports, the sets being spaced from each other a distance greater than a sag amount of the wafers. The thin wafers are supported in a predetermined reference plane, so that tools such as robots or automatic handlers can be programmed to pick them up without damaging them. In another embodiment, a double into single pitch wafer cassette is provided having a wafer entrance section with spacing twice as large between sets of edge supports as a conventional cassette, to accommodate the sag/warp of the thin wafers, and a “flattening section” which guides and flattens the wafers between opposing edge supports as they are pushed into the cassette, such that the wafers are held substantially planar.