Abstract: A thin film transistor TFT, including a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer, the active layer corresponding to the gate electrode and including a channel region, source and drain electrodes contacting the active layer, the source and drain electrodes being separate from each other, and an ohmic contact layer between the active layer and at least one of the source and drain electrodes, the ohmic contact layer including an oxide semiconductor material.

Abstract: Provided are methods of depositing N-Metals onto a substrate. Some methods comprise providing an initiation layer of TaM or TiM layer on a substrate, wherein M is selected from aluminum, carbon, noble metals, gallium, silicon, germanium and combinations thereof; and exposing the substrate having the TaM or TiM layer to a treatment process comprising soaking the surface of the substrate with a reducing agent to provided a treated initiation layer.

Abstract: A thin film transistor TFT, including a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer, the active layer corresponding to the gate electrode and including a channel region, source and drain electrodes contacting the active layer, the source and drain electrodes being separate from each other, and an ohmic contact layer between the active layer and at least one of the source and drain electrodes, the ohmic contact layer including an oxide semiconductor material.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region.

Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening.

Abstract: A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film.

Abstract: A Cu interconnect is formed with improved directionality and smoothness. Embodiments include wet etching Cu while applying a pulsing electric current. An embodiment includes forming a Cu layer, and patterning the Cu layer by exposing it to a wet etching solution which includes a passivating surface active agent while simultaneously applying an electric current. The etching solution may be a mild acid. A UV light may be applied simultaneously with the electric current. The electric current may be pulsed with a cycle frequency between 50 kHz and 500 kHz.

Abstract: A method that in one embodiment is useful in bonding a first substrate to a second substrate includes forming a layer including metal over the first substrate. The layer including metal in one embodiment surrounds a semiconductor device, which can be a micro electromechanical system (MEMS) device. On the second substrate is formed a first layer comprising silicon. A second layer comprising germanium and silicon is formed on the first layer. A third layer comprising germanium is formed on the second layer. The third layer is brought into contact with the layer including metal. Heat (and pressure in some embodiments) is applied to the third layer and the layer including metal to form a mechanical bond material between the first substrate and the second substrate in which the mechanical bond material is electrically conductive. In the case of the mechanical bond surrounding a semiconductor device such as a MEMS, the mechanical bond can be particularly advantageous as a hermetic seal for protecting the MEMS.

Abstract: A method of fabricating a semiconductor device includes forming a gate dielectric layer and a first gate layer sequentially on an overall surface of a substrate including a first region and a second region, forming a lanthanum-oxide (La2O3) mask pattern on the first gate layer disposed on the second region, and selectively removing the first gate layer disposed on the first region by etching using the La2O3 mask pattern as a mask, thereby forming a first gate layer pattern on the second region.

Abstract: It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. Therefore, the invention provides a method for narrowing (miniaturizing) the line width according to a method different from a conventional method. A region to be liquid-repellent is formed and further, a region to be lyophilic is formed selectively in the region to be liquid-repellent in a surface for forming a pattern, before forming a desired pattern. After that, a pattern for a wiring or the like is formed in the lyophilic region by a dropping method typified by an ink-jetting method for dropping a composition including a conductive material for the wiring or the like.

Abstract: The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated.

Abstract: A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.

Abstract: A method for forming a semiconductor chip or wafer includes following steps. A semiconductor substrate is provided, and then a polymer layer is deposited over the semiconductor substrate, wherein the polymer layer comprises polyimide. The polymer layer with a temperature profile having a peak temperature between 200 and 320 degrees Celsius. Alternatively, the temperature profile may comprises a period of time with a temperature higher than 320 degree Celsius, wherein the period of time is shorter than 45 minutes.

Abstract: The manufacturing method includes: forming a seed film on a semiconductor chip; forming a photoresist having an opening above an electrode of the semiconductor chip on the seed film; forming a first Au bump on the seed film in the opening by electrolytic plating with a current density of 1.5 A/dm2 or above; grinding a surface of the first Au bump; stripping the photoresist; and removing the seed film by dry-etching.

Abstract: A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.

Abstract: In a method of manufacturing a NOR flash memory, when the memory device dimensions are further reduced, the forming of spacers at two lateral sides of the gate structures is omitted, and a space between two gate structures can be directly filled up with a dielectric spacer or a shallow trench isolation (STI) layer. Therefore, it is possible to avoid the problem of increased difficulty in manufacturing memory device caused by forming spacers in an extremely small space between the gate structures. The method also enables omission of the self-alignment step needed to form the salicide layer. Therefore, the difficulty in self-alignment due to the extremely small space between the gate structures can also be avoided.

Abstract: A system may include a first conductive ground pad, a second conductive ground pad, a first conductive via coupling the first ground pad to the second ground pad, a first conductive signal trace, a second conductive signal trace, and a second conductive via disposed within the first conductive via and coupling the first conductive signal trace to the second conductive signal trace. The first conductive ground pad and the second conductive ground pad may be disposed between the first conductive signal trace and the second conductive signal trace.

Abstract: A method that in one embodiment is useful in bonding a first substrate to a second substrate includes forming a layer including metal over the first substrate. The layer including metal in one embodiment surrounds a semiconductor device, which can be a micro electromechanical system (MEMS) device. On the second substrate is formed a first layer comprising silicon. A second layer comprising germanium and silicon is formed on the first layer. A third layer comprising germanium is formed on the second layer. The third layer is brought into contact with the layer including metal. Heat (and pressure in some embodiments) is applied to the third layer and the layer including metal to form a mechanical bond material between the first substrate and the second substrate in which the mechanical bond material is electrically conductive. In the case of the mechanical bond surrounding a semiconductor device such as a MEMS, the mechanical bond can be particularly advantageous as a hermetic seal for protecting the MEMS.

Abstract: Semiconductor devices and methods are disclosed for improving electrical connections to integrated circuits. A process flow and device with a dual/single damascene interconnect structure overlying an existing interconnect structure in a semiconductor wafer is provided. A capping layer is formed thereon that comprises nickel/palladium layers within a bond pad opening. The layers are polished using a chemical mechanical polishing (CMP) technique so that the capping layers are within the opening.

Abstract: Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 ? to about 50 ? and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water.

Abstract: The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first etching process to the substrate to remove a polysilicon layer and a metal gate layer on the substrate; applying a diluted hydrofluoric acid (HF) to the substrate to remove polymeric residue; thereafter applying to the substrate with a cleaning solution including hydrochloride (HCl), hydrogen peroxide (H2O2) and water (H2O); applying a wet etching process diluted hydrochloride (HCl) to the substrate to remove a capping layer; and applying to the substrate with a second etching process to remove a high k dielectric material layer.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region.

Abstract: A semiconductor device, and a method of fabricating the semiconductor device, which is able to prevent a leaning phenomenon from occurring between the adjacent storage nodes. The method includes forming a plurality of multi-layered pillar type storage nodes each of which is buried in a plurality of mold layers, wherein the uppermost layers of the multi-layered pillar type storage nodes are fixed by a support layer, etching a portion of the support layer to form an opening, and supplying an etch solution through the opening to remove the multiple mold layers. A process of depositing and etching the mold layer by performing the process 2 or more times to form the multi-layered pillar type storage node. Thus, the desired capacitance is sufficiently secured and the leaning phenomenon is avoided between adjacent storage nodes.

Abstract: A method for manufacturing a semiconductor device prevents failure of self-aligned contacts to improve the yield of the semiconductor device. A height of a device isolating film is larger than a height of an active region. A recess region of the device isolating film is planarized by a wet etching process to remove a hard mask layer when a recess gate is etched. A contact plug is then formed in the recess region between adjacent recess gates.

Abstract: A method for manufacturing a semiconductor device includes forming an insulation layer having a contact hole on a semiconductor substrate. A metal silicide layer is deposited on a surface of the contact hole and the insulation layer to have a concentration gradient that changes from a silicon-rich composition to a metal-rich composition, with the lower portion of the metal silicide layer having the silicon-rich composition and the upper portion of the metal silicide layer having the metal-rich composition. The metal silicide layer is then annealed so that the compositions of metal and silicon in the metal silicide layer become uniform.

Abstract: Embodiments of this method improve the results of a chemical mechanical polishing (CMP) process. A surface is implanted with a species, such as, for example, Si, Ge, As, B, P, H, He, Ne, Ar, Kr, Xe, and C. The implant of this species will at least affect dishing, erosion, and polishing rates of the CMP process. The species may be selected in one embodiment to either accelerate or decelerate the CMP process. The dose of the species may be varied over the surface in one particular embodiment.

Abstract: In a particular illustrative embodiment, a method of forming a magnetic tunnel junction (MTJ) device is disclosed that includes forming a trench in a substrate. The method further includes depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The method also includes planarizing the MTJ structure. In a particular example, the MTJ structure is planarized using a Chemical Mechanical Planarization (CMP) process.

Abstract: Methods, systems, and apparatuses for electrical connections through circuit boards are described. A via-in-via structure in a circuit board provides two electrical signal paths. The circuit board includes a dielectric layer having opposing first and second planar surfaces. A first opening extends through the dielectric layer. An electrically conductive coating coats a surface of the dielectric layer in the first opening. An electrically insulating material substantially fills the first opening. The circuit board includes a first additional dielectric layer attached to the first planar surface, and a second additional dielectric layer attached to the second planar surface. A second opening extends through the first additional dielectric layer, the electrically insulating material filling the first opening, and the second additional dielectric layer.

Abstract: A semiconductor device includes a first interlayer dielectric including a trench on a semiconductor layer, a mask pattern on the first interlayer dielectric, a first conductive pattern in the trench, and a second interlayer dielectric on the mask pattern. The second interlayer dielectric includes an opening over the first conductive pattern. A second conductive pattern is in the opening and is electrically connected to the first conductive pattern. The first conductive pattern has an upper surface lower than an upper surface of the mask pattern.

Abstract: The present method of fabricating a resistive memory device includes the steps of providing a first electrode, oxidizing a portion of the first electrode with an oxidizing agent, providing a metal body on the oxidized portion of the first electrode, oxidizing the entire metal body with an oxidizing agent, and providing a second electrode on the oxidized metal body.

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A method of manufacturing dual work function devices starting from a single metal electrode and the device resulting therefrom are disclosed. In one aspect, the method includes a single-metal-single-dielectric (SMSD) CMOS integration scheme. A single dielectric stack comprising a gate dielectric layer and a dielectric capping layer and one metal layer overlying the dielectric stack are first deposited, forming a metal-dielectric interface. Upon forming the dielectric stack and the metal layer, at least part of the dielectric capping layer is selectively modified by adding work function tuning elements, the part being adjacent to the metal-dielectric interface.

Abstract: A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode.

Abstract: A semiconductor substrate is inserted into a heat treatment apparatus at a low temperature ranging from room temperature to about 50° C., and organic substances included in a metal on the semiconductor substrate are released without carbonization in an annealing process before CMP. Further, organic substances capable of preventing the corrosion of the metal are decomposed, and the organic substances themselves and chlorine, sulfuric acid, and ammonia which are included in the organic substances are diffused out of the metal film by setting the heat treatment apparatus at a rate of temperature rise of 15° C./min or less until a prescribed heat treatment temperature is reached.

Abstract: A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.

Abstract: Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.

Abstract: A semiconductor device includes a first wiring layer, a second wiring layer and a third wiring layer. The first wiring layer is formed on a semiconductor substrate. The second and the third wiring layer wiring layers are arranged in a direction intersecting with the first wiring layer on respective sides of the wiring layer. An air bridge wiring intersects the second and third wiring layers sandwiching an air layer above the first wiring layer therewith. The overall shape of the air bridge wiring has an upward convex curvature in an arch shape and the transverse sectional shape of the air bridge wiring is in the form of a downward concave curvature.

Abstract: In a method for planarizing an insulation layer in a semiconductor device, an insulation layer is formed over a semiconductor substrate having a cell region and a peripheral region. The cell region is higher than the peripheral region due to a capacitor formed in the cell region. A metal layer is formed over the insulation layer. The metal layer is chemical mechanical polished to expose the insulation layer portion in the cell region. The exposed insulation layer portion in the cell region is chemical mechanical polishing to planarize the insulation layer, and the planarized insulation layer and the remaining metal layer are chemical mechanical polishing to remove the metal layer remained in the peripheral region. The method for planarizing an insulation layer does not require a separate photosensitive layer forming process or a dry etching process.

Abstract: An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.

Abstract: Provided herein are methods for using corrosion-inhibiting cleaning compositions for semiconductor wafer processing that include an aqueous admixture of at least water, a surfactant and a corrosion-inhibiting compound selected from a group consisting of amino phosphonates, polyamines and polycarboxylic acids. The quantity of the corrosion-inhibiting compound in the admixture is preferably in a range from about 0.0001 wt % to about 0.1 wt % and the quantity of the surfactant is preferably in a range from about 0.001 wt % to about 1.0 wt %. The aqueous admixture may also include sulfuric acid and a fluoride, which act as oxide etchants, and a peroxide, which acts as a metal etchant.

Abstract: A memory device with improved heat transfer characteristics. The device first includes a dielectric material layer; first and second electrodes, vertically separated and having mutually opposed contact surfaces. A phase change memory element is encased within the dielectric material layer, including a phase-change layer positioned between and in electrical contact with the electrodes, wherein the lateral extent of the phase change layer is less than the lateral extent of the electrodes. An isolation material is positioned between the phase change layer and the dielectric layer, wherein the thermal conductivity of the isolation material is lower than the thermal conductivity of the dielectric material.

Abstract: A method for patterning a semiconductor device can include forming a conductive layer over a semiconductor substrate; alternatively forming positive photoresists and negative photoresists over the conductive layer; forming a plurality of first conductive lines by selectively removing a portion of the conductive layer using the positive photoresist and the negative photoresist as masks; forming an oxide film over the semiconductor substrate including the first conductive lines and the conductive layer; performing a planarization process over the oxide film using the uppermost surface of the first conductive line as a target; removing the plurality of first conductive lines using the oxide film as a mask; forming a plurality if trenches in the semiconductor substrate and removing a portion of the oxide film to expose the uppermost surface of the conductive layer; and then forming a plurality of second conductive lines by removing the exposed conductive layer using the oxide film as a mask.

Abstract: A method for manufacturing a metal pattern of a semiconductor device capable of preventing generation of a ring defect in a metal pattern by performing a stuffing process for making increasing the density of an anti-reflection-coating using O2 gas or N2 gas.

Abstract: Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a polishing pressures of about 2 psi or less and at platen rotational speeds of about 200 cps or greater. The polishing process may use an abrasive-containing polishing composition having up to about 1 wt. % of abrasives. The polishing process may be integrated into a multi-step polishing process.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly patterned by the actinic irradiation so that it is possible to fabricate the resistive memory cell through simple processes, and avoiding ashing and stripping steps.

Abstract: An integrated circuit semiconductor device comprises a substrate, a deep via within the substrate, a metal fill located within the deep via and defining an upper surface, and an interconnect wiring. The contact area electrically connects the metal fill to the interconnect wiring, the contact area being located laterally of the deep via such that the contact area does not contact the upper surface of the metal fill.

Abstract: The semiconductor device of the present invention includes a first interconnection, a via-plug that is connected to the first interconnection, and a second interconnection that is formed as a single unit with the via-plug. The cross-sectional shape of the via-plug is such that the plug sidewall angle, which indicates the angle of the via-plug sidewall with respect to the surface of the first interconnection, is a positive angle; and moreover, at least two points exist between the base and the top of the via-plug on at least one sidewall of the two sidewalls of the cross-sectional shape of the via-plug at which the plug sidewall angle attains a maximum value. Since shapes that would give rise to the occurrence of concentrations of stress are not formed in the via-plug sidewalls, metal is more effectively embedded in the via-hole, and the incidence of voids is prevented.

Abstract: A method of forming a wiring level and an electrical isolation associated with the wiring level on a surface of a semiconductor wafer comprises the steps of providing the semiconductor wafer having said surface, forming a plurality of electrically conductive wiring lines upon said surface, each of the wiring lines having a spacing with respect to neighboring one of the wiring lines, depositing a first layer of amorphous carbon upon the wiring lines by means of non-conformal plasma enhanced chemical vapor deposition (PECVD), such that air-filled voids formed below the first layer within the spacings between neighboring wiring lines. Alternatively, OSG (organo-silicon glass) or FSG (fluorine doped silicon glass) may be deposited to yield air-filled voids within the spacings. According to an embodiment, the carbon, OSG or FSG layers are used as an IMD-layer (line-to-line isolation), added by a further layer of a dielectric material, which then serves as an ILD-layer (level-to-level isolation).