Mounting On Metallic Conductive Member (epo) Patents (Class 257/E21.51)
  • Patent number: 9986633
    Abstract: Embodiments are directed to a method of embedding a discrete component in a substrate. The method includes forming a cavity in the substrate. The method further includes inserting a discrete component into the cavity, wherein the discrete component comprises a top terminal and a bottom terminal. The method further includes positioning the discrete component within the cavity such that the top terminal is above the bottom terminal and below a front face of the substrate. The method further includes forming an intermediate conductive material within the cavity and over the top terminal. The method further includes forming a top conductive material over the intermediate conductive material such that the top conductive material is electrically coupled through the intermediate conductive material to the top terminal.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Lei Shan
  • Patent number: 8941219
    Abstract: An integrated circuit package system includes: interconnection pads; a first device mounted below the interconnection pads; a bond wire, or a solder ball connecting the first device to the interconnection pads; a lead connected to the interconnection pad or to the first device; an encapsulation having a top surface encapsulating the first device; and a recess in the top surface of the encapsulation with the interconnection pads exposed therefrom.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: January 27, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Jairus Legaspi Pisigan
  • Patent number: 8928145
    Abstract: A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Paul Stephen Andry, Cyril Cabral, Jr., Kenneth P. Rodbell, Robert L. Wisnieff
  • Patent number: 8916409
    Abstract: An electronic device includes a substrate and a plurality of particles anchored to the substrate. An electrode material is formed over the particles and configured to form peaks over the particles. One or more operational layers are fog led over the electrode material for performing a device function.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ahmed Abou-Kandil, Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Hisham S. Mohamed, Devendra K. Sadana
  • Patent number: 8872326
    Abstract: The mechanisms of forming a semiconductor device package described above provide a low-cost manufacturing process due to the relative simple process flow. By forming an interconnecting structure with a redistribution layer(s) to enable bonding of one or more dies underneath a package structure, the warpage of the overall package is greatly reduced. In addition, interconnecting structure is formed without using a molding compound, which reduces particle contamination. The reduction of warpage and particle contamination improves yield. Further, the semiconductor device package formed has low form factor with one or more dies fit underneath a space between a package structure and an interconnecting structure.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung
  • Patent number: 8866183
    Abstract: An LED module includes: a package having electrodes provided on the outer surface of opposing sidewalls, and a light-emitting element connected to the electrodes and mounted on the package; a base member having a copper metal; an insulating layer stacked on the surface of the base member and having an insulating material; and a conductive wiring pattern connected to the electrodes by soldering and formed on the surface of the insulating layer. The insulating layer has a through-hole formed by removing a part of the section where the package is positioned, and a heat dissipation unit formed by soldering between the back surface of the package and the base member, which face one another with the through-hole interposed therebetween.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: October 21, 2014
    Assignee: Panasonic Industrial Devices Sunx Co., Ltd.
    Inventors: Sachio Higuchi, Takashi Tanaka, Mitunori Mizoguti, Tsuyoshi Inui, Atsuo Fukuda
  • Patent number: 8809186
    Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 19, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
  • Patent number: 8741691
    Abstract: A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chung Yee, Chun Hui Yu
  • Publication number: 20140131842
    Abstract: An axially-mountable device includes a semiconductor chip comprising lower and upper electrical contacts. A lower die pad is electrically and mechanically connected to the lower electrical contact of the chip. An upper die pad is electrically and mechanically connected to the upper electrical contact of the chip. A first axially extending electrical lead is electrically and mechanically connected to the upper die pad and extends in a first axial direction. A second axially extending electrical lead is electrically and mechanically connected to the lower die pad and extends in a second axial direction that is opposite to the first axial direction. Packaging material encapsulates the semiconductor chip, the upper and lower die pads and a portion of the first and second axially extending leads. The first and second leads extend from the packaging material and are adapted to allow the device to be axially-mounted with another electrical component.
    Type: Application
    Filed: November 10, 2012
    Publication date: May 15, 2014
    Applicant: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Chih-Ping Peng, Hui-Ying Ding
  • Patent number: 8722436
    Abstract: A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: May 13, 2014
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chih-Kuang Yu, Hung-Yi Kuo
  • Patent number: 8720049
    Abstract: Disclosed herein is a method for fabricating a printed circuit board, including: stacking a second insulating layer including a reinforcement on an outer surface of a first insulating layer having a post via formed thereon; polishing an upper surface of the second insulating layer to expose an upper side of the post via; stacking a film member on the second insulating layer to cover the post via and compress the second insulating layer; polishing an upper surface of the film member to expose an upper side of the post via; and forming a circuit layer connected to the post via on the upper surface of the film member.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: May 13, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Tae Kyun Bae, Chang Gun Oh, Ho Sik Park
  • Patent number: 8685794
    Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: April 1, 2014
    Assignee: UTAC Thai Limited
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul, Kasemsan Kongthaworn, Vorajit Suwannaset
  • Patent number: 8673689
    Abstract: Embodiments of the present disclosure provide semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board. The substrate is formed using several techniques that minimize the amount of mask levels used to form the substrate. For example, a metal substrate is patterned to form a three dimensional pattern on the surface. A dielectric material is deposited on the three dimensional pattern. Using several patterning and polishing embodiments described herein, the metal/dielectric substrate is patterned and polished to form a substantially flush surface that is bonded to the semiconductor device. In one embodiment, the top surface of the metal/dielectric substrate is patterned to expose the underlying metal substrate and the bottom surface of the metal substrate is polished to be substantially flush with the dielectric material.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: March 18, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Shiann-Ming Liou, Huahung Kao
  • Patent number: 8652879
    Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: February 18, 2014
    Assignee: UTAC Thai Limited
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul, Kasemsan Kongthaworn, Vorajit Suwannaset
  • Patent number: 8637974
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die attach pad integrally connected to a connector portion and a lead; attaching an integrated circuit die to the die attach pad; connecting an internal interconnect to the integrated circuit die and the lead; forming an encapsulation over the integrated circuit die; removing the connector portion to separate the die attach pad and the lead; and forming an isolation cover between the die attach pad and the lead.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: January 28, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventor: Zheng Zheng
  • Patent number: 8633061
    Abstract: A package structure includes a metal sheet having perforations; a semiconductor chip having an active surface and an opposite inactive surface, wherein the active surface has electrode pads thereon, conductive bumps are disposed on the electrode pads, the semiconductor chip is combined with the metal sheet via the inactive surface thereof, a protective buffer layer is formed on the active surface to cover the conductive bumps, and the perforations are arranged around a periphery of the inactive surface of the semiconductor chip; an encapsulant formed on the metal sheet and in the perforations, for encapsulating the semiconductor chip and exposing the protective buffer layer; and a circuit fan-out layer formed on the encapsulant and the protective buffer layer and having conductive vias penetrating the protective buffer layer and electrically connecting to the conductive bumps. A method of fabricating the package structure and a package-on-package device including the package structure are also provided.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: January 21, 2014
    Assignee: Unimicron Technology Corporation
    Inventors: Tzyy-Jang Tseng, Dyi-Chung Hu, Yu-Shan Hu
  • Patent number: 8623708
    Abstract: A method of manufacture of an integrated circuit packaging system includes providing a lead-frame having an inner portion and a bottom cover directly on a bottom surface of the inner portion; forming an insulation cover directly on the lead-frame with the insulation cover having a connection opening; connecting an integrated circuit die to the lead-frame through the connection opening with the integrated circuit die over the insulation cover; forming a top encapsulation directly on the insulation cover; forming a routing layer having a conductive land directly on the bottom cover by shaping the lead-frame; and forming a bottom encapsulation directly on the conductive land with the bottom cover exposed from the bottom encapsulation.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: January 7, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8618641
    Abstract: A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier is greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: December 31, 2013
    Assignee: Siliconware Precision Industries Co., Ltd
    Inventors: Chang-Yueh Chan, Chih-Ming Huang, Chun-Yuan Li, Chih-Hsin Lai
  • Patent number: 8617933
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead overhang at an obtuse angle to a lead top side and having a lead ridge protruding from a lead non-horizontal side, the lead overhang having a lead overhang-undercut side at an acute angle to a lead overhang non-horizontal side; forming a lead conductive cap completely covering the lead overhang non-horizontal side and the lead top side; forming a package paddle adjacent the lead; mounting an integrated circuit over the package paddle; and forming an encapsulation over the integrated circuit, the package paddle, and the lead.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: December 31, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu, Dioscoro A. Merilo
  • Patent number: 8609446
    Abstract: A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: December 17, 2013
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chih-Kuang Yu, Hung-Yi Kuo
  • Patent number: 8610146
    Abstract: Provided is an LED package including a metal substrate that has one or more via holes formed therein; an insulating layer that is formed on a surface of the metal substrate including inner surfaces of the via holes; a plurality of metal patterns that are formed on the insulating layer and are electrically isolated from one another; and an LED chip that is mounted on a metal pattern among the plurality of metal patterns.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: December 17, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Hyun Shin, Seog Moon Choi, Young Ki Lee
  • Patent number: 8603864
    Abstract: A method of fabricating a semiconductor device. One embodiment provides a metal carrier. A semiconductor chip is provided. A porous layer is produced at a surface of at least one of the carrier and the semiconductor chip. The semiconductor chip is placed on the carrier. The resulting structure is heated until the semiconductor chip is attached to the carrier.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: December 10, 2013
    Assignee: Infineon Technologies AG
    Inventors: Edmund Riedl, Ivan Nikitin, Johannes Lodermeyer, Robert Bergmann, Karsten Guth
  • Patent number: 8586475
    Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: November 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
  • Publication number: 20130285220
    Abstract: A device comprises a semiconductor package including a first integrated circuit (IC) die including a plurality of through silicon vias (TSVs). The TSVs are formed of conductive material that extend through the first IC die from an outer surface on a first side of the die to an outer surface of a second side of the die. The package further includes first electrical connections contacting the first side of the first IC die, and second electrical connections contacting the second side of the first IC die. The first electrical connections are independent of the second electrical connections. Molding compound encapsulates the first IC die and the first and second electrical connections. The semiconductor package is mounted on a substrate so that the first and second sides of the IC die are oriented perpendicular to the substrate.
    Type: Application
    Filed: April 27, 2012
    Publication date: October 31, 2013
    Inventor: CHRISTOPHER W. ARGENTO
  • Patent number: 8564110
    Abstract: A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: October 22, 2013
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Yueh-Se Ho, Hamza Yilmaz, Jun Lu, Lei Shi, Liang Zhao, Ping Huang
  • Patent number: 8564124
    Abstract: A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: October 22, 2013
    Assignee: International Rectifier Corporation
    Inventors: Michael A. Briere, Chuan Cheah, Kunzhong Hu
  • Patent number: 8546160
    Abstract: A method for packaging LEDs includes steps of: forming a substrate with a rectangular frame, a plurality of first and second electrode strips received within the frame and alternately arranged along a width direction of the frame; forming a carrier layer on each pair of the first and second electrode strips, the carrier layer defining a plurality of recesses; arranging an LED die in each recess and electrically connecting the LED die with first and second electrodes; forming an encapsulation in each recess to cover the LED die; and cutting the first and second electrode strips along the width direction of the frame to obtain a plurality of separated LED packages each including the first and second electrodes, the LED die, the encapsulation and a part of the carrier layer.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: October 1, 2013
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventor: Pin-Chuan Chen
  • Publication number: 20130207255
    Abstract: A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 15, 2013
    Inventors: Alan J. Magnus, Carl E.D. Acosta, Douglas G. Mitchell, Justin E. Poarch
  • Patent number: 8492242
    Abstract: Methods of forming devices, including LED devices, are described. The devices may include fluorinated compound layers. The methods described may utilize a plasma treatment to form the fluorinated compound layers. The methods described may operate to produce an intermetallic layer that bonds two substrates such as semiconductor wafers together in a relatively efficient and inexpensive manner.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: July 23, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Owen Fay, Xiao Li, Josh Woodland, Shijian Luo, Jaspreet Gandhi, Te-Sung Wu
  • Patent number: 8492883
    Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper sloped portion; and (3) a lower sloped portion. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the central portion of the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: July 23, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Chien-Wen Chen, Hsu-Yang Lee
  • Patent number: 8481364
    Abstract: A fabrication method for integrating chip(s) onto a flexible substrate in forming a flexible micro-system. The method includes a low-temperature flip-chip and a wafer-level fabrication process. Using the low-temperature flip-chip technique, the chip is bonded metallically onto the flexible substrate. To separate the flexible substrate from the substrate, etching is used to remove the sacrificial layer underneath the flexible substrate. The instant disclosure applies standardized micro-fabrication process for integrating chip(s) onto the flexible substrate. Without using special materials or fabrication procedures, the instant disclosure offers a cost-effective fabrication method for flexible micro-systems.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: July 9, 2013
    Assignee: National Chiao Tung University
    Inventors: Tzu-Yuan Chao, Chia-Wei Liang, Yu-Ting Cheng
  • Patent number: 8460970
    Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: June 11, 2013
    Assignee: UTAC Thai Limited
    Inventor: Saravuth Sirinorakul
  • Publication number: 20130119539
    Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 16, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Hsiao, Ming-Da Cheng, Chih-Wei Lin, Chen-Shien Chen, Chih-Hua Chen, Chen-Cheng Kuo
  • Patent number: 8431477
    Abstract: A method for joining aligned discrete optical elements by which the optical elements can be joined in the aligned state. A thermal connection having long-term stability can be produced at little expense and with high positioning accuracy. Surface regions to be joined can be provided with at least one thin metallic layer by the method for joining aligned discrete optical elements. The surface regions are subsequently wetted using a liquid solder free of flux in a contactless dosed manner. The solder is applied to the surface regions to be joined via a nozzle using a pressurized gas stream.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: April 30, 2013
    Assignee: Fraunhofer-Gesellschaft zur forderung der Angewandten Forschung e.V.
    Inventors: Erik Beckert, Henrik Banse, Elke Zakel, Matthias Fettke
  • Patent number: 8426963
    Abstract: A power semiconductor package structure includes a carrier, a first power chip, a second power chip, a first conductive sheet, a second conductive sheet and a third conductive sheet. The first power chip has a first surface and a second surface opposing to the first surface. A first control electrode and a first main power electrode are disposed on the first surface, and a second main power electrode is disposed on the second surface. The second surface is disposed on the carrier, and electrically connected to the carrier through the second main power electrode. The second power chip has a third surface and a fourth surface opposing to the third surface. A third main power electrode is disposed on the third surface, and a fourth main power electrode is disposed on the fourth surface. The fourth surface is disposed on the first power chip. The first conductive sheet is electrically connected to the first main power electrode and the fourth main power electrode.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: April 23, 2013
    Assignee: Delta Electronics, Inc.
    Inventors: Jian-Hong Zeng, Shou-Yu Hong
  • Patent number: 8377797
    Abstract: A method of attaching a semiconductor component to a heat-sink where the component is first placed onto a heat-sink substrate whose attachment surface comprises a malleable-metal film, a semiconductor component is placed onto the malleable-metal film, and pressure and heat is applied for a predetermined time to the stack including substrate with malleable-metal film and semiconductor component.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: February 19, 2013
    Assignee: Science Research Laboratory, Inc.
    Inventors: Aland K. Chin, Jonah H. Jacob, Maciej Thomas Knapczyk
  • Patent number: 8372747
    Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: February 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
  • Patent number: 8368203
    Abstract: A semiconductor package includes a metal plate, a power element, a lead frame having a die pad, a resin sheet having insulation properties, a control circuit that controls the power element, and a mold resin. The power element is mounted on the die pad, and the die pad is mounted on the metal plate via the resin sheet. The resin sheet is expanded including at least a lower surface of the die pad while the lower surface of the resin sheet is smaller than an surface of the metal plate, and the control circuit is arranged in a region on the metal plate, which region is other than the region where the power element is arranged.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: February 5, 2013
    Assignee: Denso Corporation
    Inventors: Takatoshi Inokuchi, Tadatoshi Asada
  • Patent number: 8367472
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: February 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Ho Lee, Dong Ho Lee, Eun Chul Ahn, Yong Chai Kwon
  • Publication number: 20130020689
    Abstract: A Quad Flat Pack (QFP) device includes a semiconductor die attached to a flag of a lead frame. Bonding pads of the die are electrically connected to inner and outer rows of leads of the lead frame with bond wires. The die, die flag, bond wires and portions of the inner and outer leads are covered with a mold compound, which defines a package body. The outer leads are similar to the gull-wing leads of a conventional QFP device while the inner leads form contact points at a bottom surface of the package body. A cut is performed on an inner side of the inner leads to separate the inner leads from the die pad.
    Type: Application
    Filed: June 6, 2012
    Publication date: January 24, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Penglin Mei, Liwei Liu, Dehong Ye
  • Patent number: 8354303
    Abstract: A method and structure for a dual heat dissipating semiconductor device. A method includes attaching a drain region on a first side of a die, such as a power metal oxide semiconductor field effect transistor (MOSFET) to a first leadframe subassembly. A source region and a gate region on a second side of the die are attached to a second leadframe subassembly. The first leadframe subassembly is attached to a third leadframe subassembly, then the device is encapsulated or otherwise packaged. An exposed portion of the first leadframe subassembly provides an external heat sink for the drain region, and the second leadframe subassembly provides external heat sinks for the source region and the gate region, as well as output leads for the gate region. The third leadframe subassembly provides output leads for the drain region.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: January 15, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Juan Alejandro Herbsommer
  • Patent number: 8350263
    Abstract: A semiconductor package includes a wiring board, a semiconductor device mounted on the wiring board, an electrically-conductive thermal interface material provided on the semiconductor device, a test electrode in contact with a first surface of the thermal interface material to be electrically connected to the thermal interface material, and an electrically-conductive heat spreader in contact with a second surface of the thermal interface material opposite to its first surface.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: January 8, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Takuya Oda
  • Publication number: 20130001761
    Abstract: A lead carrier provides support for a semiconductor device during manufacture. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a die attach pad surrounded by a plurality of terminal pads. The pads are formed of a fusible fixing material on a lower portion. A chip is mounted upon the die attach pad and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be heated above a melting temperature of the fusible fixing material and peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronics system board.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 3, 2013
    Inventor: Philip E. Rogren
  • Publication number: 20120313233
    Abstract: A stackable semiconductor package, a stacked semiconductor package that uses the stackable semiconductor packages, and a method of fabricating the same. The semiconductor package includes a die paddle unit having a first surface and a second surface opposite to the first surface, a semiconductor die attached to the first surface of the die paddle unit, a plurality of leads each including a first external terminal unit, a second external terminal unit, and a connection lead unit that connects the first external terminal unit to the second external terminal unit, a bonding wire that connects the semiconductor die to the first external terminal unit, and a sealing member formed to expose the first external terminal unit and the second external terminal unit and to surround the semiconductor die and the bonding wire.
    Type: Application
    Filed: May 21, 2012
    Publication date: December 13, 2012
    Inventor: Kyung Teck Boo
  • Patent number: 8304293
    Abstract: Disclosed are systems and methods for improving the thermal performance of integrated circuit packages. Aspects of the present invention include improved thermal package structures and methods for producing the same through the application of one or more thermal spreaders in the package. In embodiments, a thermal spreader is incorporated in a semiconductor chip package between a semiconductor die and its die pad. By including a thermal spreader in an IC package, the package can handle higher levels of power while maintaining approximately the same temperature of the package or can reduce the temperature of the package when operating at the same power level, as compared to a package without a thermal spreader.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: November 6, 2012
    Assignee: Maxim Integrated, Inc.
    Inventors: Tarak A. Railkar, Steven D. Cate
  • Publication number: 20120270369
    Abstract: Methods for forming lead free solder interconnections for integrated circuits. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of material is formed on the input/output terminal of the integrated circuit. A lead free solder connector is formed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. An intermetallic compound is formed at the interface between the cap layer and the lead free solder connector. A solder connection is formed between input/output terminal of the integrated circuit and the metal finish pad that is less than 0.5 weight percent copper, and the intermetallic compound is substantially free of copper.
    Type: Application
    Filed: July 2, 2012
    Publication date: October 25, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yao-Chun Chuang, Ching-Wen Hsiao, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 8278143
    Abstract: A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting at least one of the first metallic bond part and the second metallic bond part.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Yoichiro Kurita
  • Publication number: 20120235289
    Abstract: A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.
    Type: Application
    Filed: May 24, 2012
    Publication date: September 20, 2012
    Inventors: Yan Xun Xue, Yueh-Se Ho, Hamza Yilmaz, Jun Lu, Lei Shi, Liang Zhao, Ping Huang
  • Patent number: 8268716
    Abstract: A method of coupling an integrated circuit to a substrate includes providing the substrate, forming a contact pad in the substrate, contacting the contact pad with a solder ball, and repeatedly exposing the solder ball to a thermal process to cause intermetallics based on a metal in the contact pad to be formed in the thermal ball.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Valerie Oberson, Srinivasa N. Reddy, Krystyna W. Semkow, Richard A. Shelleman, Kamalesh K. Srivistava
  • Patent number: 8247271
    Abstract: A structure fabrication method. First, an integrated circuit including N chip electric pads is provided electrically connected to a plurality of devices on the integrated circuit. Then, an interposing shield having a top side and a bottom side and having N electric conductors in the interposing shield is provided being exposed to a surrounding ambient at the top side but not at the bottom side. Next, the integrated circuit is bonded to the top side of the interposing shield such that the N chip electric pads are in electrical contact with the N electric conductors. Next, the bottom side of the interposing shield is polished so as to expose the N electric conductors to the surrounding ambient at the bottom side of the interposing shield. Then, N solder bumps are formed on the polished bottom side of the interposing shield and in electrical contact with the N electric conductors.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Paul Stephen Andry, Cyril Cabral, Jr., Kenneth P. Rodbell, Robert L. Wisnieff