Abstract: A resetable over-current self-protecting semiconductor power device comprises a vertical power semiconductor chip and an over-current protection layer composed of current limiting material such as a PTC material. The over-current protection layer may be sandwiched between the vertical power semiconductor chip and a conductive plate, which could be a leadframe, a metal plate, a PCB plate or a PCB that the device is mounted on.

Abstract: A leadframe for a semiconductor package is disclosed including electrical leads which extend from one side of the leadframe to an opposite side of the leadframe, where electrical connection may be made with the semiconductor die at the second side of the leadframe. The semiconductor die may be supported on the leads extending across the leadframe. The package may further include a spacer layer affixed to the electrical leads to fortify the semiconductor package and to prevent exposure of the electrical leads during the molding of the package.

Abstract: The present invention provides a structure of memory card comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and a through hole structure formed there through, traces formed within the substrate; a first die disposed within the die receiving cavity; a first dielectric layer formed on the first die and the substrate; a first re-distribution layer (RDL) formed on the first dielectric layer, wherein the first RDL is coupled to the first die and the traces; a second dielectric layer formed over the first RDL; a second die disposed on the second dielectric layer; a third dielectric layer formed over the second dielectric layer and the second die; a second RDL formed on the third dielectric layer, wherein the second RDL is coupled to the second die and the first RDL; a forth dielectric layer formed over the second RDL; a third die formed over the forth dielectric layer and coupled to the second RDL; a fifth dielectric layer formed around the third die; and a plastic c

Abstract: A semiconductor package includes: a semiconductor chip and a plurality of frames. A plurality of electrodes are formed on a surface of the semiconductor chip. The plurality of frames are connected to the plurality of electrodes. The plurality of frames are formed by dividing one conductive plate by etching.

Abstract: The objective of the invention is to present a mounting method by which mounting at higher densities and finer pitches can be handled so as to mount extremely small conductive balls. The mounting method of the present invention may be used to prepare porous base member 210 and mask set 220 with a 2-layer structure to be placed on base member 210, on which multiple through-holes 222a and 224a are created; vacuum adsorption is applied to base member 210 so as to form an adsorption surface on the surface of base member 210 that is exposed by through-holes 222a and 224a; microballs 260 are dropped into through-holes 222a and 224a of mask set 220; and microballs 260 are adsorbed by base member 210. Then, adsorbed microballs 260 are pressed against multiple terminal regions 108 that are formed on one surface of substrate 100 in order to transfer them there.

Abstract: A direct gold/silicon eutectic die bonding method is disclosed. The method includes the steps of gold plating a die bonding pad, grinding a wafer to a desired thickness, dicing the wafer after the grinding step, picking a die, and attaching the die to the die bonding pad at a temperature above the gold/silicon eutectic temperature. For thinner wafers, a dicing before grinding process is employed.

Abstract: A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of the segments has a first end (104a) near the mount pad and a second end (104b) remote from the mount pad. The device further has a semiconductor chip (103) attached to the mount pad and electrical interconnections (107) between the chip and the first segment ends. Encapsulation material (120) covers the chip, the bonding wires and the first segment ends, yet leaves the second segment ends exposed. At least portions of the second segment ends have the base metal covered by a layer of solderable metal (130, e.g., nickel) and by an outermost layer of noble metal (140, e.g., stack of palladium and gold).

Abstract: In a method for manufacturing an acceleration sensor device, a lid for covering an opening of a package body is prepared by stamping. The lid is plated and plating films are formed on surfaces of the lid. The burrs formed on the surfaces of the lid in the plating process are removed by chemical polishing. A semiconductor sensor chip is inserted in the package body through the opening and fixed. Then, the lid 70 is attached to the package body.

Abstract: A leadframe comprising a downset formed adjacent to an edge of the leadframe so as to direct the molding compound to flow evenly inside the mold cavity. The downset has an upward slope extending from the edge of the frame and levels off with the rest of the frame at a first transition point. The upward slope facilitates the upward flow of the molding compound entering from a bottom gate. Likewise, the leadframe also directs flow in a top gated mold by reversing the orientation of the leadframe or by forming a reverse downset on the leadframe.

Abstract: An embedded heat spreader includes a semiconductor die, an elastomer layer attached to the die, a tape lead attached to the elastomer, a portion of the tape lead exposed through the elastomer to connect with the die, a polymer resin attached to the tape lead, and a thermally conductive substrate attached to the polymer resin such that the thermally conductive substrate can spread heat from the semiconductor die.

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract: A method of fabricating a micro-array IC package is recited. A wafer has a B-stageable adhesive applied, and the wafer is diced. The individual dice are applied to a lead-frame via their adhesive, and wirebonded to associated leads. The lead-frame is then encapsulated, and solder connectors are applied. The lead-frame is then singulated to produce a plurality of lead-frame based micro-array packages. The process thus allows lead-frame based manufacturing methods to be employed in the production of BGA-type packages, allowing such packages to be produced faster and more efficiently.

Abstract: A method for manufacturing an adhesive substrate with a die-cavity sidewall is disclosed. A region for forming die-cavity sidewall is defined on one surface of the substrate. The substrate is laminated with a sacrificial film, a partially cured resin is formed between the substrate and the sacrificial film. And then, an aperture is routed through the substrate, the partially cured resin, and the sacrificial film. The aperture is located corresponding to the region so that the substrate has a die-cavity sidewall formed inside the aperture. Thereafter, the sacrificial film is removed to expose the partially cured resin on the substrate so that the substrate with a die-cavity sidewall can have good adhesion.

Abstract: A process for manufacturing a plurality of leadless semiconductor packages includes an electrically testing step to test encapsulated chips in a matrix of a leadless leadframe. Firstly, a leadless leadframe having at least a packaging matrix is provided. The packaging matrix defines a plurality of units and a plurality of cutting streets between the units. The leadless leadframe has a plurality of leads in the units and a plurality of connecting bars connecting the leads along the cutting streets. A plated metal layer is formed on the upper surfaces of the leads and the upper surfaces of the connecting bars. After die-attaching, wire-bonding connection, and encapsulation, the leadless leadframe is etched to remove the connecting bars, then two sawing steps are performed. During the first sawing step, the plated metal layer on the upper surface of the connecting bars is cut out to electrically isolate the leads.

Abstract: A thermally conductive substrate includes a thermally conductive resin sheet member attached to a lead frame. The lead frame comprises a thermally conductive resin sheet member and it is integrated with the thermally conductive resin sheet member on the lead frame. The thermally conductive resin sheet member is formed from a thermosetting resin mixture which comprises 70 to 90 parts by weight of an inorganic filler and 5 to 30 parts by weight of a thermosetting resin composition including a thermosetting resin, and the thermosetting resin is in a semi-cured state.

Abstract: A circuit assembly has a heat sink assembly and a chip scale package assembly. The chip scale package assembly has an integrated circuit die coupled to a first printed wiring board. The heat sink assembly has an integrated circuit die coupled to a second printed wiring board. Preferably, the heat sink assembly and the chip scale package assembly are assembled separately then assembled together. The circuit pads on the first printed wiring board correspond with circuit pads on the second printed wiring board. The circuit pads may be coupled together by solder or adhesive bonding. The circuit pads on the first printed wiring board may have solder balls formed of high temperature solder that do not melt when the heat sink assembly is assembled with chip scale package assembly. The solder balls allow chip scale package assembly to maintain a predetermined distance from the circuit pads on the second printed wiring board.