Abstract: In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.

Abstract: A method for manufacturing a MOS device. The method includes providing a semiconductor substrate. The method forms a gate dielectric layer overlying the semiconductor substrate and a polysilicon gate overlying the gate dielectric layer. The polysilicon gate is characterized by a thickness, a width and a polysilicon footing profile. In a specific embodiment, the method performs a TCAD simulation and determines a response of device performance due to the polysilicon footing profile from the model. The method uses the model to provide a process control window for fabricating the polysilicon gate.

Abstract: A method of detecting heavy metal in a semiconductor substrate, includes: a gate oxide film forming step of forming an organic oxide film by spin coating or a sol-gel process, and forming a metal/oxide film/semiconductor junction element by using a mercury probe method; and a step of detecting and quantifying heavy metal by calculating the surface concentration of the heavy metal from junction capacitance characteristics of the element.

Abstract: As the thickness of the card holder for preventing warping of a multilayered wiring substrate 1 is increased, there occurs a problem that a thin film sheet 2 is buried in a card holder and secure contact between probes 7 and test pads cannot be realized. For its prevention, the thin film sheet 2 and a bonding ring 6 are bonded in a state where a tensile force is applied only to the central region IA of the thin film sheet 2, and a tensile force is not applied to an outer peripheral region OA. Then, the height of the bonding ring 6 defining the height up to the probe surface of the thin film sheet 2 is increased, thereby increasing the height up to the probe surface of the thin film sheet 2.

Abstract: Method for dynamically compensating probe tip misalignment with a semiconductor wafer. The wafer is located on a handler and the wafer is adjusted to a first temperature. Probe tips of an inspection system are moved to a first position centered above pads of a test module on the wafer. The first position is recorded in a memory of the inspection system at the first temperature. The wafer and the probe tips are adjusted to a second temperature while the wafer remains in the inspection system. A second position of the probe tips is recorded in the memory while the probe tips and the wafer are equilibrated at the second temperature. A difference between the first and second position is calculated. Relative positions of the probe tips or the wafer is compensated based on the calculated difference, such that the probe tips are re-centered above the pads at the second temperature.

Abstract: Before a plasma doping process is performed, there is generated a plasma of a gas containing an element belonging to the same group in the periodic table as the primary element of a silicon substrate 9, e.g., a monosilane gas, in a vacuum chamber 1. Thus, the inner wall of the vacuum chamber 1 is covered with a silicon-containing film. Then, a plasma doping process is performed on the silicon substrate 9.

Abstract: An integrated circuit device and method. A substrate having contacts has a plurality of capacitors thereon. A plurality of fusible links selectively connect the plurality of capacitors to one another and selected ones of the capacitors to the contacts. In this manner, for example, the capacitance value can be adjusted to tune an antenna mounted on the substrate during testing of the integrated circuit device.

Abstract: Substrates to be aligned comprise microcoils arranged at the level of their facing surfaces. In an alignment phase, power is supplied to at least the microcoils of the first substrate, whereas the inductance of the microcoils of the second substrate is measured. The microcoils are preferably flat microcoils in the form of a spiral or a serpentine.

Abstract: A semiconductor manufacture and testing device is provided, comprising: a process device configured to perform a semiconductor processing operation on a semiconductor wafer; a testing device configured to perform a testing operation on the semiconductor wafer and generate real-time testing metrics relating to the testing operation; a data storage element configured to store the real-time testing metrics as stored testing metrics; a control and dispatch element configured to receive the stored testing metrics and generate dispatch control signals based on the stored testing metrics and a set of evaluation rules; and a test routing element located between the process element and the testing element, and configured to route the semiconductor wafer either from the process element to the testing element or from the process element around the testing element, based the dispatch control signals.

Abstract: An epitaxial silicon wafer is produced with a resistivity in the area adjacent the edge that is greater or less than the resistivity adjacent the center. The wafer may be manufactured by a method wherein one or more process parameters are adjusted during deposition of epitaxial layer to control the edge resistivity. Such process parameters may include using a non-homogeneous temperature and/or a process reactant gas flow across the front surface of the wafer.

Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multilayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multilayer film. A clamping member is provided on the frame to make the multilayer film project out to eliminate slack in the multilayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.

Abstract: A method of forming a probe pad layout/design, and related device. At least some of the illustrative embodiments are methods comprising testing a semiconductor device by electrically contacting a first portion of a semiconductor die by way of a first pad within a scribe street adjacent to the semiconductor die, and electrically contacting a second portion of the semiconductor die by way of a first bond pad within the semiconductor die.

Abstract: A transistor comprises a substrate of a first conductivity type, a drain region and a source region of a second conductivity type, a gate, a gate oxide layer, an adjustment implant region of the first conductivity type and a planar junction. The drain region and the source region are disposed in the substrate. The gate is placed over the substrate between the source region and the drain region. The gate is separated from the substrate by the gate oxide layer. The adjustment implant region is disposed under the gate oxide layer and in the substrate. A second doping concentration of the adjustment implant region is higher than a first doping concentration of the substrate. The adjustment implant region and the drain region in a predetermined shape form the planar junction with a surface curvature pointing towards the drain region to relax electrical field intensity at a location of the planar junction.

Abstract: A method of stacking a chip, including an integrated circuit, onto a substrate including applying an anisotropic conductive film (ACF) or a solder-filled conductive film onto a surface thereof, the surface being configured to electrically couple to the film, placing the chip onto the film, the chip being configured to electrically couple to the film, compressively pressurizing the chip, the film and the surface such that the chip is electrically coupled to the surface via the film,, testing the chip to determine whether the chip is operating normally, reworking the placement of the chip onto the film and repeating the compressive pressurization if the chip is determined to not be operating normally, repeating the testing to determine whether the chip is operating normally, and once the chip is determined to be operating normally, bonding the chip, the film and the surface.

Abstract: A semiconductor and method is disclosed. One embodiment includes a detector arrangement to detect the position of a connection element. A probe tip, the detector arrangement including first connection pads are arranged on a substrate surface. A first circuit is connected to the first connection pads.

Abstract: An approach for predicting dose repeatability in an ion implantation is described. In one embodiment, an ion source is tuned to generate an ion beam with desired beam current. Beam current measurements are obtained from the tuned ion beam. The dose repeatability is predicted for the ion implantation as a function of the beam current measurements.

Abstract: To suppress the occurrence of image quality irregularities in a liquid crystal display device having a TFT substrate which is manufactured by performing steps a plurality of times in such a manner that one region is divided into a plurality of exposure regions, and the plurality of exposure regions is exposed.

Abstract: A system, structure and method is provided for providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structure on which a subject circuit resides. The method is provided for optimizing an electronic system having at least one integrated circuit. The method includes storing a target performance voltage of the at least one integrated circuit; remotely querying the at least one integrated circuit to obtain the target performance voltage; and providing an operational voltage of a next-level assembly according to the stored target performance voltage.

Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.

Abstract: There is provided a tuning method for use by a semiconductor device capable of being fabricated using a plurality of fabrication processes comprising reading a fabrication identification included in the semiconductor device, associating the fabrication identification with one of the plurality of fabrication processes to determine an associated fabrication process used for fabrication of the semiconductor device, and tuning at least one parameter of the semiconductor device based on the associated fabrication process.

Abstract: In a display apparatus and a method of manufacturing the display apparatus, a gate line, a data line, and a plurality of layers are formed on an array substrate on which a pixel area, a pad area, and a peripheral area are defined. During the forming processes of the gate line, the data line, and the layers, the gate line and the data line are partially exposed in the peripheral area, or contact portions formed on the gate line and the data line in the peripheral area are exposed. Thus, the gate line and the data line may be tested using the contact portions as electrical terminals during the manufacturing process of the display apparatus.

Abstract: A technique of manufacturing a semiconductor integrated circuit device is provided for reducing the possibility of attachment of foreign matter to a membrane probe when performing probe inspection using the membrane probe formed by the manufacturing technique. A pressing member for pressing a membrane sheet includes a pressing pin receiving portion relatively disposed above for receiving the tip of a pressing pin of the plunger in a recess, and a membrane sheet pressing portion relatively disposed below. The membrane sheet pressing portion in contact with the membrane sheet has the minimum plane size to enable pressing of the entire surface of one chip of interest to be subjected to the probe inspection.

Abstract: In the present invention, a semiconductor substrate wherein a plurality of MEMS microphones is formed is disposed opposed to a discharge electrode in a state of being stuck on a sheet. Electretization of a dielectric film provided in the MEMS microphone is performed by irradiating the dielectric film between a fixed electrode and a vibration film provided in the MEMS microphone with ions resulting from a corona discharge of the discharge electrode in a state that a predetermined potential difference is applied to the fixed electrode and the vibration film and fixing charges based on the ions to the dielectric film. The electretization is successively performed to each MEMS microphone on the semiconductor substrate by relatively moving the semiconductor substrate and the discharge electrode. Therefore, electretization of the dielectric film in the MEMS microphone chip is realized using a low-cost and simple fabricating equipment and productivity can be enhanced.

Abstract: An element includes a hollow space for a mechanically sensitive electrical element. The element includes a first housing part and a second housing part rigidly connected to the first housing part via joint surfaces. The element also includes connection surfaces on a base of a recess in the first housing the first housing part being covered by the second housing part to form an enclosed hollow space.

Abstract: As the thickness of the card holder for preventing warping of a multilayered wiring substrate 1 is increased, there occurs a problem that a thin film sheet 2 is buried in a card holder and secure contact between probes 7 and test pads cannot be realized. For its prevention, the thin film sheet 2 and a bonding ring 6 are bonded in a state where a tensile force is applied only to the central region IA of the thin film sheet 2, and a tensile force is not applied to an outer peripheral region OA. Then, the height of the bonding ring 6 defining the height up to the probe surface of the thin film sheet 2 is increased, thereby increasing the height up to the probe surface of the thin film sheet 2.

Abstract: By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.

Abstract: A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

Abstract: A printing platform receives (102) (preferably in-line with a semiconductor device printing process (101)) a substrate having at least one semiconductor device printed thereon and further having a test structure printed thereon, which test structure comprises at least one printed semiconductor layer. These teachings then provide for the automatic testing (103) of the test structure with respect to at least one static (i.e., relatively unchanging) electrical characteristic metric. The static electrical characteristic metric (or metrics) of choice will likely vary with the application setting but can include, for example, a measure of electrical resistance, a measure of electrical reactance, and/or a measure of electrical continuity. Optionally (though preferably) the semiconductor device printing process itself is then adjusted (105) as a function, at least in part, of this metric.

Abstract: A method for monitoring current characteristics of a semiconductor device includes forming an isolation layer and a well area over a substrate, and then forming a P+ area and an N+ area spaced apart by the isolation layer to define active areas, and then forming a gate oxide layer over the substrate including the P+ area and the N+ area, and then forming a polysilicon layer over one of the N+ area and the P+ area, and then connecting a electronic measuring probe to one of the N+ area and the P+ area and connecting a power terminal to the polysilicon layer, and then measuring the current characteristics of the semiconductor device using the polysilicon layer as a power pad and one of the N+ area and the P+ area as a pad.

Abstract: The present invention provides an inspection system of ID chips that can supply a signal or power supply voltage to an ID chip without contact, and can increase throughput of an inspection process and an inspection method using the inspection system. The inspection system according to the present invention includes a plurality of inspection electrodes, a plurality of inspection antennas, a position control unit, a unit for applying voltage to each of the inspection antennas, and a unit for measuring potentials of the inspection electrodes. One feature of the inspection system is that a plurality of ID chips and the plurality of inspection electrodes are overlapped with a certain space therebetween, and the plurality of ID chips and the plurality of inspection antennas are overlapped with a certain space therebetween, and the plurality of ID chips are interposed between the plurality of inspection electrodes and the plurality of inspection antennas by the position control unit.

Abstract: Provided is a method for managing manufacturing apparatuses used in a managed production line including a plurality of manufacturing processes for manufacturing an electronic device, each of the apparatuses being used in each of the processes, the method including: acquiring a property of a reference device manufactured in a predetermined reference production line including the manufacturing processes to be performed; performing at least one of the manufacturing processes in the managed production line, performing the other manufacturing processes in the reference production line, and manufacturing a comparison device; measuring a property of the comparison device; comparing the measured properties between the reference and the comparison devices; and judging whether the manufacturing apparatus used in the at least one manufacturing process is defective or not, based on a property difference between the reference and the comparison devices.

Abstract: A semiconductor package includes a substrate, at least one chip including a first side and a backside opposite of the first side, the first side electrically coupled to the substrate, a conductive layer coupled to the backside of the at least one chip, and at least one electronic component coupled to the conductive layer and in electrical communication with the substrate.

Abstract: A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent comprises at least one cell and belongs to one of a plurality circuit constituent types, and applying mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs.

Abstract: An object of the invention is to provide a method and an apparatus for plasma processing which can accurately monitor an ion current applied to the surface of a sample. Predetermined gas is exhausted via an exhaust port 11 by a turbo-molecular pump 3 while introducing the gas within the vacuum chamber 1 from a gas supply device 2, and the pressure within the vacuum chamber 1 is kept at a predetermined value by a pressure regulating valve 4. A high-frequency power supply 5 for a plasma source supplies a high-frequency power to a coil 8 provided near a dielectric window 7 to generate inductively coupled plasma within the vacuum chamber 1. A high-frequency power supply 10 for the sample electrode for supplying the high-frequency power to the sample electrode 6 is provided. A matching circuit 13 for the sample electrode and a high-frequency sensor 14 are provided between the sample electrode high-frequency power supply and the sample electrode 6.

Abstract: There is provided a manufacturing system for manufacturing an electronic device through a plurality of manufacturing stages. The manufacturing system includes a plurality of manufacturing apparatuses performing processes corresponding to the plurality of manufacturing stages.

Abstract: A method for setting predefinable parameters is described, in which for an electronic component, for example a voltage regulator having at least one integrated circuit, the latter has an external connection, via which it is connectable to a programming device. For the latter, a so-called zero programming is provided in the manufacture of the integrated circuit, and predefinable parameters or settings are programmed in following the completion of the manufacturing process, in particular following the assembly of the component or the voltage regulator with the associated generator.

Abstract: Method, system, IC and design structure for meeting a performance requirement using redundant critical path circuits, are disclosed. In one embodiment, the IC includes a plurality of redundant critical path circuits, wherein at least one of the plurality of redundant critical path circuits meeting a performance requirement is operational and the others are non-operational.

Abstract: Zero point shift based on thermal siphon effect occurring actually when a substrate is processed is detected accurately and corrected suitably. The semiconductor fabrication system comprises a gas supply passage (210) for supplying gas into a heat treatment unit (110), an MFC (240) for comparing an output voltage from a detecting unit for detecting the gas flow rate of the gas supply passage with a set voltage corresponding to a preset flow rate and controlling the gas flow rate of the gas supply passage to the set flow rate, and a control unit (300).

Abstract: A method for fabricating copper wiring of a semiconductor device comprises forming a deposition stop time detection pattern having two trench structures positioned with a predetermined distance from each other on a dielectric substrate; positioning a deposition stop time detection apparatus having a plurality of detection electrodes and a guide device above the deposition stop time detection pattern; depositing copper on the substrate; and stopping deposition of the copper by an electric signal being generated when the two detection electrodes are electrically connected by the copper deposited in the two trench structure.

Abstract: Methods of measuring copper impurities on a silicon surface are disclosed. In certain embodiments, copper is electrically activated by ultra-violet illumination of the surface at room temperature. Activation can enhance the copper contribution to surface recombination and to surface voltage which are measured in a non-contact manner using a ac-surface photovoltage and a vibrating Kelvin-probe, respectively. Differential measurements before and after activation enable the separations of the copper impurities from other surface contaminants.

Abstract: According to the present invention, a method for inspecting a semiconductor device includes the steps of carrying out a first test for inspecting characteristic of semiconductor devices under a shielded (dark) condition to discriminate non-defective devices; and carrying out a second test to semiconductor devices, which have been passed the first test as non-defective devices, for inspecting characteristic of the semiconductor devices. The second test is carried out while a predetermined color of light is applied to semiconductor devices.

Abstract: A method for using relatively low-cost silicon with low metal impurity concentration by adding a measured amount of dopant and or dopants before and/or during silicon crystal growth so as to nearly balance, or compensate, the p-type and n-type dopants in the crystal, thereby controlling the net doping concentration within an acceptable range for manufacturing high efficiency solar cells.

Abstract: Gas supplied to gas flow passages of a top plate from a gas supply device by gas supply lines forms flow along a vertical direction along a central axis of a substrate, so that the gas blown from gas blow holes can be made to be uniform, and a sheet resistance distribution is rotationally symmetric around a substrate center.

Abstract: A frame bonded and fixed to a back face of a probe sheet so as to surround a group of pyramid-shaped or truncated pyramid-shaped contact terminals collectively formed at a central region portion of the probe sheet on a probing side thereof is protruded from a multi-layered wiring board, and pressing force is imparted to the frame and a pressing piece at a central portion by a plurality of guide pins having spring property so as to tilt finely.

Abstract: A substrate including a semiconductor layer, where characteristics of an element can be evaluated with high reliability, and an evaluating method thereof are provided. A substrate including a semiconductor layer of the invention has a closed-loop circuit in which an antenna coil and a semiconductor element are connected in series, and a surface of an area over which the circuit is formed is covered with an insulating film. By using such a circuit, a contactless inspection can be carried out. Further, a ring oscillator can be substituted for the closed-loop circuit.

Abstract: A method for improving within-wafer uniformity is provided. The method includes forming an electrical component by a first process step and a second process step, wherein the electrical component has a target electrical parameter. The method includes providing a first plurality of production tools for performing the first process step; providing a second plurality of production tools for performing the second process step; providing a wafer; performing the first process step on the wafer using one of the first plurality of production tools; and selecting a first route including a first production tool from the second plurality of production tools. A within-wafer uniformity of the target electrical parameter on the wafer manufactured by the first route is greater than a second route including a second production tool in the second plurality of production tools.

Abstract: The present invention discloses a wafer level test structure and a test method; in which, a heating plate is formed on the wafer for heating a structure to be tested positioned above or adjacent to the heating plate. The heating plate produces heat by electrically connecting to a current. Thus, the heat provided by the heating plate and the electric input/output into/from the structure to be tested are controlled separately and not influenced each other.

Abstract: In a soldering method for mounting a semiconductor device on a wiring board, a plurality of solid-phase solders are provided between the semiconductor device and the wiring board, and are thermally melted to thereby produce a plurality of liquid-phase solders therebetween. A constant force is exerted on the liquid-phase solders by relatively moving the semiconductor device with respect to the wiring board so that an invariable gap is determined between the semiconductor device and the wiring board.

Abstract: A method of inspecting defects in a semiconductor device includes forming a test pattern in a scribe lane region of a semiconductor substrate. The test pattern includes a second conductive layer formed on an isolation layer of the semiconductor substrate. Further, the method includes measuring a current flowing between the second conductive layer and the semiconductor substrate by applying a first voltage between the second conductive layer and the semiconductor substrate. Defects formed in the isolation layer can be inspected during a semiconductor manufacturing process. Accordingly, the yield of semiconductor devices can be improved with the inspection results.

Abstract: An ion doping apparatus includes: a chamber 11; a discharge section 13 for discharging a gaseous content from within the chamber 11; an ion source 12 being provided in the chamber 11 and including an inlet 14 through which to introduce a gas containing an element to be used for doping, the ion source 12 decomposing the gas introduced through the inlet 14 to generate ions containing the element to be used for doping; an acceleration section 23 for pulling out from the ion source 12 the ions generated at the ion source 12 and accelerating the ions toward a target object held in the chamber; and a beam current meter 26 for measuring a beam current caused by the accelerated ions. The beam current is measured by the beam current meter 26 a plurality of times, and if a result of the measurements indicates a stability of the beam current, the ion doping apparatus automatically begins to implant into the target object the ions containing the element to be used for doping.