Abstract: A method of detecting heavy metal in a semiconductor substrate, includes: a gate oxide film forming step of forming an organic oxide film by spin coating or a sol-gel process, and forming a metal/oxide film/semiconductor junction element by using a mercury probe method; and a step of detecting and quantifying heavy metal by calculating the surface concentration of the heavy metal from junction capacitance characteristics of the element.

Abstract: A chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying their positions. In the chip forming position specifying method, different marks are formed for every chip in a transfer mask (hereinafter called “mark forming mask”) used to form a wiring layer, in addition to normal functional wirings. The positions of the chips on the wafer are respectively specified according to combinations of the marks of a plurality of the mark forming masks, which have been transferred onto the wafer.

Abstract: A circuit architecture provides for the parallel supplying of power during electric or electromagnetic testing of electronic devices integrated on a same semiconductor wafer and bounded by scribe lines. The circuit architecture comprises a conductive grid interconnecting the electronic devices and having a portion external to the devices and a portion internal to the devices. The external portion extends along the scribe lines; and the internal portion extends within at least a part of the devices. The circuit architecture includes interconnection pads between the external portion and the internal portion of the conductive grid and provided on at least a part of the devices, the interconnection pads forming, along with the internal and external portions, power supply lines which are common to different electronic devices of the group.

Abstract: In a display apparatus and a method of manufacturing the display apparatus, a gate line, a data line, and a plurality of layers are formed on an array substrate on which a pixel area, a pad area, and a peripheral area are defined. During the forming processes of the gate line, the data line, and the layers, the gate line and the data line are partially exposed in the peripheral area, or contact portions formed on the gate line and the data line in the peripheral area are exposed. Thus, the gate line and the data line may be tested using the contact portions as electrical terminals during the manufacturing process of the display apparatus.

Abstract: Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.

Abstract: An integrated circuit (IC) that includes a semiconductor die in an IC package. The semiconductor die includes an electrical endpoint. The IC also includes a pad affixed to the semiconductor die. The pad is characterized by a capacitance and is coupled to the electrical endpoint. The IC also includes a bond wire coupling the pad to an IC package pin. The bond wire is an inductor characterized by an inductance. The inductance is configured to decrease signal degradation caused by the capacitance of the pad on electrical signals transmitted between the pin and the electrical endpoint of the semiconductor die.

Abstract: An analysis method for a semiconductor device is described. The semiconductor device having an abnormal region is provided. Thereafter, a focused ion beam microscope analysis process is performed to the abnormal region, wherein the result of the focused ion beam microscope analysis process shows that the abnormal region has a defect therein. After the focused ion beam microscope analysis process, an electrical property measurement step is performed to the abnormal region, so as to determine whether the defect in the abnormal region is a device failure root cause or not.

Abstract: A surface mount type semiconductor device is disclosed. The semiconductor device has testing lands on a lower surface of a wiring substrate with a semiconductor chip mounted thereon. Lower surface-side lands with solder balls coupled thereto respectively and testing lands with solder balls not coupled thereto are formed on a lower surface of a wiring substrate. To suppress the occurrence of contact imperfection between the testing lands and land contacting contact pins provided in a probe socket, the diameter of each testing land is set larger than the diameter of each lower surface-side land. Even when the wiring substrate is reduced in size, electrical characteristic tests using the testing lands can be done with high accuracy.

Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity corresponds to the target band discontinuity.

Abstract: A device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads and a gate including a gate conductor surrounding the nanowire and a fully silicided material surrounding the gate conductor to radially strain the nanowire.

Abstract: A method for manufacturing a semiconductor device, the semiconductor device including an integrated circuit having plural connection terminals arranged on a predetermined local region of the integrated circuit, plural metal bumps, and a wiring layer connected to at least a portion of the connection terminals via the plural metal bumps, the method includes the steps of a) measuring an impedance value of the predetermined local region of the integrated circuit, b) determining whether the measured impedance value matches a predetermined impedance value, c) determining positions of the plural metal bumps in accordance with the determination result of step b), d) forming the plural metal bumps on the positions determined in step c), and e) forming the wiring layer on the plural metal bumps.

Abstract: In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element includes a conductor overlying a space in a resistor.

Abstract: The invention relates to a method for assembly of solar cell modules by arranging a multitude pre-manufactured, individualized solar cells for forming a matrix of solar cells for the solar cell module; depositing a metallization layer at least partially on at least one surface of the matrix of solar cells for forming the solar cell module; testing electrical function at least of the solar cell module; depositing a passivation layer on a surface of the solar cell module. In another aspect the invention relates to a manufacturing system for a solar cell module and a solar cell module (26) comprising a matrix of pre-manufactured and individualized solar cells and manufactured according to the aforementioned method.

Abstract: A passivation structure and fabricating method thereof includes providing a chip having a main die region and a scribe line region defined thereon and a plurality of metal pads respectively positioned in the main die region and the scribe line region, forming a first patterned passivation layer having a plurality of first openings and second openings respectively exposing the metal pads in the main die region and the scribe line region on the chip, and forming a second patterned passivation layer filling the first openings in the scribe line region and having a plurality of third openings corresponding to the first openings thus exposing the metal pads in the main die region.

Abstract: A method of characterizing an ion implantation process, the method including a first step of producing a PN junction degraded by the ion implantation of species, the species implantation being obtained by the ion implantation process to be characterized; a second step of measuring a parameter representative of an electrical conduction of the degraded PN junction and a dispersion of the parameter on a surface on which the degraded PN junction is produced, the parameter and the dispersion forming a reference parameter and a reference dispersion, the first and second steps being repeated in time so as to follow the evolution of the parameter representative of electrical conduction with relation to the reference parameter and the dispersion of the representative parameter with relation to the reference dispersion.

Abstract: Many of the principles of an oxide semiconductor are still unclear and therefore there is no established method for evaluating an oxide semiconductor. Thus, an object is to provide a novel method for evaluating an oxide semiconductor. Carrier density is evaluated, and hydrogen concentration is also evaluated. Specifically, a MOS capacitor (a diode or a triode) is manufactured, and the C-V characteristics of the MOS capacitor are obtained. Then, the carrier density is estimated from the C-V characteristics obtained.

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: The present invention provides a signal transmitting/receiving method comprising: disposing a ferromagnetic film between a semiconductor device having an inductor and an external device which includes an external inductor provided in a position corresponding to the inductor of the semiconductor device; disposing the inductor and the external inductor so as to face each other via the ferromagnetic film therebetween; and in a state in which the inductor and the external inductor face each other, transmitting and receiving the signals between the inductor and the external inductor by electromagnetic induction.

Abstract: A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure includes a first interconnect region in a first interconnect layer, a second interconnect region in a second interconnect layer, and a connecting region electrically connecting the interconnect regions through a first insulating layer. The IH device includes a heating interconnect region through which a heating current flows. The heating interconnect region is within or outside the first or second interconnect region or connecting region. When the heating current is applied, a measurement voltage is applied to the SMT structure, and a current through the SMT structure is measured to detect stress migration properties of the semiconductor module.

Abstract: Systems and methods for detecting and monitoring Nickel-silicide process and induced failures. In a first method embodiment, a method of characterizing a Nickel-silicide semiconductor manufacturing process includes accessing a test chip including a parallel coupled chain of transistors, wherein the transistors are designed for inducing stress into Nickel-silicide features of the transistors, and for increasing a probability of a manufacturing failure of the Nickel-silicide features. A biasing voltage is applied to one terminal of the parallel coupled chain, all other terminals of the parallel coupled chain and grounded, and current is measured at each of the all other terminals of the parallel coupled chain. This process is repeated for each terminal of the parallel coupled chain. The measured currents from all possible conduction paths are compared to determine a manufacturing defect in the parallel coupled chain of transistors.

Abstract: Methods are provided that relate to the capacitive monitoring of characteristic pertaining to layer formed during the back end-of-the-line (BEOL) processing of a semiconductor device. In one embodiment, a method includes the steps of forming a first capacitor array including first and second overlying contacts each formed in a different one of the plurality of BEOL layers, measuring the interlayer capacitance between the first and second overlying contacts, and converting the measured interlayer capacitance to a distance between the first and second overlying contacts.

Abstract: A method of measuring a resistivity of a sidewall of a contact hole formed in a semiconductor device, wherein said semiconductor device includes a first electrode formed on a substrate; a second electrode formed on the first electrode with an insulating film in between; a resist pattern formed on the first electrode and the second electrode; a contact hole formed in the first electrode and the second electrode; and an organic film deposited on the sidewall of the contact hole, includes the steps of: placing a probe needle on the first electrode and the second electrode so that the probe needle contacts with the first electrode and the second electrode several times; establishing electrical conductivity of the probe needle relative to the first electrode and the second electrode; and measuring the resistivity of the organic film between the first electrode and the second electrode.

Abstract: A method for controlling the threshold voltage of a semiconductor element having at least a semiconductor as a component is characterized in including a process to measure one of a threshold voltage and a characteristic value serving as an index for the threshold voltage; a process to determine one of the irradiation intensity, irradiation time, and wavelength of the light for irradiating the semiconductor based on one of the measured threshold voltage and the measured characteristic value serving as the index for the threshold voltage; and a process to irradiate light whose one of the irradiation intensity, irradiation time, and wavelength has been determined onto the semiconductor; wherein the light irradiating the semiconductor is a light having a longer wavelength than the wavelength of the absorption edge of the semiconductor, and the threshold voltage is changed by the irradiation of the light.

Abstract: A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.

Abstract: System for wafer-level phosphor deposition. A method for phosphor deposition on a semiconductor wafer that has a plurality of LED dies includes the operations of covering the semiconductor wafer with a selected thickness of photo resist material, removing portions of the photo resist material to expose portions of the semiconductor wafer so that electrical contacts associated with the plurality of LED dies remain unexposed, and depositing phosphor on the exposed portions of the semiconductor wafer.

Abstract: According to one embodiment, there is provided a method of manufacturing a nonvolatile memory device. In this method, a first voltage may be applied to a variable resistive element having a resistance value which is electrically rewritable in a high resistance and in a low resistance. In this method, a second voltage may be applied to the variable resistive element in a case where the resistance value of the variable resistive element to which the first voltage has been applied is greater than a resistance value of the low resistance and is not greater than a resistance value of the high resistance. Further, in this method, the applying of the second voltage to the variable resistive element may be repeated until the resistance value of the variable resistive element to which the second voltage has been applied falls within a range of the resistance value of the low resistance.

Abstract: A process condition evaluation method for a liquid crystal display module (LCM) includes: a first step of obtaining a threshold power measuring pattern, an analysis sample for a cell bonding status in an LCD fabrication process, and obtaining a lower substrate sample by separating an upper substrate from the threshold power measuring pattern; a second step of supplying voltages on a gate pad on the lower substrate sample with sequentially increasing a voltage level by a predetermined unit by using an electrical device, and obtaining a threshold current and a threshold voltage by measuring currents at a drain pad whenever voltage increased by a predetermined unit is applied to the gate pad; and a third step of obtaining threshold power based on the threshold current and the threshold voltage, and thereby evaluating process conditions of the LCM.

Abstract: A layered chip package includes a plurality of layer portions that are stacked, each of the layer portions including a semiconductor chip. The plurality of layer portions include at least one first-type layer portion and at least one second-type layer portion. The semiconductor chip has a circuit, a plurality of electrode pads electrically connected to the circuit, and a plurality of through electrodes. In every vertically adjacent two of the layer portions, the plurality of through electrodes of the semiconductor chip of one of the two layer portions are electrically connected to the respective corresponding through electrodes of the semiconductor chip of the other of the two layer portions. The first-type layer portion includes a plurality of wires for electrically connecting the plurality of through electrodes to the respective corresponding electrode pads, whereas the second-type layer portion does not include the wires.

Abstract: A method and apparatus for manufacturing an integrated circuit (IC) device (90) is disclosed. A wafer (10) is first provided having a first or top surface and a second or bottom surface. The wafer may be a blank polished or unpolished silicon wafer or the like. High aspect ratio micro-structures (16) that are specifically designed to provide a die level interconnect configuration and mapping, are provided on the first blank surface (12) of the wafer. The wafer with preformed conductive interconnect microstructures (16) are further processed for device fabrication, for example, at the wafer fabrication facilities. Once the front side (12) devices are fabricated, the silicon material (20) is then removed from a second side (14) of the device wafer (10), opposite the first side, to expose the high temperature conductive interconnect microstructures (16). Contacts are formed on the second side of the device wafer using conductive metal.

Abstract: An adaptive switch mode LED driver provides an intelligent approach to driving multiple strings of LEDs. The LED driver determines an optimal current level for each LED channel from a limited set of allowed currents. The LDO driver then determines a PWM duty cycle for driving the LEDs in each LED channel to provide precise brightness control over the LED channels. Beneficially, the LED driver minimizes the power dissipation in the LDO circuits driving each LED string, while also ensuring that the currents in each LED string are maintained within a limited range. A sample and hold LDO allows PWM control over extreme duty cycles with very fast dynamic response. Furthermore, fault protection circuitry ensures fault-free startup and operation of the LED driver.

Abstract: A pressure-sensitive adhesive sheet according to the present invention is a pressure-sensitive adhesive sheet in which a pressure-sensitive adhesive layer is provided on a base film, in which the base film contains conductive fibers, and in which an electrically conductive path is formed between the pressure-sensitive adhesive layer and the base film. With this structure, an electrical continuity test can be performed even in a condition where a semiconductor wafer or a semiconductor chip formed by dicing the semiconductor wafer is applied, and deformation (warping) and damage of the semiconductor wafer and generation of flaws and scratches on the backside can be prevented in the test.

Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

Abstract: A method performs electrical testing and assembly of an electronic device on a wafer and comprising a pad made in an oxide layer covered by a passivation layer. The method includes connecting the electronic device to a testing apparatus; providing said electronic device with a metallization layer extending on the passivation layer from the pad to a non-active area of said wafer. The method comprises-performing the electrical testing on wafer of the electronic device by placing a probe of on a portion of the extended metallization layer; performing the cut of said wafer, reducing the extension of the metallization layer to the edge of the electronic device; embedding the device inside a package, forming on the metallization layer an electrical connection configured to connect the metallization layer to a circuit in said package.

Abstract: The present invention relates to methods and apparatus for providing composition control to thin compound semiconductor films for radiation detector and photovoltaic applications. In one aspect of the invention, there is provided a method in which the molar ratio of the elements in a plurality of layers are detected so that tuning of the multi-element layer can occur to obtain the multi-element layer that has a predetermined molar ratio range. In another aspect of the invention, there is provided a method in which the thickness of a sub-layer and layers thereover of Cu, In and/or Ga are detected and tuned in order to provide tuned thicknesses that are substantially the same as pre-determined thicknesses.

Abstract: A display substrate includes a gate wire, a data wire which crosses the gate wire, a display part, a dummy pixel part and a test part. The display part includes a pixel element electrically connected to the gate wire and the data wire, and the pixel element includes a display element. The dummy pixel part surrounds the display part to protect the pixel element from static electricity. The test part is formed adjacent to the display part and includes a test element having a test display element formed in a substantially same manner as the display element.

Abstract: In the present invention, a semiconductor substrate wherein a plurality of MEMS microphones is formed is disposed opposed to a discharge electrode in a state of being stuck on a sheet. Electretization of a dielectric film provided in the MEMS microphone is performed by irradiating the dielectric film between a fixed electrode and a vibration film provided in the MEMS microphone with ions resulting from a corona discharge of the discharge electrode in a state that a predetermined potential difference is applied to the fixed electrode and the vibration film and fixing charges based on the ions to the dielectric film. The electretization is successively performed to each MEMS microphone on the semiconductor substrate by relatively moving the semiconductor substrate and the discharge electrode. Therefore, electretization of the dielectric film in the MEMS microphone chip is realized using a low-cost and simple fabricating equipment and productivity can be enhanced.

Abstract: An etching resist including first and second portions, the first portion being thicker than the second portion, is formed on a metallic layer. Through the etching resist, a semiconductor layer and the metallic layer are patterned by etching so as to form a wiring from the metallic layer and leave the semiconductor layer under the wiring. An electrical test is conducted on the wiring. The second portion is removed while the first portion is left unremoved. Selective etching is performed through the first portion so as to leave the semiconductor layer unetched to pattern the wiring to be divided into drain and source electrodes. A substrate is cut. In patterning the wiring, the wiring is etched to be cut at a position closer to a cutting line of the substrate with respect to the drain and source electrodes, while leaving the semiconductor layer unetched.

Abstract: To manufacture a photovoltaic device through a first step of sequentially stacking a transparent electrode, a photovoltaic layer, and a rear surface electrode to thereby form a structure in which photovoltaic cells are serially connected, a second step of measuring characteristics of the photovoltaic cell; and a third step of removing, according to a result of measurement, the transparent electrode, the photovoltaic layer, and the rear surface electrode along the serial connection direction, to thereby divide the serially connected photovoltaic cells into a plurality of regions.

Abstract: A device and method for measuring ion beam angle with respect to a substrate is disclosed. The method includes forming a plurality of shadowing structures extending substantially perpendicular from an upper surface of the substrate, directing an ion beam toward the substrate, the plurality of shadowing structures interrupting an incident angle of the ion beam to define implanted and non-implanted portions of the substrate. The method further includes measuring the dose of implanted species within the substrate, determining an implanted surface area as a function of measuring the dose of implant, determining non-implanted surface area based on the implanted surface area, and obtaining the ion beam angle as a function of the non-implanted surface area.

Abstract: A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.

Abstract: To provide a manufacturing method of a semiconductor device capable of placing a larger number of alignment marks for lithography and PCM and at the same time, preventing information leakage from the PCM. In a portion of a first scribe region sandwiched between first semiconductor chip regions, a first region and a second region are placed in parallel to each other. The first region is equipped with at least one monitor selected from a first monitor for electrically evaluating at least either one of an active element (such as transistor) and a passive element (such as resistor or capacitor), a second monitor for dimensional control, and a third monitor for measuring film thickness. In the second region, an alignment mark for lithography is placed. In the cutting step, the first region is cut off.

Abstract: An electrical characteristics test for a semiconductor integrated circuit using a Kelvin contact method can be conducted in a pre-process without obstructing the reduction in size of a semiconductor chip or without complicating the circuit design. A probe card in a testing apparatus includes probes for Kelvin contact, the probes for Kelvin contact including a coil probe and a POGO pin probe disposed inside the coil probe, and a probe for two-terminal measurement. Electrode pads formed in each chip area over a wafer are in a relation of A=B<2A, given that the area of one of the electrode pads with which the probe for Kelvin contact comes into contact is B and the area of the other electrode pad with which the probe for two-terminal measurement comes into contact is A.

Abstract: A method for manufacturing a solar cell, includes: forming a photoelectric converter which includes a plurality of compartment elements, and in which the compartment elements adjacent to each other are electrically connected; specifying a compartment element having a structural defect in the photoelectric converter; restricting a portion in which the structural defect exists in the compartment element by specifying a defect portion based on a resistance distribution that is obtained by measuring resistances of portions between the compartment elements adjacent to each other; and removing the structural defect by supplying a bias voltage to the portion in which the structural defect exists.

Abstract: In a method of manufacturing a semiconductor device, element properties of an element property extraction pattern formed on a semiconductor wafer is extracted as element properties of a current control element corresponding to the element property extraction pattern. A supply energy to the current control element is set which is formed between nodes on the semiconductor wafer, based on the extracted element properties. The set supply energy is supplied to the current control element to irreversible control an electrical connection between the nodes through the device breakdown by the current control element.

Abstract: By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of electrical characteristics of the test metal region. Consequently, by means of the electrical characteristics, respective variations of the etch process may be identified.

Abstract: In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided.

Abstract: A method for manufacturing a solar cell, includes: forming a photoelectric converter which includes a plurality of compartment elements, and in which the compartment elements adjacent to each other are electrically connected; specifying a first compartment element having a structural defect in the photoelectric converter; restricting a portion in which the structural defect exists in the first compartment element by specifying a defect portion based on a resistance distribution that is obtained by measuring resistances of portions between the compartment elements adjacent to each other; and removing or separating off the structural defect by irradiating the first compartment element and a second compartment element with a laser beam so as to intersect a boundary section between the first compartment element including the portion in which the structural defect exists and the second compartment element adjacent to the first compartment element.

Abstract: Provided is a semiconductor apparatus which may check a state of connection of a penetrating electrode in a semiconductor substrate with ease. A semiconductor apparatus manufacturing method includes: forming in a semiconductor substrate at least three kinds of the through-holes each having a large area, a middle area, and a small area of openings; forming a conductive layer on an inner surface of the at least three kinds of the through-holes having different areas of the openings to form the penetrating electrodes; and measuring resistance values of the penetrating electrode including the through-hole having the large area of the opening and the penetrating electrode including the through-hole having the small area of the opening among the three kinds of the penetrating electrodes to determine states of connection of the penetrating electrodes.

Abstract: A method for manufacturing a thin film solar cell is characterized by including a string formation step for forming a string of thin film photoelectric conversion elements which are electrically connected in series and each of which has a first electrode layer, a photoelectric conversion layer and a second electrode layer which are successively laminated on a surface of a translucent insulation substrate; a film removal step for removing the thin film photoelectric conversion element portion formed on the outer circumference of the surface of the translucent insulation substrate by a light beam to form a non-conductive surface region on the entire circumference; and a cleaning step for removing conductive extraneous matters generated in the film removal step and attached to the non-conductive surface region.

Abstract: A method and apparatus for testing a photovoltaic substrate disposes the substrate on a support gantry with connection points such as vacuum cups. The gantry is actuated into a test position. A probe nest coupled to the gantry connects to a junction box on the substrate. A power supply applies voltage to the junction box, and an actuated frame contacts an edge region of the substrate to detect any breakthrough current. The actuated frame comprises a liner for maximizing contact with the edge of the substrate. The liner may be conductive, or may have a conductive surface. Current sensors coupled to the conductive liner of the frame detect any breakthrough current. A solar spectrum simulator provides solar spectrum radiation for testing the photovoltaic properties of the substrate.