Abstract: Provided is a method of de-embedding. The method includes forming a test structure having a device-under-test embedded therein, the test structure having left and right pads coupling the device-under-test, the device-under-test dividing the test structure into left and right half structures, the left and right half structures each having intrinsic transmission parameters; forming a plurality of dummy test structures, each dummy test structure including a left pad and a right pad; measuring transmission parameters of the test structure and the dummy test structures; and deriving intrinsic transmission parameters of the device-under-test using the intrinsic transmission parameters of the left and right half structures and the transmission parameters of the test structure and the dummy test structures.

Abstract: Disclosed is an adhesive sheet for inspection, which is obtained by arranging an adhesive layer on a base film. The base film and the adhesive layer are electrically conductive, and an electrically conductive path is formed between the base film and the adhesive layer. Consequently, an inspection for electrical conduction of a semiconductor wafer or a semiconductor chip obtained by dicing a semiconductor wafer can be performed while the semiconductor wafer or the semiconductor chip is bonded to the adhesive sheet. In addition, this adhesive sheet for inspection enables to prevent deformation (warping) or breakage of a semiconductor wafer or generation of cracks or scratches on the back surface of the semiconductor wafer during the inspection.

Abstract: In various embodiments, optoelectronic devices are described herein. The optoelectronic device may include an optoelectronic cell arranged so as to wrap around a central axis wherein the cell includes a first conductive layer, a semi-conductive layer disposed over and in electrical communication with the first conductive layer, and a second conductive layer disposed over and in electrical communication with the semi-conductive layer. In various embodiments, methods for making optoelectronic devices are described herein. The methods may include forming an optoelectronic cell while flat and wrapping the optoelectronic cell around a central axis. The optoelectronic devices may be photovoltaic devices. Alternatively, the optoelectronic devices may be organic light emitting diodes.

Abstract: A test element group for monitoring leakage current in a semiconductor device and a method of manufacturing the same are disclosed. The test element group for monitoring leakage current in a semiconductor device includes device isolation layers formed over a first conductivity type semiconductor substrate. A second conductivity type well may be formed over the first conductivity type semiconductor substrate. First conductivity type impurity regions may be formed in first active areas between the device isolation layers in the second conductivity type well. Monitoring contacts may be formed within the first active areas to monitor leakage current, using layout data such that a distance from each of the monitoring contacts to a border of each of the first active areas is set to have an allowable minimum value under a predetermined design rule.

Abstract: A wafer containing a plurality of electro-optical devices, each device being enclosed in chamber that has a translucent cover. An X-Y matrix of pairs of interconnections on the wafer are connected to the circuitry of the electro-optical devices for addressing the electro-optical devices. The pairs of interconnections extend outside of the chambers enclosing the devices to testing areas on the periphery of the wafer. Testing is done by signals applied through the interconnections while simultaneously exposing the devices to light through the translucent covers.

Abstract: The present invention relates to a method and device for monitoring a lithographic process of an integrated circuit. In a first step a design for an integrated circuit is provided. The integrated circuit comprises at least an integrated circuit transistor pair having a gate of a first transistor connected to a gate of a second transistor. The gate of the second transistor is designed such that it has a predetermined overlap with respect to a source and a drain of the second transistor. A detection circuit is connected to the at least an integrated circuit transistor pair for detecting if in operation functionality of the second transistor of each of the at least an integrated circuit transistor pair is one of a transistor and a short circuit. The integrated circuit is then manufactured in dependence upon the desogn. After manufacturing, the detection circuit is used to determine the functionality of the second transistor of each of the at least an integrated circuit transistor pair.

Abstract: In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element includes a conductor overlying a space in a resistor.

Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

Abstract: A diagnostic and self-healing treatment system for a semiconductor device, the system provides: i) a shunt busting/blocking treatment, ii) self-healing treatment, and iii) an in-situ non-contact diagnostic determination.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. In one embodiment, the flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer.

Abstract: A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and a stage. In one embodiment, the stage includes: (1) a underlying test segment in the underlying interconnect layer, (2) a overlying test segment in the overlying interconnect layer and (3) logic circuitry activatible after formation of the underlying interconnect layer and before formation of the overlying interconnect layer to place the underlying test segment in the ring path and further activatible after the formation of the overlying interconnect layer to substitute the overlying test segment for the underlying test segment in the ring path.

Abstract: A semiconductor device includes a semiconductor substrate that is made of either of silicon carbide (SiC) and gallium nitride (GaN), and has a defect region containing a crystal defect; a first insulating film that coats the defect region and is arranged on the semiconductor substrate; and a conductor film that electrically connects to a principal surface of the semiconductor substrate, the principal surface being exposed to a region that is not coated with the first insulating film.

Abstract: Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.

Abstract: Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a switching signal generating circuit formed of a PMOS transistor, a resistor, and inverters which outputs an internal switching signal for switching an operating mode between a first operating mode and a second operating mode when an operating state satisfies a predetermined condition, a mode selection pad to which an external switching signal capable of selecting the first operating mode is input in priority to the internal switching signal, and a switching circuit formed of an OR circuit which switches the operating mode between the first operating mode and the second operating mode based on the external switching signal or the internal switching signal. An output from the switching signal generating circuit is input to the mode selection pad via a trimming fuse.

Abstract: The present invention relates to a silicon wafer having testing pad(s) and a method for testing the same. The silicon wafer includes a silicon substrate, an insulation layer, at least one testing pad and a dielectric layer. The testing pad includes a first metal layer, a second metal layer and at least one first interconnection metal. The first metal layer is disposed on the insulation layer, and has a first area and a second area. The first area and the second area are electrically insulated with each other. The second metal layer is disposed above the first metal layer. The first interconnection metal connects the second area of the first metal layer and the second metal layer. Therefore, when a through hole and a seed layer are formed in the following processes, the through hole is estimated whether it is qualified by probing the testing pad to know whether the seed layer connects the second area of the first metal layer of the testing pad, thus the yield rate of the following processes is increased.

Abstract: A print head circuit of an inkjet printer comprising a plurality of row heating elements arranged in a plurality of rows, a plurality of column heating elements arranged in a plurality of columns, and a plurality of lateral bipolar junction transistors (BJTs), each lateral BJT is connected in between and in series with a corresponding one of the plurality of row heating elements and a corresponding one of the plurality of column heating elements, the plurality of lateral BJTs have common bases, wherein the plurality of row heating elements and the plurality of column heating elements are selectively energized to heat ink in the inkjet printer in a desired pattern for printing media, and wherein each of the plurality of lateral BJTs operates to allow the corresponding row and column heating elements that are connected in series with the lateral BJT to be energized.

Abstract: In a process for a semiconductor typically represented by a vertical power MOSFET, etc. of repeating various fabrications in a state of a thin film wafer with the thickness of the wafer being 200 ?m or less, it is a standard procedure of conducting processing in a stage of bonding a reinforcing glass sheet to a device surface of the wafer (main surface on the side of surface) in the step after film thickness-reduction. However according to the study of the present inventors, it has been found that about 70% for the manufacturing cost is concerned with the reinforcing glass sheet. In the present invention, a stress relief insulation film pattern is formed to the peripheral end of the rear face of a wafer in which processing to the device surface (surface side face) of the wafer has been completed substantially and back grinding has been applied.

Abstract: In the current manufacturing process of LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by the voltage-application test (high-temperature and high-humidity test) in an environment of high temperature (such as an approximate range from 85 to 130° C.) and high humidity (such as about 80% RH). For that test, the inventors of the present invention found the phenomenon of occurrence of separation of titanium nitride film as the anti-reflection film from upper film and of generation of cracks in the titanium nitride film at an edge part of upper surface of the aluminum-based bonding pad applied with a positive voltage during the high-temperature and high-humidity test caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film.

Abstract: A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SiP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device.

Abstract: A method of attaching a pair of chips, each having primary contacts that can be mated to each other, involves forming one or more secondary contacts on each of the two chips of a shape sufficient to prevent an initial attachment material from contacting any of the primary contacts during a preliminary attachment operation, the secondary contacts further having a height that will prevent the primary contacts from touching when the secondary contacts are brought into contact with each other, bringing the secondary contacts into closer and closer aligned proximity to each other at least until the primary contacts touch in a first phase, and heating the primary contacts until material between each of corresponding primary contacts on each of the chips in the pair forms an electrical connection.

Abstract: In a semiconductor device constituted of stacked semiconductor chips, in order to independently test each of the chips, a second chip is disposed to face a first chip, with a second interconnection terminal thereof connected to a first interconnection terminal of the first chip. First and second external terminals of the first and second chips are formed on surfaces of the first and second chips, the surface being on a same side of the first and second chips. Therefore, even after the first chip and the second chip are pasted together, it is possible to test the first chip and the second chip while operating them independently. Further, since test probes or the like can be brought into contact with the external terminals of the first chip and the second chip from the same side, it is possible to simultaneously test the first chip and the second chip.

Abstract: A test structure or a circuit element acting temporarily as a test structure may be provided within the die region of sophisticated semiconductor devices, while probe pads may be located in the frame in order to not unduly consume valuable die area. The electrical connection between the test structure and the probe pads may be established by a conductive path including a buried portion, which extends from the die region into the frame below a die seal, thereby maintaining the electrical and mechanical characteristics of the die seal. Hence, enhanced availability of electrical measurement data and superior authenticity of the data may be accomplished, wherein the measurement data may be obtained during the production process.

Abstract: A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and a fifth active region formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.

Abstract: A method of inspecting defects in a semiconductor device includes forming a test pattern in a scribe lane region of a semiconductor substrate. The test pattern includes a second conductive layer formed on an isolation layer of the semiconductor substrate. Further, the method includes measuring a current flowing between the second conductive layer and the semiconductor substrate by applying a first voltage between the second conductive layer and the semiconductor substrate. Defects formed in the isolation layer can be inspected during a semiconductor manufacturing process. Accordingly, the yield of semiconductor devices can be improved with the inspection results.

Abstract: A rewritable nonvolatile memory includes a test cell that is dedicated to testing the storage characteristics of other, similar, storage cells formed within the same integrated circuit memory. The test cell may be share the same structure and composition as storage cells and may be positioned proximate storage cells.

Abstract: A method for forming a light source by plurality of light-emitting units, includes: step (A), determining the number of the light-emitting units based on following factors: the factors include a maximum supply voltage of a power supply circuit and a working voltage of each of the light-emitting units; step (B), determining a set power of each of the light-emitting units based on a set power of the light source and the number of the light-emitting units determined in the step (A); step (C), fabricating or selecting each of the light-emitting units based on the working voltage of each of the light emitting units and the set power of each of the light-emitting units determined in the step (B); step D), forming the light source by connecting each of the light-emitting units obtained in the step (C) in series according to the number of the light-emitting units determined in the step (A).

Abstract: A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level.

Abstract: It is described a method for producing an integrated circuit element comprising a first electric component of a first type and a second electric component of a second type, wherein the two components require different measurement conditions for testing the components as to be defective or as to be defect free. The production method comprises the steps of (a) forming the first and the second component on a substrate, (b) providing a conductor path on the substrate in order to contact the first and the second component, the conductor path comprising a galvanic gap, wherein the galvanic gap provides the possibility to individually connect the first component with a measurement device, (c) accomplishing a test of the first component with the measurement device and (d) in case the test shows a defect free first component, closing the galvanic gap with a conductive connection, and in case the test shows a defective first component, identifying the corresponding integrated circuit element as to be defective.

Abstract: In remote plasma cleaning, it is difficult to locally excite a plasma because the condition is not suitable for plasma excitation different from that at the time of film formation and a method using light has a problem of fogginess of a detection window that cannot be avoided in a CVD process and is not suitable for a mass production process.

Abstract: Embodiments of the present invention relate to semiconducting carbon-containing devices and methods of making thereof. The semi-conducting carbon containing devices comprise an n-type semiconducting layer and a p-type semiconducting layer, both of which are positioned over a substrate. The n-type semiconducting layer can be formed by pyrolyzing a carbon- and nitrogen-containing polymer, and the p-type semiconducting layer can be formed by pyrolyzing an aromatic- and aliphatic-group-containing polymer. In some embodiments, the devices are solar cell devices.

Abstract: A test structure which can be used to detect residual conductive material such as polysilicon which can result from an under etch comprises a PMOS transistor and an OTP EPROM floating gate device. By testing the devices using different testing parameters, it can be determined whether residual conductive material remains subsequent to an etch, and where the residual conductive material is located on the device. A method for testing a semiconductor device using the test structure is also described.

Abstract: Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.

Abstract: A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.

Abstract: A charge transfer device 1 has an P-type region, an N-type well provided to the surficial portion of the P-type region, and transfer electrodes having P-type conductivity, provided over the N-type substrate while placing an insulating film in between.

Abstract: A semiconductor structure formation method and operation method. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball.

Abstract: In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.

Abstract: An analysis method of wafer ion implant is presented, the steps of the method comprises: (a) cleave a wafer for analysis, and (b) from these pieces of wafers determine which ones are wafer with defect and set an insulator on the wafer with defect, (c) finally, use scanning electron microscope to observe whether the ion implant on the wafer with defect was correct or not. Whereby, engineers can take less time to analyze whether the ion implant of the wafer is correct or not with 100% repeatability.

Abstract: A method of characterizing an ion implantation process, the method including a first step of producing a PN junction degraded by the ion implantation of species, the species implantation being obtained by the ion implantation process to be characterized; a second step of measuring a parameter representative of an electrical conduction of the degraded PN junction and a dispersion of the parameter on a surface on which the degraded PN junction is produced, the parameter and the dispersion forming a reference parameter and a reference dispersion, the first and second steps being repeated in time so as to follow the evolution of the parameter representative of electrical conduction with relation to the reference parameter and the dispersion of the representative parameter with relation to the reference dispersion.

Abstract: A probe electrode structure on a substrate is described, comprising a first probe electrode and a neighboring second probe electrode on a layer sequence that generally includes, in a direction from the substrate to the probe electrodes, an electrically conductive bottom layer, an electrically insulating center layer and a electrically conductive top layer. The probe-electrode structure of the invention provides a means to detect an undercutting of the first probe electrode in an etching step that aims at removing the top layer from regions outside the first probe electrode. An undercutting that exceeds an admissible distance from the first edge of the first electrode will remove the first top-layer probe section in the first probe opening, which causes a detectable change of the electrical resistance between the first and second probe electrodes.

Abstract: A three-dimensional (3D) chip is fabricated from components that have been cut out of a two-dimensional (2D) chip to create the layers of the 3D chip. By testing the 2D chip first, the layers of the 3D chip have been pre-tested, thus reducing testing and production costs.

Abstract: A method of manufacturing an MEMS device includes: forming a covering structure having an MEMS structure and a hollow portion, which is located on a periphery of the MEMS structure and is opened to an outside, on a substrate; and performing surface etching for the MEMS structure in a gas phase by supplying an etching gas to the periphery of the MEMS structure from the outside.

Abstract: A semiconductor processing apparatus includes a reaction chamber, a movable susceptor, a movement element, and a control system. The reaction chamber includes a baseplate. The baseplate includes an opening. The movable susceptor is configured to hold a workpiece. The movable element is configured to move a workpiece held on the susceptor towards the opening of the baseplate. The control system is configured to space the susceptor from the baseplate by an unsealed gap during processing of a workpiece in the reaction chamber. Purge gases may flow through the gap into the reaction chamber. Methods of maintaining the gap during processing include calibrating the height of pads and capacitance measurements when the susceptor is spaced from the baseplate.

Abstract: A method of producing an electronic connection device, including: a) formation, in a plane of a support substrate, of at least one first contact element and, in a direction approximately perpendicular to the plane, of at least one second contact element having a first end in electrical contact with the first contact element or elements and a second end, the second contact element or elements including one or more metal tracks standing up along the direction perpendicular to the surface of the substrate; b) then positioning at least one electrical or electronic component in contact with the first contact element or elements; and c) encapsulation of the component(s) and of the first and second contact elements, at least the second end or ends of the second contact element or elements being flush with the surface of the encapsulating material.

Abstract: An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).

Abstract: A method of manufacturing a semiconductor device includes: forming a first pad and a second pad over a substrate; forming a first insulating film over the second pad without forming the first insulating film over the first pad; forming a metal film over the first pad and the second pad; forming an electrode over the first pad with the metal film interposed therebetween; selectively removing the metal film over the second pad; and removing the first insulating film over the second pad.

Abstract: An embodiment of a method for indexing a plurality of die obtainable from a material wafer comprising a plurality of stacked material layers is disclosed. Each die is obtained in a respective position of the wafer; the plurality of dies is obtained by means of a manufacturing process performed in at least one manufacturing stage using at least one lithographic mask for treating a surface of the material wafer trough an exposition to a proper radiation. Said at least one manufacturing stage comprises at least two steps for treating a respective superficial portion of the material wafer that corresponds to a subset of said plurality of dies using the at least one lithographic mask through the exposition to the proper radiation in temporal succession.

Abstract: The present invention relates to a method for trimming passive devices during fabrication to account for process variations. More particularly, the present invention relates to a method by which an adjustable device layer comprised within a passive device (e.g., resistor body, capacitor electrodes) can be measured and subsequently trimmed (e.g., etched to reduce size) during processing to correct for process variations. Essentially, an operational parameter is measured for a plurality of passive devices. The measurements are used to form an adjustment map for a region of a semiconductor body (e.g., wafer) comprising information pertaining to operational parameters as a function of spatial coordinates. The adjustment map is utilized by a DMD projector configured to pattern openings into a hardmask configured over the adjustable device layer. The adjustable device layer is then etched in regions not protected by the hardmask, thereby effectively trimming the passive device according to the adjustment map.

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.