Abstract: A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the second high-voltage insulated-gate field effect transistor from each other; a second device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the third high-voltage insulated-gate field effect transistor from each other; a first impurity diffusion layer of the first conductivity type that is formed below the first device isolation insulating film; and a second impurity diffusion layer of the first conductivity type that is formed below the second device isolation insulating film.

Abstract: A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper. An insulating film may be deposited on the stress liner layers before the polishing, and another insulating film may be deposited above the first insulating film after the polishing. Contacts may be formed such that the contacts need only penetrate one stress liner layer to reach a transistor well or gate structure.

Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract: By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region and the well region that may be conventionally caused by the contact irregularity. Moreover, additionally or alternatively, the surface topography of the semiconductor region and the adjacent isolation trench may be modified prior to the formation of metal silicide regions and contact plugs to enhance the lithography procedure for forming respective contact openings in an interlayer dielectric material. For this purpose, the isolation trench may be brought to an equal or higher level compared to the adjacent semiconductor region.

Abstract: A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask pattern has openings exposing gaps between each two adjacent pillars in the first direction; etching the insulation layer to a predetermined depth using the mask pattern as an etching barrier to form trenches; and filling the trenches with a conductive material to form word lines extending in the first direction.

Abstract: Provided is a method of implanting dopant ions to an integrated circuit. The method includes forming a first pixel and a second pixel in a substrate, forming an etch stop layer over the substrate, forming a hard mask layer over the etch stop layer, patterning the hard mask layer to include an opening between the first pixel and the second pixel, and implanting a plurality of dopants through the opening to form an isolation feature.

Abstract: A description is given of a method for producing isolation trenches (32, 34) with different sidewall dopings on a silicon-based substrate wafer for use in the trench-isolated smart power technology. In this case, a first trench (32) having a first width and a second trench (34) having a second width which is greater than the first width are formed using a hard mask (30). The sidewalls of the first and second trenches are doped in accordance with a first doping type in order to produce sidewalls having a first doping. A material layer (50, 51, 60, 61) is deposited with a thickness determined so as to fill the first trench (32) completely up to and beyond the hard mask and to maintain the gap (34a) in the second trench (34). By means of isotropic etching the material layer is removed from the second trench, but residual material of the material layer is maintained in the first trench.

Abstract: According to one embodiment, a semiconductor device includes: a substrate in which, on a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type and a semiconductor layer of the second conductivity type are stacked; trench that define an element forming region in the substrate; element isolation insulation film formed in the trench; and a semiconductor element formed in the element forming region. The trench include first trench formed from the surface of the substrate to boundary depth and second trench formed from the boundary depth to the bottom and having a diameter smaller than that of the first trench. First diffusion layers connected to the buried layer are formed around the first or second trench according to inter-element breakdown voltage required of the semiconductor element.

Abstract: Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.

Abstract: An integrated circuit has a buried insulation layer formed over a semiconductor substrate, and a semiconductor mesa formed over the buried insulation layer. A low resistivity guard ring substantially surrounds the semiconductor mesa and is in contact with the semiconductor substrate. The low resistivity guard ring is grounded and isolates the semiconductor mesa from RF signals.

Abstract: A method of forming a transistor in a semiconductor device includes forming device isolation structures in a substrate to define an active region. An oxide-based layer and a nitride-based layer are then formed between the active region and the device isolation structures. A predetermined gate region is etched in the active region to form a recess region. The damage layers are formed by a tilted ion implantation process using neutral elements on portions of the oxide-based layer exposed at the sidewalls of the recess region and other portions of the oxide-based layer below the recess region. The damage layers are then removed, thus causing a portion of the active region exposed at the bottom of the recess region to protrude.

Abstract: The prevention of active area loss in the STI model is disclosed which results in an improved device performance in devices manufactured according to the process flow. The process generally shared among the multiple various embodiments inverts the current conventional STI structure towards a process flow where an insulator is patterned with tapered trenches. A segregation layer is formed beneath the surface of the insulator in the tapered trenches. The tapered trenches are then filled with a semiconductor material which is further processed to create a number of active devices. Therefore, the active devices are created in patterned dielectric instead of the STI being created in the semiconductor substrate of the active devices.

Abstract: A doping method for a semiconductor device includes forming a trench in a semiconductor substrate, forming a doped layer doped with a dopant over the undoped layer, and forming a doped region into which the dopant is diffused, wherein the doped region is a portion of the semiconductor substrate in contact with the doped layer.

Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first surface, an active area and a peripheral area. The semiconductor device further includes least one channel stop trench formed in the semiconductor substrate, wherein the channel stop trench extends from the first surface at least partially into the semiconductor substrate and is arranged between the active area and the peripheral area. At least one electrode is arranged in the channel stop trench. The semiconductor substrate includes at least a peripheral contact region, which is arranged in the peripheral area at the first surface of the semiconductor substrate. A conductive layer is provided and in electrical contact with the electrode arranged in the channel stop trench and in electrical contact with the peripheral contact region. The conductive layer is electrically connected to the semiconductor substrate merely in the peripheral area and electrically insulated from the semiconductor substrate in the active area.

Abstract: This invention relates to a method of fabricating a semiconductor device. A P well for a cell junction may be formed by performing an ion implantation process employing a zero tilt condition. Stress caused by collision between a dopant and a Si lattice within a semiconductor substrate may be minimized and, therefore stress remaining within the semiconductor substrate may be minimized. Accordingly, Number Of Program (NOP) fail by disturbance caused by stress remaining within a channel junction may be reduced. Further, a broad doping profile may be formed at the interface of trenches by using BF2 as the dopant when the P well is formed. A fluorine getter layer may be formed on an oxide film of the trench sidewalls and may be used as a boron diffusion barrier. Although a Spin On Dielectric (SOD) insulating layer may be used as an isolation layer, loss of boron (B) may be prevented.

Abstract: A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation.

Abstract: A method for manufacturing semiconductor device has forming a plurality of trenches having at least two kinds of aspect ratios on a semiconductor substrate, filling the plurality of trenches with a coating material containing silicon, forming a mask on the coating material in a part of the trenches among the plurality of trenches filled with the coating material, implanting an ion for accelerating oxidation of the coating material into the coating material in the trenches on which the mask is not formed, forming a first insulating film by oxidizing the coating materials into which the ion is implanted, removing the coating material from the part of the trenches after removing the mask and forming a second insulating film in the part of the trenches from which the coating material is removed.

Abstract: The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.

Abstract: A trench MOSFET structure having improved avalanche capability is disclosed, wherein the source region is formed by performing source Ion Implantation through contact open region of a thick contact interlayer, and further diffused to optimize a trade-off between Rds and the avalanche capability. Thus, only three masks are needed in fabrication process, which are trench mask, contact mask and metal mask. Furthermore, said source region has a doping concentration along channel region lower than along contact trench region, and source junction depth along channel region shallower than along contact trench, and source doping profile along surface of epitaxial layer has Gaussian-distribution from trenched source-body contact to channel region.

Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first surface, an active area and a peripheral area. The semiconductor device further includes least one channel stop trench formed in the semiconductor substrate, wherein the channel stop trench extends from the first surface at least partially into the semiconductor substrate and is arranged between the active area and the peripheral area. At least one electrode is arranged in the channel stop trench. The semiconductor substrate includes at least a peripheral contact region, which is arranged in the peripheral area at the first surface of the semiconductor substrate. A conductive layer is provided and in electrical contact with the electrode arranged in the channel stop trench and in electrical contact with the peripheral contact region. The conductive layer is electrically connected to the semiconductor substrate merely in the peripheral area and electrically insulated from the semiconductor substrate in the active area.

Abstract: A mask structure and process for forming trenches in a silicon carbide or other wafer, and for implanting impurities into the walls of the trenches using the same mask where the mask includes a thin aluminum layer and a patterned hard photoresist mask. A thin LTO oxide may be placed between the metal layer and the hard photoresist mask.

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises an integrated circuit die having a plurality of solder bumps; and a substrate comprising a first plurality of contact pads on a first surface and a second plurality of contact pads on a second surface. The plurality of solder bumps on the integrated circuit die is coupled to the first plurality of contact pads on the first surface of the substrate, wherein at least one edge of the substrate is formed after the integrated circuit die is attached to the substrate. According to one embodiment of the invention, the at least one edge of the substrate is formed after excess substrate material is detached at designated areas. According to another aspect of the invention, an assembly fixture is disclosed. An apparatus and method for assembling an integrated circuit package are also disclosed.

Abstract: Methods for fabricating a device structure in a semiconductor-on-insulator substrate. The method includes forming a first isolation region in the substrate device layer that extends from a top surface of the device layer to a first depth and forming a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth. The method further includes forming a doped region of the device structure in the semiconductor layer that is located vertically between the first isolation region and the insulating layer.

Abstract: Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material.

Abstract: The present invention provides a mountable integrated circuit package system comprising: providing an inner integrated circuit package including a first external interconnect having a shoulder; connecting an intraconnect between a second external interconnect and the shoulder; and forming an outer encapsulation over the inner integrated circuit package, the intraconnect, and partially exposing the first external interconnect on a top encapsulation side of the outer encapsulation and the second external interconnect on a bottom encapsulation side of the outer encapsulation.

Abstract: A system and method is disclosed for providing improved trench isolation of semiconductor devices. An isolation trench of the present invention is manufactured as follows. A substrate of a semiconductor device is provided and a trench is etched in the substrate. Then a silicon liner is grown in the trench. The trench is then filled with polysilicon material. Polysilicon material is also deposited on top of the filled trench to protect the silicon dioxide liner from the effects of subsequent etch procedures and oxidation procedures. The initial height of the polysilicon material is selected to be large enough to allow the polysilicon material to survive the subsequent etch procedures and oxidation procedures.

Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first surface, an active area and a peripheral area. The semiconductor device further includes least one channel stop trench formed in the semiconductor substrate, wherein the channel stop trench extends from the first surface at least partially into the semiconductor substrate and is arranged between the active area and the peripheral area. At least one electrode is arranged in the channel stop trench. The semiconductor substrate includes at least a peripheral contact region, which is arranged in the peripheral area at the first surface of the semiconductor substrate. A conductive layer is provided and in electrical contact with the electrode arranged in the channel stop trench and in electrical contact with the peripheral contact region. The conductive layer is electrically connected to the semiconductor substrate merely in the peripheral area and electrically insulated from the semiconductor substrate in the active area.

Abstract: A method for forming shallow trench isolation in a semiconductor device. The method includes forming a trench in a predetermined depth on a semiconductor substrate, filling the trench with a first filing oxide, injecting an impurity into a portion of the first filling oxide inside the trench, removing the portion of the first filling oxide by wet etching, and filling the trench with a second filling oxide.

Abstract: A method of forming a device isolation film of a semiconductor device is provided. The method of forming a device isolation film of a semiconductor device according to an embodiment includes forming the device isolation film by ion-implanting insulation materials inside of a trench formed on a semiconductor substrate.

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate in which a gate insulating layer and a pad layer are formed in an active region. A first trench is formed in an isolation region of the substrate. A passivation film is formed to cover the pad layer and fill the first trench. A second trench is formed by patterning the pad layer and removing an exposed semiconductor substrate, the second trench being formed within the first trench. An ion implantation process is performed on the semiconductor substrate exposed through the second trench.

Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.

Abstract: An image sensor includes a trench formed by a shallow trench isolation (STI) process, a channel stop layer formed over a substrate in the trench, an isolation structure filled in the trench, and a photodiode formed in the substrate adjacent to a sidewall of the trench. In more detail of the image sensor, a trench is formed in a substrate through a STI process, and a channel stop layer is formed over the substrate in the trench. An isolation structure is formed in the trench, and a photodiode is formed in the substrate adjacent to a sidewall of the trench.

Abstract: An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.

Abstract: An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation region or the pre-metal dielectric layer includes a O3 TEOS oxide having a stress retaining dopant. The O3 TEOS oxide induces a stress in a channel region of the transistor.

Abstract: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length.

Abstract: A method of fabricating a semiconductor device, including: forming a first well of a second conduction type and a second well of a first conduction type on a semiconductor substrate of the first conduction type, forming a gate oxide corresponding to each element on a surface of the semiconductor substrate, forming trenches by etching at forming locations of first and second trench isolating regions respectively at a first depth larger than a depth of a diffusion layer formed in a memory-cell forming region within the second well and smaller than a depth of a diffusion layer of a transistor of a peripheral circuit region, executing additional etching at a forming location of the second trench isolating region so that a second depth larger than the first depth is obtained and doping the trenches at the forming locations of the first and second trench isolating regions respectively, with a doping agent, thereby executing a planarization process.

Abstract: A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material.

Abstract: A semiconductor device and related method of manufacture are disclosed. The device comprises; a trench having a corner portion formed in the semiconductor substrate, a first oxide film formed on an inner wall of the trench and having an upper end portion exposing the corner portion of the semiconductor substrate, a nitride liner formed on the first oxide film, a second oxide film formed in contact with the upper end of the first oxide film and on the exposed corner portion and an upper surface of the semiconductor substrate, a field insulating film formed on the nitride liner to substantially fill the trench, and a field protecting film formed in contact with the second oxide film and filling a trench edge recess formed between the field insulating film and the second oxide film.

Abstract: A method for forming the passivation layer for silicon-isolation interface between photosensitive regions of an image sensor, the method includes providing a substrate having a plurality of spaced apart photosensitive regions that collect charge in response to incident light; etching trenches in the substrate between the photosensitive regions; forming a plurality of masks over the photosensitive regions so that trenches between the photosensitive regions are not covered by the masks; implanting the image sensor with a first low dose to passivate the trenches; filling the trenches with a dielectric to form isolation between the photosensitive regions; forming a plurality of masks which cover the photosensitive regions but does not cover a surface corner of the isolation trench to permit passivation implantation at the surface corner of the trench isolation; and implanting the image sensor at a second low dose to passivate the surface corner of trenched isolation region.

Abstract: A method of making a semiconductor device is disclosed. A semiconductor body, an STI region, a gate and a silicided source/drain region are provided. The STI area is etched, and a liner is formed at the upper surface.

Abstract: Methods of manufacturing a semiconductor structure are disclosed including a deep trench isolation in which a channel stop is formed in the form of an embedded impurity region in the substrate prior to the deep trench etch and formation of transistor devices (FEOL processing) on the substrate. In this fashion, the FEOL processing thermal cycles can activate the impurity region. The deep trench isolations are then formed after FEOL processing. The method achieves the reduced cost of forming deep trench isolations after FEOL processing, and allows the practice of sharing of a collector level between devices to continue. The invention also includes the semiconductor structure so formed.

Abstract: A semiconductor device may include a semiconductor substrate, trench region, buffer pattern, gap fill layer, and transistor. The trench region may be provided in the semiconductor substrate to define an active region. The buffer pattern and gap fill layer may be provided in the trench region. The buffer pattern and gap fill layer may fill the trench region. The gap fill layer may be densified by the buffer pattern. The transistor may be provided in the active region. A method of manufacturing a semiconductor device may include: forming a trench region in a semiconductor substrate; forming a buffer layer on an inner wall of the first trench region; forming a gap fill layer, filling the trench region; performing a thermal process to react the impurity with the oxygen, forming a buffer pattern; and forming a transistor in the active region.

Abstract: A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride margin near the upper edges of the silicon trench walls includes oxynitride corners that are relatively thicker and contain a higher concentration of nitrogen as compared to the other regions of the oxynitride margin. The oxynitride features limit the STI fill height loss and also reduce the formation of divots in the STI fill below the level of the silicon substrate cause by hydrofluoric acid etching and other fabrication processes. Limiting STI fill height loss and the formation of divots improves the functions of the STI structure.

Abstract: A method includes forming trenches in a semiconductor substrate by etching the semiconductor substrate; and then forming a first ion injection layer in sidewalls of the trenches at an active region of the semiconductor substrate; and then forming a second ion injection layer in a substantially horizontally extending surface of the active region located between the trenches; and then performing a threshold voltage adjusting implant on at least the active region, wherein the first ion injection layer and the second ion injection layer overlap at a portion of the active region to provide the overlapping portion with a higher doping concentration than a non-overlapping portion of the active region; and then forming a gate structure on the active region.

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having an implanted buffer layer (133) located in the sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the implanted buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

Abstract: A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench insulation (STI) regions adjacent to the nFETs and pFETs thus can be formed to induce different stress to the channel regions of the respective nFETs and pFETs. As a consequence, performance of both the nFETs and the pFETs can be improved by the STI stress. In addition, the area of the IC can also be reduced as the two silicon layers are positioned vertically relative to one another.

Abstract: A method of forming an isolation structure of a semiconductor device includes implanting dopants of a first type into a semiconductor substrate to form a doped region in the substrate. A mask layer is provided over the substrate and the doped region of the substrate. The mask layer is patterned to expose an isolation region of the substrate, the isolation region defining an active region, the isolation region and the active region being defined at least partly within the doped region. Dopants of a second type are implanted at an edge of the active region as defined by the isolation region. The isolation region of the semiconductor substrate is etched to form an isolation trench having a depth that extends below a depth of the doped region. Dopants of a third type are implanted on sidewalls of the trench in order to minimize the dopants of the second type provided on the sidewalls of the isolation trench from migrating away from the sidewalls.

Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract: There are provided a semiconductor device and a method of forming the same. The semiconductor device may include a semiconductor substrate including a digital circuit region and an analog circuit region, a device isolation layer on the boundary between the digital circuit region and the analog circuit region, a conductive region adjacent to the side surface and the bottom surface of the isolation layer, and a ground pad which is electrically connected to the conductive region and to which a ground voltage is applied.

Abstract: A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are formed in the semiconductor body along the trench edges and are then driven. Insulation caps are then formed over the trenches. Outside spacers are next formed along the sides of the caps. Using these spacers as masks, the semiconductor surface is etched and high conductivity contact regions formed. The outside spacers are then removed and source and drain contacts formed. Alternatively, the source implants are not driven. Rather, prior to outside spacer formation a second source implant is performed. The outside spacers are then formed, portions of the second source implant etched, any remaining source implant driven, and the contact regions formed. The gate electrodes are either recessed below or extend above the semiconductor surface.