Abstract: Integrated circuits, and integrated circuit devices, might include a semiconductor, a first active area in the semiconductor, a second active area in the semiconductor, and an isolation structure in the semiconductor between the first active area and the second active area. The isolation structure might include a first edge portion extending below a surface of the semiconductor to a first depth, a second edge portion extending below the surface of the semiconductor to the first depth, and an interior portion between the first edge portion and the second edge portion, and extending below the surface of the semiconductor to a second depth, less than the first depth.

Abstract: A method for defining a length of a fin including forming a plurality of first slice walls on a mask material layer, which is provided over the fin, using a plurality of hard mask patterns, providing a plurality of fill mask patterns self-aligned with respect to the plurality of first slice walls to expose one or more select areas between one or more pairs of adjacent ones of the plurality of first slice walls, and providing a trim mask pattern including one or more openings and self-aligned with respect to the plurality of second slice walls to expose one or more of the plurality of first slice walls may be provided.

Abstract: A copper pillar bump has a sidewall protection layer formed of an electrolytic metal layer. The electrolytic metal layer is an electrolytic nickel layer, an electrolytic gold layer, and electrolytic copper layer, or an electrolytic silver layer.

Abstract: A semiconductor device manufacturing method is disclosed. The method is to form a second semiconductor layer which has less susceptibility to adopting insulative characteristics than a first semiconductor layer on the first semiconductor layer. Then, grooves which expose portions of the second and first semiconductor layers are formed to extend from the upper surface of the second semiconductor layer into the first semiconductor layer. Next, portions of the first and second semiconductor layers which are exposed to the grooves are changed into an insulator form to fill the grooves with the insulator-form portions of the first semiconductor layer.

Abstract: A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench insulation (STI) regions adjacent to the nFETs and pFETs thus can be formed to induce different stress to the channel regions of the respective nFETs and pFETs. As a consequence, performance of both the nFETs and the pFETs can be improved by the STI stress. In addition, the area of the IC can also be reduced as the two silicon layers are positioned vertically relative to one another.