Abstract: A system that incorporates teachings of the subject disclosure may include, for example, a thin film capacitor a silicon substrate having a silicon dioxide layer; an adhesion layer on the silicon dioxide layer, wherein the adhesion layer is a polar dielectric; a first electrode layer on the adhesion layer; a dielectric layer on the first electrode layer; and a second electrode layer on the dielectric layer. Other embodiments are disclosed.

Abstract: A semiconductor device may include a plurality of single-photon avalanche diodes. The single-photon avalanche diodes may be arranged in microcells. Each microcell may be a split microcell with first and second independent microcell segments. Each microcell segment in the split microcell may have a respective single-photon avalanche diode that is coupled to an output line. The single-photon avalanche diode of each microcell segment may also be coupled to a respective resistor that is used to quench avalanches in the single-photon avalanche diode. Splitting the microcell may reduce the recovery time of each microcell. The segments of the split microcell may be positioned close together, even if susceptible to optical crosstalk. Intra-microcell isolation structures may be formed between the microcell segments. Inter-microcell isolation structures may be formed around a perimeter of the split microcell. The intra-microcell and inter-microcell isolation structures may be different.

Abstract: A semiconductor device includes a first conductive feature and a second conductive feature. A first passivation layer is positioned between the first conductive feature and the second conductive feature. A second passivation layer is positioned between the first conductive feature and the second conductive feature and over the first passivation layer. A lowermost portion of an interface where the first passivation layer contacts the second passivation layer is positioned below 40% or above 60% of a height of the first conductive feature.

Abstract: Apparatuses with a gate electrode in a semiconductor device are described. An example apparatus includes an active region surrounded by an isolation region, and a gate electrode extending in a first direction to pass over the active region. The gate electrode includes a body gate portion over the active region, the body gate portion having a first gate length in a second direction perpendicular to the first direction, a lead-out portion over the isolation region, the lead-out portion having a second gate length in the second direction, the second gate length being greater than the first gate length, and a hammer-head portion having a first end in contact with the body gate portion and a second end opposite to the first end in contact with the hammer-head portion.

Abstract: Reliability of a semiconductor device is improved. A resist pattern having an opening in a first region where a memory transistor is formed and covering other regions is prepared. Next, by ion implantation using this resist pattern as a mask, a channel region is formed in a surface of a semiconductor substrate in the first region, and a nitrogen-introduction portion is formed inside the channel region. Next, the resist pattern is removed. Then, a gate insulating film having a charge storage layer is formed on the semiconductor substrate in the first region, and a gate electrode is formed on the gate insulating film.

Abstract: A method for forming an integrated circuit (IC) and an IC are disclosed. The method for forming the IC includes: forming an isolation structure separating a memory semiconductor region from a logic semiconductor region; forming a memory cell structure on the memory semiconductor region; forming a memory capping layer covering the memory cell structure and the logic semiconductor region; performing a first etch into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure; forming a logic device structure on the logic semiconductor region; and performing a second etch into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.

Abstract: A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.

Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.

Abstract: A method of manufacturing a semiconductor device includes forming a first gate structure on a substrate, the first gate structure including a gate insulation layer, a gate electrode, and a hard mask sequentially stacked on the substrate, forming a preliminary spacer layer on sidewalls of the first gate structure and the substrate, the preliminary spacer layer including silicon nitride, implanting molecular ions into the preliminary spacer layer to form a spacer layer having a dielectric constant lower than a dielectric constant of the preliminary spacer layer, anisotropically etching the spacer layer to form spacers on the sidewalls of the first gate structure, and forming impurity regions at upper portions of the substrate adjacent to the first gate structure.

Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

Abstract: A semiconductor structure comprising a layer of a III-N material and at least a portion of said layer being covered by a passivation layer, wherein the passivation layer comprises a first layer of SiN formed on said at least a portion of said III-N material layer and a second layer of SiN formed on said first layer of SiN; the first SiN layer having a first thickness and generating tensile stress in the structure and the second SiN layer having a second thickness and generating compressive stress in the structure.

Abstract: A semiconductor device including a substrate, a plurality of insulators, a dielectric layer and a plurality of gates is provided. The substrate includes a plurality of trenches and a semiconductor fin between trenches. The insulators are disposed in the trenches. The dielectric layer covers the semiconductor fin and the insulators. A lengthwise direction of the gates is different from a lengthwise direction of the semiconductor fin. The gates comprise at least one first gate that is penetrated by the semiconductor fin and at least one second gate that is not penetrated through by the semiconductor fin. The second gate comprises a broadened portion disposed on the dielectric layer and a top portion disposed on the broadened portion, wherein a bottom width of the broadened portion is greater than a width of the top portion.

Abstract: A method for planarizing a semiconductor device includes steps herein. A substrate is provided, on which a stop layer is formed. A trench is formed in the substrate. A first semiconductor film is deposited conformally on the stop layer and the trench. A second semiconductor film is deposited to fill the trench and cover the first semiconductor film. A chemical-mechanical polishing process is performed until the stop layer is exposed. A removal rate of the chemical-mechanical polishing process on the first semiconductor film is higher than that on the second semiconductor film. The first dielectric layer on the substrate selectively is removed.

Abstract: A substrate having an insulating surface is prepared; a stacked film including a first oxide semiconductor layer and a second oxide semiconductor layer is formed over the substrate; a mask layer is formed over part of the stacked film and then dry etching treatment is performed, so that the stacked film is removed, with a region provided with the mask layer remaining, and a reaction product is formed on a side surface of the remaining stacked film; the reaction product is removed by wet etching treatment after removal of the mask layer; a source electrode and a drain electrode are formed over the stacked film; and a third oxide semiconductor layer, a gate insulating film, and a gate electrode are stacked and formed in this order over the stacked film, and the source electrode and the drain electrode.

Abstract: An apparatus (e.g., a computer device) includes an image coding system and/or an image decoding system. A method of decoding an encoded image includes positioning a first pixel and a second pixel at a midpoint of the first pixel and the second pixel, the midpoint being associated with two colors of a first color space, repositioning the first pixel to a first position, the first position being on a boundary of a second color space and having a value, in the second color space, corresponding to a third color of the first color space, and repositioning the second pixel to a second position, the second position being rotationally symmetric with the repositioned first pixel around the midpoint.

Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.

Abstract: A semiconductor structure includes a semiconductor substrate with a substrate region and a trench extending into the surface region of the semiconductor substrate. The trench includes sidewalls, a bottom and a depth. The semiconductor structure further includes a trench liner overlying the bottom and the sidewalls of the trench. The semiconductor structure also includes a shallow trench isolation structure filling at least the depth of the trench. The shallow trench isolation structure is formed from alternating layers of silicon nitride and high-density plasma oxide.

Abstract: The invention enhances the accuracy of an end point detection when an insulation film formed on a semiconductor substrate is dry-etched. Gate layers made of polysilicon are formed, and an end point detection dummy layer made of polysilicon is formed on a LOCOS. After the gate layers and the dummy layer are formed, a TEOS film is formed on a silicon substrate so as to cover the gate layers and the dummy layer. The TEOS film, a thin gate oxide film and a thick gate oxide film are then dry-etched to form sidewalls on the sidewalls of the gate layers and also expose the front surface of the P well of the silicon substrate in a region surrounded by the LOCOS. The end point detection dummy layer helps the end point detection by being exposed during this dry-etching to enhance the accuracy of the end point detection.

Abstract: Semiconductor devices and methods for making such devices are described. The semiconductor devices are made by providing a semiconductor substrate with an active region, providing a bulk oxide layer in a non-active portion of the substrate, the bulk oxide layer having a first thickness in a protected area of the device, providing a plate oxide layer over the bulk oxide layer and over the substrate in the active region, forming a gate structure on the active region of the substrate, and forming a self-aligned silicide layer on a portion of the substrate and the gate structure, wherein the final thickness of the bulk oxide layer in the protected area after these processes remains substantially the same as the first thickness. The thickness of the bulk oxide layer can be increased without any additional processing steps or any additional processing cost. Other embodiments are described.

Abstract: High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.

Abstract: Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures.

Abstract: Structures and methods for precision trench formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a first oxygen-containing region in a semiconductor substrate by performing an oxygen ion implantation to a portion of the semiconductor substrate, and oxidizing the first oxygen-containing region using oxygen contained therein by performing a thermal processing to the semiconductor substrate, where the first oxygen-containing region is converted to a first oxide region. The method further comprises forming a groove in the semiconductor substrate by eliminating the first oxide region, where the performing thermal processing comprises subjecting the first oxygen-containing region to a gas low on oxygen.

Abstract: Problems with a conventional mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of an insulation film on an inner wall of a mesa groove corresponding to a PN junction, are solved using an inexpensive material, and a mesa type semiconductor device of high withstand voltage and high reliability is offered together with its manufacturing method. A stable protection film made of a thermal oxide film is formed on the inner wall of the mesa groove in the mesa type semiconductor device to cover and protect the PN junction, and an insulation film having negative electric charges is formed to fill a space in the mesa groove covered with the thermal oxide film so that an electron accumulation layer is not easily formed at an interface between an N? type semiconductor layer and the thermal oxide film.

Abstract: High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.

Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor layer including a first region and a second region, a first contact plug disposed on the semiconductor layer and electrically connected to the first region, a second contact plug disposed on the semiconductor layer and electrically connected to the second region, a conductive layer electrically connected to the first contact plug, the conductive layer having a side surface and a bottom surface, and an insulating layer disposed between the conductive layer and the second contact plug so as to insulate the conductive layer from the second contact plug, the insulating layer facing the side surface and a portion of the bottom surface of the conductive layer.

Abstract: A substrate may have active areas at different levels separated by a mask. Along the mask may be a shallow trench isolation. Along the shallow trench isolation may be a LOCOS isolation. The shape of a substrate transition region between the levels may be tunably controlled. The shallow trench isolation may reduce the bird's beak effect.

Abstract: A method of fabricating an extended drain MOS transistor which reduces a design rule and prevents the generation of leakage current. The method includes sequentially forming a diffusion film, a first conductive epitaxial layer, a gate oxide layer and a hard mask layer over a semiconductor substrate, forming a first hard mask pattern having a first thickness by performing a first etching process on the hard mask layer, forming a second hard mask pattern having a second thickness by performing a second etching process on the first hard mask layer, and then forming a thin gate oxide layer by performing a third etching process on the gate oxide layer using the second hard mask pattern as a mask.

Abstract: A field-effect transistor (142) includes a lowly p-doped region 110 formed on a surface of a substrate (102), an n-doped drain region 112 and n-doped source region 114 arranged on a surface of the lowly p-doped region 110, and a device isolation insulating film 132 and device isolation insulating film 134. Here, the device isolation insulating film 132 is formed greater in film thickness than the device isolation insulating film 134; and in the n-doped source region 114, the peak concentration section having a highest dopant concentration is formed in a deeper position than in the n-doped drain region 112.

Abstract: Provided is a LOCOS offset MOS field-effect transistor in which a first lightly-doped N-type drain offset region with a LOCOS oxide film and a second lightly-doped N-type drain offset region without a LOCOS oxide film are formed in a drain-side offset region, and both the regions are covered with a gate electrode. Provision of the first lightly-doped N-type drain offset region mitigates an electric field applied to the first lightly-doped N-type drain offset region to increase a breakdown voltage. Provision of the second lightly-doped N-type drain offset region increases carriers within the second lightly-doped N-type drain offset region to obtain a high current drivability.

Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate; an element isolation region provided in the semiconductor substrate and having an oxide layer and an oxidant-diffusion prevention layer provided on the oxide layer; a gate dielectric film provided on the semiconductor substrate and the oxidant-diffusion prevention layer; and a gate electrode provided on the gate dielectric film.

Abstract: The present application discloses a method for manufacturing a full silicidation metal gate, comprises the steps of forming locally oxidized isolation or shallow trench isolation, performing prior-implantation oxidation and then doping 14N+; removing the prior-implantation oxidation layer formed before ion implantation, performing gate oxidation, and depositing a polysilicon layer; performing lithography and etching to form a gate electrode of polysilicon; implanting and activating dopants; depositing metal such as Ni; performing a first annealing so that Ni reacts with a portion of polysilicon; selectively removing unreacted Ni; performing a second annealing so that the whole gate electrode is converted into nickel silicide to form a full silicidation metal gate electrode. The present invention provides a full silicidation metal gate electrode which overcomes the disadvantages of polysilicon gate electrode.

Abstract: The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically chip regions having different potentials from each other with the aid of isolation trenches (10). In order to prevent voltage rises at sharp edges on the bottom of the isolation trenches, said edges are rounded in a simple process, part of the insulating layer (2) being isotropically etched.

Abstract: Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a bird's beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the bird's beak region and terminating at the inner edge of the bird's beak region, a gate crossing the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the guard region. A variation of a local oxidation of silicon process is used with an additional bird's beak implantation mask as well as minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density.

Abstract: Structures and methods for precision trench formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a first oxygen-containing region in a semiconductor substrate by performing an oxygen ion implantation to a portion of the semiconductor substrate, and oxidizing the first oxygen-containing region using oxygen contained therein by performing a thermal processing to the semiconductor substrate, where the first oxygen-containing region is converted to a first oxide region. The method further comprises forming a groove in the semiconductor substrate by eliminating the first oxide region, where the performing thermal processing comprises subjecting the first oxygen-containing region to a gas low on oxygen.

Abstract: Structures and methods for precision trench formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a first oxygen-containing region in a semiconductor substrate by performing an oxygen ion implantation to a portion of the semiconductor substrate, and oxidizing the first oxygen-containing region using oxygen contained therein by performing a thermal processing to the semiconductor substrate, where the first oxygen-containing region is converted to a first oxide region. The method further comprises forming a groove in the semiconductor substrate by eliminating the first oxide region, where the performing thermal processing comprises subjecting the first oxygen-containing region to a gas low on oxygen.

Abstract: Disclosed is a producing method of a semiconductor device produced by transferring a plurality of substrates into a processing chamber, supplying oxygen-containing gas and hydrogen-containing gas into the processing chamber which is in a heated state to process the plurality of substrates by oxidation, and transferring the plurality of the oxidation-processed substrates out from the processing chamber, wherein the hydrogen-containing gas is supplied from a plurality of locations of a region corresponding to a substrate arrangement region in which the plurality of substrates are arranged in the processing chamber.

Abstract: A CMOS device with polysilicon protection tiles is shown in FIG. 2. LOCOS regions 12.1 and 12.2 separate adjacent active regions 16.1 from 16 and 18.1 from 18, respectively. On the upper surface of the LOCOS regions 12.1, 12.2 are polysilicon tiles 14.1, 14.2, respectively. At the corner of the gate polysilicon 14.3 and the polysilicon tiles 14.1 and 14.2 are oxide spacers 60.1-60.6. The polysilicon tiles 14.1, 14.2 have silicide layers 50.1, 50.2. Other silicide layers 50.4-50.6 are on the tops of the source, drain and polysilicon gate. An insulation layer 32 covers the substrate and metal contacts 36, 34, 38 extend from the surface of the layer 32 to the silicide layers on the source, gate and drain, respectively. The polysilicon tiles are made from the same layer of polysilicon as the gate and they are formed simultaneously with the gates. The intention of the polysilicon tiles is to reduce erosion of the field oxide between closely spaced active regions.

Abstract: An embodiment method for forming a MOS transistor for power applications in a substrate of semiconductor material, said method being integrated in a process for manufacturing integrated circuits which uses an STI technique for forming the insulating regions. The method includes the phases of forming an insulating element on a top surface of the substrate and forming a control electrode on a free surface of the insulating element. The insulating element insulates the control electrode from the substrate. Said insulating element comprises a first portion and a second portion. The extension of the first portion along a first direction perpendicular to the top surface is lower than the extension of the second portion along such first direction. The phase of forming the insulating element comprises generating said second portion by locally oxidizing the top surface.

Abstract: A microelectronic device includes a metal gate with a metal gate upper surface. The metal gate is disposed in an interlayer dielectric first layer. The interlayer dielectric first layer also has an upper surface that is coplanar with the metal gate upper surface. A dielectric etch stop layer is disposed on the metal gate upper surface but not on the interlayer dielectric first layer upper surface.

Abstract: Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.

Abstract: A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region

Abstract: The invention enhances the accuracy of an end point detection when an insulation film formed on a semiconductor substrate is dry-etched. Gate layers made of polysilicon are formed, and an end point detection dummy layer made of polysilicon is formed on a LOCOS. After the gate layers and the dummy layer are formed, a TEOS film is formed on a silicon substrate so as to cover the gate layers and the dummy layer. The TEOS film, a thin gate oxide film and a thick gate oxide film are then dry-etched to form sidewalls on the sidewalls of the gate layers and also expose the front surface of the P well of the silicon substrate in a region surrounded by the LOCOS. The end point detection dummy layer helps the end point detection by being exposed during this dry-etching to enhance the accuracy of the end point detection.

Abstract: Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures.

Abstract: An IGFET that minimizes the effect of the dislocation at the edge of the device region by displacing the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation. This minimizes the lateral diffusion of the source and drain impurities and the formation of metal silicides into the dislocation region. The spacing of the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation region is produced by providing additional lateral opposed second gate regions or oxide barrier layer extending from the oxide layer into the adjacent regions of the substrate region and the first gate region extending therebetween. Both the first gate region and the two second gate regions or barrier layer are used in the self-aligned processing of the source and drain regions. The first gate region defines the length of the channel, while the two opposed second gate regions or barrier layer define the width of the channel region.

Abstract: The present invention provides a method for manufacturing a semiconductor device, comprising the steps of preparing a substrate having a quartz support substrate and a silicon layer, forming a base or substrate silicon oxide film over the entire upper surface of the silicon layer, forming a silicon nitride film over the entire upper surface of the substrate silicon oxide film by a plasma CVD method, patterning the silicon nitride film thereby to form a mask pattern having a circumferential exposure portion that exposes the substrate silicon oxide film in a circumferential area, a first opening pattern that exposes the substrate silicon oxide film in an element isolation area, and a second opening pattern that exposes the substrate silicon oxide film within a peripheral area, and thermally oxidizing the substrate using the mask pattern as a mask thereby to form an element isolation structure portion in the element isolation area.

Abstract: A semiconductor device production method according to the present invention includes the steps of: forming a LOCOS oxide film in a surface of a silicon layer by a LOCOS method; forming an impurity region in the silicon layer by introducing an impurity into the silicon layer; and sequentially removing parts of the LOCOS oxide film and the silicon layer to form a trench for isolation of the impurity region after the formation of the LOCOS oxide film and the impurity region.

Abstract: Shallow trench isolation methods are disclosed. In a particular embodiment, a method includes implanting oxygen under a bottom surface of a narrow trench of a silicon substrate and performing a high-temperature anneal of the silicon substrate to form a buried oxide layer. The method also includes performing an etch to deepen the narrow trench to reach the buried oxide layer. The method further includes depositing a filling material to form a top filling layer in the narrow trench.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes: forming a LDMOS region, an offset drain MOS region, and a CMOS region; simultaneously forming a first well in the LDMOS region and the offset drain MOS region; simultaneously forming a second well in the first well of the LDMOS region and the CMOS region; and forming a second well in the CMOS region, wherein a depth of the first well is larger than a depth of the second well and the second well is a retrograde well formed by a high energy ion implantation method.

Abstract: A method by which generation of leak current can be suppressed and also a fine element can be formed by performing element isolation at a temperature at which a glass substrate can be used is provided. The method includes a first step of forming a base film over a glass substrate; a second step of forming a semiconductor film over the base film; a third step of forming, over the semiconductor film, a film preventing oxidation or nitridation of the semiconductor film into a predetermined pattern; and a fourth step of performing element isolation by radical oxidation or radical nitridation of a region of the semiconductor film, which is not covered with the predetermined pattern, at a temperature of the glass substrate lower than a strain point thereof by 100° C. or more, where radical oxidation or radical nitridation is performed over a semiconductor film placed apart from a plasma generation region, in a plasma treatment chamber with an electron temperature within the range of 0.5 to 1.

Abstract: The present invention provides a method for manufacturing a semiconductor device, comprising the steps of preparing a substrate having a quartz support substrate and a silicon layer, forming a base or substrate silicon oxide film over the entire upper surface of the silicon layer, forming a silicon nitride film over the entire upper surface of the substrate silicon oxide film by a plasma CVD method, patterning the silicon nitride film thereby to form a mask pattern having a circumferential exposure portion that exposes the substrate silicon oxide film in a circumferential area, a first opening pattern that exposes the substrate silicon oxide film in an element isolation area, and a second opening pattern that exposes the substrate silicon oxide film within a peripheral area, and thermally oxidizing the substrate using the mask pattern as a mask thereby to form an element isolation structure portion in the element isolation area.