Abstract: A semiconductor device may include a plurality of wiring structures spaced apart from each other, a protection pattern including a metal nitride on each of the wiring structures, a spacer on a sidewall of the protection pattern, and an insulating interlayer structure containing the wiring structures and having an air gap between the wiring structures.

Abstract: A semiconductor structure that includes: a semiconductor substrate having a semiconductor base and back end of the line (BEOL) wiring layers; a dielectric cap layer on the semiconductor base; trenches on the dielectric cap layer, each of the trenches including dielectric walls, a dielectric bottom in contact with the dielectric cap layer and a metal filling a space between the dielectric walls; air gap openings on the dielectric cap layer and interspersed with the trenches, each air gap opening between the dielectric wall from one metal trench and adjacent to the dielectric wall of a second metal, the dielectric cap layer forming a bottom of the air gap openings; and a second dielectric cap layer formed over the trenches and over the air gap openings, the second dielectric cap layer pinching off each air gap opening.

Abstract: An method including forming multiple interconnect levels on top of one another, each level comprising a metal interconnect and a crack stop both embedded in a dielectric layer, and a dielectric capping layer directly on top of the dielectric layer and directly on top of the metal interconnect, the crack stop is an air gap which intersects an interface between the dielectric layer and the dielectric capping layer of each interconnect level, and forming a through substrate via through the multiple interconnect levels adjacent to, but not in direct contact with, the crack stop, the crack stop of each interconnect level is directly between the metal interconnect of each interconnect level and the through substrate via to prevent cracks caused during fabrication from propagating away from the through substrate via and damaging the metal interconnect.

Abstract: The present disclosure provides a method of fabricating a micro-electro-mechanical systems (MEMS) device. In an embodiment, a method includes providing a substrate including a first sacrificial layer, forming a micro-electro-mechanical systems (MEMS) structure above the first sacrificial layer, and forming a release aperture at substantially a same level above the first sacrificial layer as the MEMS structure. The method further includes forming a second sacrificial layer above the MEMS structure and within the release aperture, and forming a first cap over the second sacrificial layer and the MEMS structure, wherein a leg of the first cap is disposed between the MEMS structure and the release aperture. The method further includes removing the first sacrificial layer, removing the second sacrificial layer through the release aperture, and plugging the release aperture. A MEMS device formed by such a method is also provided.

Abstract: A device manufacturing method includes: sequentially forming a first sacrificial film, a first support film, a second sacrificial film, and a second support film on a semiconductor substrate; forming a hole to pass through these films; forming a crown-shaped electrode covering an inner surface of the hole and connected to the second support film and the first support film; forming a first opening in the second support film into a first pattern designed such that the connection between the crown-shaped electrode and the second support film is at least partially maintained; removing at least a part of the second sacrificial film through the first opening; forming a second opening in the first support film with use of the first opening; and removing the first sacrificial film through the second opening. This method is able to prevent misalignment of openings between the support films.

Abstract: Provided is a semiconductor device (e.g., transistor such as a FinFET or planar device) having a a liner layer and a metal layer (e.g., Tungsten (W)) in a trench (e.g., via CVD and/or ALD). A single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench.

Abstract: A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings.

Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.

Abstract: The present disclosure provides a method of fabricating a micro-electro-mechanical systems (MEMS) device. In an embodiment, a method includes providing a substrate including a first sacrificial layer, forming a micro-electro-mechanical systems (MEMS) structure above the first sacrificial layer, and forming a release aperture at substantially a same level above the first sacrificial layer as the MEMS structure. The method further includes forming a second sacrificial layer above the MEMS structure and within the release aperture, and forming a first cap over the second sacrificial layer and the MEMS structure, wherein a leg of the first cap is disposed between the MEMS structure and the release aperture. The method further includes removing the first sacrificial layer, removing the second sacrificial layer through the release aperture, and plugging the release aperture. A MEMS device formed by such a method is also provided.

Abstract: A device manufacturing method includes: sequentially forming a first sacrificial film, a first support film, a second sacrificial film, and a second support film on a semiconductor substrate; forming a hole to pass through these films; forming a crown-shaped electrode covering an inner surface of the hole and connected to the second support film and the first support film; forming a first opening in the second support film into a first pattern designed such that the connection between the crown-shaped electrode and the second support film is at least partially maintained; removing at least a part of the second sacrificial film through the first opening; forming a second opening in the first support film with use of the first opening; and removing the first sacrificial film through the second opening. This method is able to prevent misalignment of openings between the support films.

Abstract: The present invention related to a lift-off structure adapted to a substrate having a photoelectric device, the structure comprising: a buffer layer, forming on the substrate; an upper sacrificial layer, forming on the buffer layer; an etch stop layer, forming on the upper sacrificial layer, and the photoelectric device structure forming on the etch stop layer.

Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate, forming a first insulating layer, a first redistribution layer, a second insulating layer, a second redistribution layer, and at least one of first processing, in which, after the first electrically conductive material is filled in the first opening to form a first via interconnect, the first redistribution layer is formed on the first insulating layer with the first electrically conductive material such that the first redistribution layer is electrically connected to the first via interconnect; or second processing, in which, after the second electrically conductive material is filled in the second opening to form a second via interconnect, the second redistribution layer is formed on the second insulating layer with the second electrically conductive material such that the second redistribution layer is electrically connected to the second via interconnect.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle, an isolated pad, and a connector; attaching an integrated circuit die to the die attach paddle and the connector; forming an encapsulation over the integrated circuit die, the connector, the die attach paddle, and the isolated pad; and singulating the connector and the die attach paddle whereby the isolated pads are electrically isolated.

Abstract: A device manufacturing method includes: sequentially forming a first sacrificial film, a first support film, a second sacrificial film, and a second support film on a semiconductor substrate; forming a hole to pass through these films; forming a crown-shaped electrode covering an inner surface of the hole and connected to the second support film and the first support film; forming a first opening in the second support film into a first pattern designed such that the connection between the crown-shaped electrode and the second support film is at least partially maintained; removing at least a part of the second sacrificial film through the first opening; forming a second opening in the first support film with use of the first opening; and removing the first sacrificial film through the second opening. This method is able to prevent misalignment of openings between the support films.

Abstract: A method of forming a pattern includes forming a photoresist pattern on a substrate, forming a first material layer on substantially an entire surface of the substrate including the photoresist pattern, heat-treating the substrate including the first material layer and the photoresist pattern, and forming the pattern by removing the photoresist pattern and the portion of the first material layer on the photoresist pattern. A method of manufacturing an array substrate includes forming a pixel region bounded by gate and data lines, and a thin film transistor; an insulating layer is selectively removed to form a passivation layer using a photoresist pattern as an etching mask; a transparent conductive layer is formed on substantially the entire substrate, and the substrate is heat treated. The photoresist pattern and the portion of the transparent conductive layer on the photoresist pattern are removed by a stripping material.

Abstract: An interconnect structure is provided which comprises a semiconductor substrate; a patterned and cured photoresist wherein the photoresist contains a low k dielectric substitutent and contains a fortification layer on its top and sidewall surfaces forming vias or trenches; and a conductive fill material in the vias or trenches. Also provided is a method for fabricating an interconnect structure which comprises depositing a photoresist onto a semiconductor substrate, wherein the photoresist contains a low k dielectric constituent; imagewise exposing the photoresist to actinic radiation; then forming a pattern of vias or trenches in the photoresist; surface fortifying the pattern of vias or trenches proving a fortification layer on the top and sidewalls of the vias or trenches; curing the pattern of vias or trenches thereby converting the photoresist into a dielectric; and filling the vias and trenches with a conductive fill material.

Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.

Abstract: A micro electronic mechanical system structure and a manufacturing method thereof are provided. A substrate has a plurality of conductive regions is provided. A dielectric layer is formed on the substrate. A plurality of openings and recesses are formed in the dielectric layer, wherein the openings expose the conductive regions. The recesses are located between the openings. A conductive layer is formed on the dielectric layer and the openings and the recesses are filled with the conductive layer. The conductive layer is patterned to form a plurality of strips of the first conductive patterns on the dielectric layer and a second conductive pattern on the sidewall and the bottom of each recess, wherein the first conductive patterns are connected with each other through the second conductive patterns. The dielectric layer is removed. The second conductive patterns between the first conductive patterns are removed.

Abstract: A method for forming a laser diode structure. The method includes providing a laser diode material having a surface region. A multilayer dielectric mask structure comprising alternating first and second dielectric layers is formed overlying the surface region. The method forms a laser diode structure using the multilayer dielectric mask structure as a mask. The method selectively removes a portion of the first dielectric layer to form one or more undercut regions between the second dielectric layers. A passivation layer overlies the multilayer dielectric mask structure and the undercut region remained intact. The dielectric mask structure is selectively removed, exposing a top surface region of the laser diode structure. A contact structure is formed overlying at least the exposed top surface region.

Abstract: A method for fabricating a semiconductor device includes the steps of (a) forming a plasma of a gas having carbon and fluorine, and forming an internal insulation film provided with a fluorine-doped carbon film formed on a substrate using the plasma; (b) forming a metal film on the internal insulation film; (c) etching the metal film according to a pattern to form a hard mask; (d) forming a concave part in the fluorine-doped carbon film by etching the fluorine-doped carbon film using the hard mask; (e) forming a film formation of a wiring material on the substrate for filling the concave part with the wiring material; (f) removing an excess part of the wiring material and the hard mask on the fluorine-doped carbon film for exposing a surface of the fluorine-doped carbon film; and (g) removing an oxide formed on the surface of the fluorine-doped film.

Abstract: Methods of controlling deposition of metal on field regions of a substrate in an electroplating process are provided. In one aspect, a dielectric layer is deposited under plasma on the field region of a patterned substrate, leaving a conductive surface exposed in the openings. Electroplating on the field region is reduced or eliminated, resulting in void-free features and minimal excess plating. In another aspect, a resistive layer, which may be a metal, is used in place of the dielectric. In a further aspect, the surface of the conductive field region is modified to change its chemical potential relative to the sidewalls and bottoms of the openings.

Abstract: System and method for forming a structure including a MEMS device structure. In order to prevent warpage of a substrate arising from curing process for a sacrificial material (such as a photoresist), and from subsequent high temperature process steps, an improved sacrificial material comprises (i) a polymer and (ii) a foaming agent or special function group. The structure can be formed by forming a trench in a substrate and filling the trench with a sacrificial material. The sacrificial material includes (i) a polymer and (ii) a foaming agent or special function group. After further process steps are completed, the sacrificial material is removed from the trench.

Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing Cu metal surfaces and dielectric layer surfaces, forming a patterned mask layer on the patterned substrate, where the patterned mask layer contains openings that expose the Cu metal surfaces. The method further includes depositing a metal-containing layer on the Cu metal surfaces, depositing an additional metal-containing layer on the patterned mask layer, and removing the patterned mask layer and the additional metal-containing layer from the patterned substrate to selectively form metal-containing cap layers on the Cu metal surfaces.

Abstract: According to various exemplary embodiments, a spring device that includes a substrate, a self-releasing layer provided over the substrate and a stressed-metal layer provided over the self-releasing layer is disclosed, wherein an amount of stress inside the stressed-metal layer results in a peeling force that is higher than an adhesion force between the self-releasing layer and the stressed-metal layer. Moreover, a method of manufacturing a spring device, according to various exemplary embodiments, includes providing a substrate, providing a self-releasing layer over the substrate and providing a stressed-metal layer over the self-releasing layer wherein an amount of stress inside the stressed-metal layer results in a peeling force that is higher than an adhesion force between the self-releasing layer and the stressed-metal layer is also disclosed in this invention.

Abstract: A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.

Abstract: In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.

Abstract: An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV; and a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting the TWV contact.

Abstract: A planarizing method performed on a non-planar wafer involves forming electrically conductive posts extending through a removable material, each of the posts having a length such that a top of each post is located above a plane defining a point of maximum deviation for the wafer, concurrently smoothing the material and posts so as to form a substantially planar surface, and removing the material. An apparatus includes a non planar wafer having contacts thereon, the wafer having a deviation from planar by an amount that is greater than a height of at least one contact on the wafer, and a set of electrically conductive posts extending away from a surface of the wafer, the posts each having a distal end, the distal ends of the posts collectively defining a substantially flat plane.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate including a conducting layer, a first insulating film formed on the semiconductor substrate and having a via hole formed therein, a lower barrier film formed on an inside wall of the via hole, a first metal wiring formed on the lower barrier film, a second insulating film formed on the first metal wiring and the first insulating film, the second insulating film being provided with a trench which has a width greater than a width of the via hole, an upper barrier film formed on a lower surface of the trench, a second metal wiring formed on the upper barrier film, and a sidewall barrier film formed on sidewalls of the upper barrier film and the second metal wiring. The sidewall barrier film has an L-shaped mirror-symmetrical structure.

Abstract: Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern transfer layers, sacrificial dielectric layer, dielectric cap layer and into the metal wiring layer. The presence of the sacrificial dielectric layer aids in controlling the thickness and profile of the dielectric cap layer which in turn affects reliability of the interconnect.

Abstract: The micro device includes a support substrate, and a movable structure configured to move with respect to the support substrate. At least one of the support substrate and the movable structure is provided with at least one protrusion protruding towards the other of the support substrate and the movable structure. Further, a base portion extending into the one of the support substrate and the movable structure is provided integrally with the at least one protrusion. With this configuration, the protrusion is securely held by the base portion, and the detachment of the protrusion can therefore be prevented even after repeated collisions between the support substrate and the movable structure via the protrusion.

Abstract: Example embodiments are directed to a method of forming a semiconductor structure and a semiconductor structure including a semiconductor unit including a protrusion on a front side of the semiconductor unit and a recess on a backside of the semiconductor unit.

Abstract: There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched.

Abstract: In one embodiment, the present invention includes a method for forming a sacrificial material layer, patterning it to obtain a first patterned sacrificial material layer, embedding the first patterned sacrificial material layer into a dielectric material, treating the first patterned sacrificial material layer to remove it to thus provide a patterned dielectric layer having a plurality of openings in which vias may be formed. Other embodiments are described and claimed.

Abstract: The present invention provides a method of forming interconnects in a photovoltaic module. According to one aspect, a method according to the invention includes processing steps that are similar to those performed in conventional integrated circuit fabrication. For example, the method can include masks and etches to form isolation grooves between cells, and additional etches to form a conductive step adjacent to the grooves that can be used to form interconnects between cells. According to another aspect the method for forming the conductive step can be self-aligned, such as by positioning a mirror above the module and exposing photoresist from underneath the substrate at an angle one or more times, and etching to expose the conductive step. According to another aspect, the process can include steps to form grid lines in the module to improve current transport in the structure.

Abstract: A method is provided for manufacturing removable contact structures on the surface of a substrate to conduct electricity from a contact member to the surface during electroprocessing. The method comprises forming a conductive layer on the surface. A predetermined region of the conductive layer is selectively coated by a contact layer so that the contact member touches the contact layer as the electroprocessing is performed on the conductive layer.

Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device, capable of keeping a peeling layer from being peeled from a substrate in the phase before the completion of a semiconductor element and peeling a semiconductor element rapidly. It is considered that a peeling layer tends to be peeled from a substrate because the stress is applied to a peeling layer due to the difference in thermal expansion coefficient between a substrate and a peeling layer, or because the volume of a peeling layer is reduced and thus the stress is applied thereto by crystallization of the peeling layer due to heat treatment. Therefore, according to one feature of the invention, the adhesion of a substrate and a peeling layer is enhanced by forming an insulating film (buffer film) for relieving the stress on the peeling layer between the substrate and the peeling layer before forming the peeling layer over the substrate.

Abstract: Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes. In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode.

Abstract: An exemplary method includes: providing a substrate with exposed metal and dielectric surfaces, performing a reducing process on the metal and dielectric surfaces, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for selective metal layer deposition.

Abstract: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).

Abstract: There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched.

Abstract: Methods and systems for creating microelectromechanical system (MEMS) gyros. The methods and systems include generating a map of motor bias and creating MEMS gyros based on the map of motor bias to achieve a higher yield of usable MEMS gyros per wafer. The systems include a processor with components configured to determine paths of optimal motor bias for a given deep reactive ion etcher on a wafer, a stepper for imprinting a pattern for each gyro in an orientation that corresponds to the path of optimal motor bias each gyro is calculated to be most near on the wafer, and a deep reactive ion etcher to etch the gyros in the wafer.

Abstract: A method (200) is described for an electronic assembly (30). An electronic die (24) with a sacrificial layer (28) on its back (27) and electrical contacts (26) on its front (25) is temporarily attached by its front (25) to a substrate (32). The back (27) is over-molded by a first material (34) extending over the substrate (32). The substrate (32) is removed leaving the die contacts (26) and the first material (33, 34) exposed. Interconnect layer(s) (44, 64) are provided over the first material (33, 34) and the die (24), electrically coupled to the contacts (26). Further components (66) can be coupled to the upper-most interconnects (64, 53). A second material (68) is over-molded over the components (66) and upper-most interconnects (64, 53). Thinning the first material (34) exposes the sacrificial layer (28) for removal.

Abstract: According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. A plurality of parallel bit line patterns are placed on the bit line interlayer insulating layer. Each of the bit line patterns has a bit line and a bit line capping layer pattern stacked thereon. Bit line spacers covers side walls of the bit line patterns, buried holes penetrate predetermined regions of the bit line interlayer insulating layer between the bit line patterns. And a plurality of storage node contact plugs are placed between the bit line patterns surrounding by the bit line spacers. At this time, the storage node contact plugs fill the buried holes.

Abstract: An exemplary method includes: providing a substrate with an exposed metal surface, performing a reducing process on the metal surface, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for metal layer deposition.

Abstract: In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second metal interconnect are recessed to form recesses. A second insulating film filling the recesses is then formed above a substrate, and the upper portion of the second insulating film is planarized. Next, a hole and a trench are formed to extend halfway through the second insulating film, and ashing and polymer removal are performed. Subsequently to this, the hole and the trench are allowed to reach the first metal interconnect and the second metal interconnect.

Abstract: First material (106) is situated on the surface of a substructure (100 and 102) and in an opening (104), such as a Wench, that extends partway through the substructure. Second material (108) is situated on the first material in the opening. A physical sputter etch is performed on the structure while it is in a sputter etch module (206) to remove the parts of the first material overlying the substructure's surface and situated above the opening and to remove part of the second material overlying the first material in the opening so that remaining parts of the first and second materials are situated in the opening. The so-modified structure is transferred from the sputter etch module under a substantial vacuum, normally via a transfer module (202), to a deposition module (203, 204, or 205) where a layer of third material is deposited over the substructure's surface and over the parts of the first and second materials in the opening.

Abstract: A method for forming a dual damascene structure is provided. In one embodiment, a semiconductor substrate with a patterned protective layer formed thereover is provided. A conformal dielectric layer is formed over the protective layer. A patterned mask layer is formed over the dielectric layer. A portion of the dielectric layer is etched substantially up to about the top surface of the protective layer according to the pattern of the mask layer to form a trench. The protective layer is then removed to form a via hole. A conductive layer is formed in the via hole and the trench, thereby forming a dual damascene structure.

Abstract: In a circuit to drive driven elements such, as electro-optical elements, an electro-optical device has an element layer, a wire-forming layer, and an electronic component layer in order to suppress variation in characteristics of active elements. The element layer has a plurality of organic EL elements, each of which is arranged in a different position in a plane. The electronic component layer has pixel-driving IC chips. The respective pixel-driving IC chips include a plurality of pixel circuits, each of which drives each organic EL element corresponding to the pixel circuit. The wire-forming layer is positioned between the element layer and the electronic component layer. The wire-forming layer has wires to connect the respective pixel circuits included in the pixel-driving IC chips with the organic EL elements corresponding to the pixel circuits.

Abstract: A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.