Local Interconnects; Local Pads (epo) Patents (Class 257/E21.59)
  • Patent number: 11552035
    Abstract: An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: January 10, 2023
    Assignee: Intel Corporation
    Inventors: Zhaozhi Li, Sanka Ganesan, Debendra Mallik, Gregory Perry, Kuan H. Lu, Omkar Karhade, Shawna M. Liff
  • Patent number: 11515247
    Abstract: A device includes a main capacitor composed of a first plate of a first back-end-of-line (BEOL) metallization layer, a main insulator layer on the first plate, and a second plate on the main insulator layer. The second plate is composed of a second BEOL metallization layer. The device includes a first tuning capacitor of a first portion of a first BEOL interconnect trace coupled to the first plate of the main capacitor through first BEOL sideline traces. The first tuning capacitor is composed of a first insulator layer on a surface and sidewalls of the first portion of the first BEOL interconnect trace. The first tuning capacitor includes a second BEOL interconnect trace on a surface and sidewalls of the first insulator layer. The device includes a first via capture pad coupled to the second BEOL interconnect trace of the first tuning capacitor.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: November 29, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Nosun Park, Changhan Hobie Yun, Daniel Daeik Kim, Sameer Sunil Vadhavkar, Paragkumar Ajaybhai Thadesar
  • Patent number: 11462496
    Abstract: In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: October 4, 2022
    Assignee: Kioxia Corporation
    Inventor: Masayoshi Tagami
  • Patent number: 11424338
    Abstract: A semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. Each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. Each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Pei-Yu Wang
  • Patent number: 11152454
    Abstract: In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed into a pattern of a polygon spiral. An embodiment of the pattern of the resistor includes sides and corners. The material of the sides has a low resistivity and the material of the corners has a higher resistivity.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: October 19, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Arash Elhami Khorasani, Mark Griswold
  • Patent number: 11145747
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure protruding therefrom, an insulating layer is over the substrate to cover the fin structure, a gate structure in the insulating layer and over the fin structure, and source and drain features covered by the insulating layer and over the fin structure on opposing sidewall surfaces of the gate structure. The gate structure includes a gate electrode layer, a conductive sealing layer covering the gate electrode layer, and a gate dielectric layer between the fin structure and the gate electrode layer and surrounding the gate electrode layer and the conductive sealing layer. The gate electrode layer has a material removal rate that is higher than the material removal rate of the conductive sealing layer in a chemical mechanical polishing process.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yun Hsu, Hsiao-Kuan Wei
  • Patent number: 11101353
    Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Chang-Ting Chung, Wei-Cheng Lin, Wei-Jung Lin, Chih-Wei Chang
  • Patent number: 11075203
    Abstract: Semiconductor structures are provided. A first logic cell includes a plurality of first transistors over a substrate. Each first transistor includes a first gate electrode across a first channel region. The first gate electrode is electrically connected to a first conductive line of the metal layer through a first contact in a first dielectric layer and a first via in a second dielectric layer over the first dielectric layer. A second logic cell includes a plurality of second transistors over the substrate. Each second transistor includes a second gate electrode across a second channel region. The second gate electrode is electrically connected to a second conductive line of the metal layer directly through a second via in the first and second dielectric layers. The first transistors are surrounded by dummy gate electrodes, and the second transistors are surrounded by dummy gate dielectrics.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10734383
    Abstract: An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: August 4, 2020
    Assignee: Tela Innovations, Inc.
    Inventors: Michael C. Smayling, Scott T. Becker
  • Patent number: 10686036
    Abstract: A method of making a bipolar transistor includes patterning a first photoresist over a collector region of the bipolar transistor, the first photoresist defining a first opening. The method further includes performing a first implantation process through the first opening. The method further includes patterning a second photoresist over the collector region, the second photoresist defining a second opening different from the first opening. The method further includes performing a second implantation process through the second opening, wherein a dopant concentration resulting from the second implantation process is different from a dopant concentration resulting from the first implantation process.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Hsiung Yang, Long-Shih Lin, Kun-Ming Huang, Chih-Heng Shen, Po-Tao Chu
  • Patent number: 10304980
    Abstract: This disclosure provides systems, methods, and apparatus related to solar water splitting. In one aspect, a structure includes a plurality of first nanowires, the plurality of first nanowires comprising an n-type semiconductor or a p-type semiconductor. The structure further includes a second nanowire, the second nanowire comprising the n-type semiconductor or the p-type semiconductor, the second nanowire being a different composition than the plurality of first nanowires. The second nanowire includes a first region and a second region, with the first region having a conductive layer disposed thereon, and each of the plurality of first nanowires being disposed on the conductive layer.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: May 28, 2019
    Assignee: The Regents of the University of California
    Inventors: Peidong Yang, Chong Liu, Jinyao Tang, Hao Ming Chen, Bin Liu
  • Patent number: 9865564
    Abstract: A system for laser ashing of polyimide for a semiconductor manufacturing process is provided. The system includes: a semiconductor chip, a top chip attached to the semiconductor chip by a connection layer, a supporting material, a polyimide glue layer disposed between the supporting material and semiconductor chip, a plasma asher, and an ashing laser configured to ash the polyimide glue on the semiconductor chip.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES INC
    Inventors: Maxime Cadotte, Luc Guerin, Van Thanh Truong, Steve Whitehead
  • Patent number: 9825167
    Abstract: In characteristic test measurements of double-gate-in-trench p-channel power MOSFETs each having a p+ polysilicon gate electrode and a p+ field plate electrode in a trench, which were fabricated according to common design techniques, it has been found that, under conditions where a negative gate bias is applied continuously at high temperature with respect to the substrate, an absolute value of threshold voltage tends to increase steeply after the lapse of a certain period of stress application time. To solve this problem, the present invention provides a p-channel power MOSFET having an n-type polysilicon linear field plate electrode and an n-type polysilicon linear gate electrode in each trench part thereof.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: November 21, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Hitoshi Matsuura, Yoshito Nakazawa
  • Patent number: 9818356
    Abstract: A display device includes a display panel including gate lines, data lines, and pixels connected to the gate line and the data lines, a gate driver driving the gate lines, a level shifter applying a gate clock signal to the gate driver, a data driver driving the data lines, a timing controller generating control signals to control the level shifter, the gate driver, and the data driver, and a backlight unit providing light to the display panel. The level shifter sets a voltage level of a gate-on voltage of the gate clock signal to a voltage level of a first gate-on voltage or a voltage level of a second gate-on voltage higher than the first gate-on voltage in response to a gate-on control signal.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: November 14, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Myung-Ho Won, Jin-Mo Kwon, Yonghwan Kim, Chul Shin, Kwan-Woo Lee, Sung-Woon Im
  • Patent number: 9749561
    Abstract: A solid-state imaging device includes a light receiving section formed by such exposure as to stitch a plurality of patterns in a first direction on a semiconductor substrate. The light receiving section includes a plurality of pixels disposed in a two-dimensional array in the first direction and a second direction perpendicular to the first direction. Electric charges are transferred in the second direction in each of pixel columns consisting of a plurality of pixels disposed in the second direction, among the plurality of pixels.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: August 29, 2017
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Hisanori Suzuki, Masaharu Muramatsu
  • Patent number: 9691714
    Abstract: A semiconductor device of the present invention includes a first interlayer film having a first region and a second region, a MIM structure including a lower electrode formed on the second region, a first capacitance film formed on the lower electrode, and an upper electrode formed on the first capacitance film, a lower metal layer formed on the first region, and disposed in the same layer level with the lower electrode, an auxiliary metal layer disposed in the same layer level with the upper electrode, and opposed to the lower metal layer, a second interlayer film formed on the first interlayer film, and covering the auxiliary metal layer and the MIM structure, and a top metal layer formed on the second interlayer film, and penetrating through the second interlayer film to contact the auxiliary metal layer.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: June 27, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Yoshihiro Hamada, Yushi Sekiguchi
  • Patent number: 9520360
    Abstract: A method for fabricating a multilayer structure includes providing a mask on a device stack disposed on the substrate, the device stack comprising a first plurality of layers composed of a first layer type and a second layer type; directing first ions along a first direction forming a first non-zero angle of incidence with respect to a normal to a plane of the substrate, wherein a first sidewall is formed having a sidewall angle forming a first non-zero angle of inclination with respect to the normal, the first sidewall comprising a second plurality of layers from at least a portion of the first plurality of layers and composed of the first layer type and second layer type; and etching the second plurality of layers using a first selective etch wherein the first layer type is selectively etched with respect to the second layer type.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: December 13, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Anthony Renau, Christopher Hatem
  • Patent number: 9437624
    Abstract: A thin film transistor (TFT) substrate, a flat display apparatus including the TFT substrate, a method of manufacturing the TFT substrate, and a method of manufacturing the flat display apparatus, the thin film transistor (TFT) substrate including a substrate; a first gate electrode on the substrate, the first gate electrode including a first branch electrode and a second branch electrode that are spaced apart from one another; a polysilicon layer on the first gate electrode and insulated from the first gate electrode; and a second gate electrode on the polysilicon layer, the second gate electrode being insulated from the polysilicon layer and overlying the first and second branch electrodes.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: September 6, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Myounggeun Cha, Dongjo Kim, Yoonho Khang, Myounghwa Kim, Kyoungwon Lee
  • Patent number: 9006040
    Abstract: A method of fabricating a semiconductor device is disclosed. A photosensitive material is coated over the device. A plurality of masks for a chip layout are obtained. The plurality of masks are exposed to encompass a chip area of the device using at least one reticle repeatedly. The at least one reticle is of a set of reticles. The chip area has a resultant dimension greater than a dimension of the at least one reticle. A developer is used to remove soluble portions of the photosensitive material forming a resist pattern in the chip area.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Chang Hsieh, Kong-Beng Thei
  • Patent number: 9006100
    Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Yuansheng Ma, Irene Lin, Jason Stephens, Yunfei Deng, Yuan Lei, Jongwook Kye, Rod Augur, Shibly Ahmed, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 9006834
    Abstract: A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: April 14, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T Schultz
  • Patent number: 8987128
    Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Marc Tarabbia, Chinh Nguyen, David Doman, Juhan Kim, Xiang Qi, Suresh Venkatesan
  • Patent number: 8952538
    Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hirohisa Matsuki
  • Patent number: 8946079
    Abstract: A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: February 3, 2015
    Assignee: Tera Probe, Inc.
    Inventors: Shinji Wakisaka, Takeshi Wakabayashi
  • Patent number: 8906799
    Abstract: A method and structure for preventing integrated circuit failure due to electromigration and time dependent dielectric breakdown is disclosed. A randomly patterned metal cap layer is selectively formed on the metal interconnect lines (typically copper (Cu)) with an interspace distance between metal cap segments that is less than the critical length (for short-length effects). Since the diffusivity is lower for the Cu/metal cap interface than for the Cu/dielectric cap interface, the region with a metal cap serves as a diffusion barrier.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ronald G. Filippi, Erdem Kaltalioglu, Wai-Kin Li, Ping-Chuan Wang, Lijuan Zhang
  • Patent number: 8907485
    Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: December 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo M. Higgins, III, Chu-Chung Lee
  • Patent number: 8884436
    Abstract: A semiconductor device includes first pads having centers offset in a first direction, wherein the first pads are arranged in a second direction crossing the first direction; second pads separated in the first direction from the first pads and arranged in the second direction, wherein centers of the second pads are offset in the first direction; first gate lines coupled to the first pads, respectively; and second gate lines coupled to the second pads, respectively.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 11, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hyun Jo Yang
  • Patent number: 8878289
    Abstract: In the semiconductor device, a line-type buried gate is formed by burying a non-operating gate (isolation gate) with a polysilicon material to reduce a work function and a Gate Induced Drain Leakage (GIDL) caused by the non-operating gate, resulting in improvement of refresh characteristics of the semiconductor device. Operating gates including a metal conductive material may be formed in a separate step.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: November 4, 2014
    Assignee: SK hynix Inc.
    Inventor: Kyung Do Kim
  • Patent number: 8872300
    Abstract: A light emitting device module is provided comprising a light emitting device package and a board including first and second dummy pads and an electrode pad arranged between the first and second dummy pads, on which the light emitting device package is disposed, wherein at least one of the first and second dummy pads has a dummy hole, and wherein the electrode pad adjacent to at least one of the first and second dummy pads has an electrode hole.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: October 28, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyunghwa Park
  • Patent number: 8866267
    Abstract: A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side electrode (SSE) and a windowed substrate-side passivation (SSPV) atop SSE can be included. The SSPV defines an area of SSE for spreading solder material during device packaging. A device-side passivation (DSPV) beneath thus covering the device-side of SEDE can be included. A DSE can also include an extended support ledge, stacked below an SEDE, for structurally supporting it during post-wafer processing packaging.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: October 21, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Tao Feng, Anup Bhalla
  • Patent number: 8822994
    Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 2, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Laertis Economikos, Robin Van Den Nieuwenhuizen, Wei-Tsu Tseng
  • Patent number: 8791005
    Abstract: A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: July 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Troy L. Graves-Abe
  • Patent number: 8791562
    Abstract: A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: July 29, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Chung-sun Lee, Jung-Hwan Kim, Yun-hyeok Im, Ji-hwan Hwang, Hyon-chol Kim, Kwang-chul Choi, Eun-kyoung Choi, Tae-hong Min
  • Patent number: 8779577
    Abstract: A semiconductor chip includes a plurality of contact pads, which are arranged in an edge area on a surface of the semiconductor chip. In a semiconductor area of the semiconductor chip, every contact pad of the plurality of contact pads has an associated pad cell provided, which includes at least one of a driver or a receiver and is configured to drive output signals or receive input signals on its associated contact pad, if the driver or receiver is connected to the contact pad. Additionally, for a contact pad which is used as a supply contact pad, the driver or receiver of the associated pad cell is not connected to the contact pad or any other contact pad for driving output signals or receiving input signals on the same.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: July 15, 2014
    Assignee: Infineon Technologies AG
    Inventors: Peter Ossimitz, Matthias Van Daak, Dirk Hesidenz
  • Patent number: 8766257
    Abstract: A test pad structure in a back-end-of-line metal interconnect structure is formed by repeated use of the same mask set, which includes a first line level mask, a first via level mask, a second line level mask, and a second via level mask. The test pad structure includes a two-dimensional array of test pads such that a first row is connected to a device macro structure in the same level, and test pads in another row are electrically connected to another device macro structure of the same design at an underlying level. The lateral shifting of electrical connection among pads located at different levels is enabled by lateral extension portions that protrude from pads and via structures that contact the lateral extension portions. This test pad structure includes more levels of testable metal interconnect structure than the number of used lithographic masks.
    Type: Grant
    Filed: September 8, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventor: Gerald Matusiewicz
  • Patent number: 8759882
    Abstract: An integrated circuit device includes a plurality of dynamic array sections, each of which includes three or more linear conductive segments formed within its gate electrode level in a parallel manner to extend lengthwise in a first direction. An adjoining pair of dynamic array sections are positioned to have co-located portions of outer peripheral boundary segments extending perpendicular to the first direction. Some of the three or more linear conductive segments within the gate electrode levels of the adjoining pair of dynamic array sections are co-aligned in the first direction and separated by an end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the adjoining pair of dynamic array sections. Each of these end-to-end spacings is sized to ensure that each gate electrode level manufacturing assurance halo portion of the first adjoining pair of dynamic array sections is devoid of the co-aligned linear conductive segments.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: June 24, 2014
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 8754525
    Abstract: A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: June 17, 2014
    Assignee: Tera Probe, Inc.
    Inventors: Shinji Wakisaka, Takeshi Wakabayashi
  • Patent number: 8736017
    Abstract: A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: May 27, 2014
    Assignee: SK Hynix Inc.
    Inventors: Se-Aug Jang, Hong-Seon Yang, Ja-Chun Ku, Seung-Ryong Lee
  • Patent number: 8729658
    Abstract: Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: May 20, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Soo Kim, Kwang-Youl Chun, Sang-Bin Ahn
  • Publication number: 20140117533
    Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of contact pads over a substrate, and forming an insulating material over the plurality of contact pads and the substrate. The insulating material is patterned to form an opening over each of the plurality of contact pads, and the plurality of contact pads is cleaned. The method includes forming an under-ball metallization (UBM) structure over the plurality of contact pads and portions of the insulating material. Cleaning the plurality of contact pads recesses a top surface of each of the plurality of contact pads.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Publication number: 20140117534
    Abstract: A structure comprises a first passivation layer formed over a substrate, a second passivation layer formed over the first passivation layer, wherein the second passivation layer includes a first opening with a first dimension, a bond pad embedded in the first passivation layer and the second passivation layer, a protection layer formed on the second passivation layer comprising a second opening with a second dimension, wherein the second dimension is greater than the first dimension and a connector formed on the bond pad.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company. Ltd.
  • Patent number: 8710658
    Abstract: Under bump passive structures, such as capacitors and inductors, may be formed using the post-processing layers in wafer level packaging. In an embodiment, a packaged semiconductor device is described which includes an under-bump capacitor formed in semiconductor device post-processing layers. As part of the post-processing a first dielectric layer is deposited on the active face of a semiconductor die and then in sequence a first metal layer, second dielectric layer and second metal layer are deposited. The under-bump capacitor is formed from a lower plate in the first metal layer and an upper plate in the second metal layer, the plates being separated by the second dielectric layer. In order to increase capacitance, the capacitor may be formed over one or more openings in the first dielectric layer, such that the layers forming the capacitor are no longer planar but follow the underlying topology.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: April 29, 2014
    Assignee: Cambridge Silicon Radio Limited
    Inventor: Zaid Aboush
  • Patent number: 8704343
    Abstract: A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.
    Type: Grant
    Filed: September 8, 2012
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang
  • Publication number: 20140061933
    Abstract: A splash containment structure for semiconductor structures and associated methods of manufacture are provided. A method includes: forming wire bond pads in an integrated circuit chip and forming at least one passivation layer on the chip. The at least one passivation layer includes first areas having a first thickness and second areas having a second thickness. The second thickness is greater than the first thickness. The first areas having the first thickness extend over a majority of the chip. The second areas having the second thickness are adjacent the wire bond pads.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy H. DAUBENSPECK, Jeffrey P. GAMBINO, Christopher D. MUZZY, Wolfgang SAUTER
  • Publication number: 20140054800
    Abstract: A method for manufacturing a metal pad structure of a die is provided, the method including: forming a metal pad between encapsulation material of the die, wherein the metal pad and the encapsulation material are separated from each other by a gap; and forming additional material in the gap to narrow at least a part of the gap.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Johann Gatterbauer, Bernhard Weidgans, Joerg Busch
  • Publication number: 20140048941
    Abstract: A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls.
    Type: Application
    Filed: August 16, 2012
    Publication date: February 20, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Johann Gatterbauer, Bernhard Weidgans
  • Publication number: 20140042642
    Abstract: A conductive line of a semiconductor device includes a conductive layer disposed on a semiconductor substrate. A thickness of the conductive layer is substantially larger than 10000 angstrom (?), and at least a side of the conductive layer has at least two different values of curvature.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 13, 2014
    Inventors: Mu-Chin Chen, Yuan-Sheng Chiang, Chi-Sheng Hsiung
  • Publication number: 20140042627
    Abstract: A secure electronic structure is provided including a via array as a physical unclonable function (PUF). Specifically, the secure electronic structure includes an array of electrical contact vias located between a lower level of a first regularly spaced array of conductors and an upper level of a second regularly spaced array of conductors. Each electrical contact via of the via array is individually addressed through the first regularly spaced array of conductors in the lower level and the second regularly spaced array of conductors in the upper level and has a resistance value. Each resistance value of each electrical contact via forms a distribution of resistance values, wherein the distribution of resistance values is random. This random distribution of the resistance values of the array of electrical contact vias can be used as a physical unclonable function in the electronic structure of the present disclosure.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Edelstein, Gregory M. Fritz, Stephen M. Gates, Dirk Pfeiffer
  • Publication number: 20140042641
    Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 13, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Mahbub Rashed, Yuansheng Ma, Irene Lin, Jason Stephens, Yunfei Deng, Yuan Lei, Jongwook Kye, Rod Augur, Shibly Ahmed, Subramani Kengeri, Suresh Venkatesan
  • Patent number: RE44941
    Abstract: A process of cleaning wire bond pads associated with OLED devices, including the steps of depositing on the wire bond pads one or more layers of ablatable material, and ablating the one or more layers with a laser, thereby exposing a clean wire bond pad.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: June 10, 2014
    Assignee: Emagin Corporation
    Inventors: Amalkumar P. Ghosh, Yachin Liu, Hua Xia Ji