Abstract: A method and structure for preventing integrated circuit failure due to electromigration and time dependent dielectric breakdown is disclosed. A randomly patterned metal cap layer is selectively formed on the metal interconnect lines (typically copper (Cu)) with an interspace distance between metal cap segments that is less than the critical length (for short-length effects). Since the diffusivity is lower for the Cu/metal cap interface than for the Cu/dielectric cap interface, the region with a metal cap serves as a diffusion barrier.

Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.

Abstract: A semiconductor device includes first pads having centers offset in a first direction, wherein the first pads are arranged in a second direction crossing the first direction; second pads separated in the first direction from the first pads and arranged in the second direction, wherein centers of the second pads are offset in the first direction; first gate lines coupled to the first pads, respectively; and second gate lines coupled to the second pads, respectively.

Abstract: In the semiconductor device, a line-type buried gate is formed by burying a non-operating gate (isolation gate) with a polysilicon material to reduce a work function and a Gate Induced Drain Leakage (GIDL) caused by the non-operating gate, resulting in improvement of refresh characteristics of the semiconductor device. Operating gates including a metal conductive material may be formed in a separate step.

Abstract: A light emitting device module is provided comprising a light emitting device package and a board including first and second dummy pads and an electrode pad arranged between the first and second dummy pads, on which the light emitting device package is disposed, wherein at least one of the first and second dummy pads has a dummy hole, and wherein the electrode pad adjacent to at least one of the first and second dummy pads has an electrode hole.

Abstract: A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side electrode (SSE) and a windowed substrate-side passivation (SSPV) atop SSE can be included. The SSPV defines an area of SSE for spreading solder material during device packaging. A device-side passivation (DSPV) beneath thus covering the device-side of SEDE can be included. A DSE can also include an extended support ledge, stacked below an SEDE, for structurally supporting it during post-wafer processing packaging.

Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

Abstract: A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.

Abstract: A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material.

Abstract: A semiconductor chip includes a plurality of contact pads, which are arranged in an edge area on a surface of the semiconductor chip. In a semiconductor area of the semiconductor chip, every contact pad of the plurality of contact pads has an associated pad cell provided, which includes at least one of a driver or a receiver and is configured to drive output signals or receive input signals on its associated contact pad, if the driver or receiver is connected to the contact pad. Additionally, for a contact pad which is used as a supply contact pad, the driver or receiver of the associated pad cell is not connected to the contact pad or any other contact pad for driving output signals or receiving input signals on the same.

Abstract: A test pad structure in a back-end-of-line metal interconnect structure is formed by repeated use of the same mask set, which includes a first line level mask, a first via level mask, a second line level mask, and a second via level mask. The test pad structure includes a two-dimensional array of test pads such that a first row is connected to a device macro structure in the same level, and test pads in another row are electrically connected to another device macro structure of the same design at an underlying level. The lateral shifting of electrical connection among pads located at different levels is enabled by lateral extension portions that protrude from pads and via structures that contact the lateral extension portions. This test pad structure includes more levels of testable metal interconnect structure than the number of used lithographic masks.

Abstract: An integrated circuit device includes a plurality of dynamic array sections, each of which includes three or more linear conductive segments formed within its gate electrode level in a parallel manner to extend lengthwise in a first direction. An adjoining pair of dynamic array sections are positioned to have co-located portions of outer peripheral boundary segments extending perpendicular to the first direction. Some of the three or more linear conductive segments within the gate electrode levels of the adjoining pair of dynamic array sections are co-aligned in the first direction and separated by an end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the adjoining pair of dynamic array sections. Each of these end-to-end spacings is sized to ensure that each gate electrode level manufacturing assurance halo portion of the first adjoining pair of dynamic array sections is devoid of the co-aligned linear conductive segments.

Abstract: A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring.

Abstract: A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer.

Abstract: Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer.

Abstract: A structure comprises a first passivation layer formed over a substrate, a second passivation layer formed over the first passivation layer, wherein the second passivation layer includes a first opening with a first dimension, a bond pad embedded in the first passivation layer and the second passivation layer, a protection layer formed on the second passivation layer comprising a second opening with a second dimension, wherein the second dimension is greater than the first dimension and a connector formed on the bond pad.

Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of contact pads over a substrate, and forming an insulating material over the plurality of contact pads and the substrate. The insulating material is patterned to form an opening over each of the plurality of contact pads, and the plurality of contact pads is cleaned. The method includes forming an under-ball metallization (UBM) structure over the plurality of contact pads and portions of the insulating material. Cleaning the plurality of contact pads recesses a top surface of each of the plurality of contact pads.

Abstract: Under bump passive structures, such as capacitors and inductors, may be formed using the post-processing layers in wafer level packaging. In an embodiment, a packaged semiconductor device is described which includes an under-bump capacitor formed in semiconductor device post-processing layers. As part of the post-processing a first dielectric layer is deposited on the active face of a semiconductor die and then in sequence a first metal layer, second dielectric layer and second metal layer are deposited. The under-bump capacitor is formed from a lower plate in the first metal layer and an upper plate in the second metal layer, the plates being separated by the second dielectric layer. In order to increase capacitance, the capacitor may be formed over one or more openings in the first dielectric layer, such that the layers forming the capacitor are no longer planar but follow the underlying topology.

Abstract: A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.

Abstract: A splash containment structure for semiconductor structures and associated methods of manufacture are provided. A method includes: forming wire bond pads in an integrated circuit chip and forming at least one passivation layer on the chip. The at least one passivation layer includes first areas having a first thickness and second areas having a second thickness. The second thickness is greater than the first thickness. The first areas having the first thickness extend over a majority of the chip. The second areas having the second thickness are adjacent the wire bond pads.

Abstract: A method for manufacturing a metal pad structure of a die is provided, the method including: forming a metal pad between encapsulation material of the die, wherein the metal pad and the encapsulation material are separated from each other by a gap; and forming additional material in the gap to narrow at least a part of the gap.

Abstract: A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls.

Abstract: A conductive line of a semiconductor device includes a conductive layer disposed on a semiconductor substrate. A thickness of the conductive layer is substantially larger than 10000 angstrom (?), and at least a side of the conductive layer has at least two different values of curvature.

Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.

Abstract: A secure electronic structure is provided including a via array as a physical unclonable function (PUF). Specifically, the secure electronic structure includes an array of electrical contact vias located between a lower level of a first regularly spaced array of conductors and an upper level of a second regularly spaced array of conductors. Each electrical contact via of the via array is individually addressed through the first regularly spaced array of conductors in the lower level and the second regularly spaced array of conductors in the upper level and has a resistance value. Each resistance value of each electrical contact via forms a distribution of resistance values, wherein the distribution of resistance values is random. This random distribution of the resistance values of the array of electrical contact vias can be used as a physical unclonable function in the electronic structure of the present disclosure.

Abstract: A semiconductor device and method of fabricating the same reduce the likelihood of the occurrence of electrical defects. The device includes a first interlayer insulating film on a semiconductor substrate; a contact pad spacer on the first interlayer insulating film; and a contact pad in the first interlayer insulating film and the contact pad spacer. The cross-sectional area of an upper portion of the contact pad in the contact pad spacer in a direction horizontal to the substrate is equal to or less than a cross-sectional area of an intermediate portion at an interface between the contact pad spacer and the first interlayer insulating film in a direction horizontal to the substrate.

Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.

Abstract: Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.

Abstract: In one example, a stress gauge for an integrated circuit product is disclosed that includes a layer of insulating material, a body positioned at least partially in the layer of insulating material, wherein the body is comprised of a material having a piezoelectric constant of at least about 0.1 pm/V, and a plurality of spaced apart conductive contacts, each of which is conductively coupled to the body.

Abstract: An apparatus comprises a first dielectric layer formed over a substrate, a first metal line embedded in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, a second metal line embedded in the second dielectric layer, an interconnect structure formed between the first metal line and the second metal line, a first carbon layer formed between the first metal line and the interconnect structure and a second carbon layer formed between the second metal line and the interconnect structure.

Abstract: Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need.

Abstract: In various embodiments, a method of processing a contact pad may include providing a contact pad, a topmost layer of the contact pad containing aluminum or an aluminum alloy, at least part of the topmost layer of the contact pad being exposed; subjecting the contact pad to a thermally activated atmosphere containing water or reactive components of water.

Abstract: A releasable buried layer for 3-D fabrication and methods of manufacturing is disclosed. The method includes forming an interposer structure which includes forming a carbon rich dielectric releasable layer over a wafer. The method further includes forming back end of the line (BEOL) layers over the carbon rich dielectric layer, including wiring layers and solder bumps. The method further includes bonding the solder bumps to a substrate using flip chip processes. The flip chip processes comprises reflowing the solder bumps and rapidly cooling down the solder bumps which releases the carbon rich dielectric releasable layer from the wafer.

Abstract: A semiconductor device and its manufacturing method are offered to increase the number of semiconductor devices obtained from a semiconductor wafer while simplifying a manufacturing process. After forming a plurality of pad electrodes in a predetermined region on a top surface of a semiconductor substrate, a supporter is bonded to the top surface of the semiconductor substrate through an adhesive layer. Next, an opening is formed in the semiconductor substrate in a region overlapping the predetermined region. A wiring layer electrically connected with each of the pad electrodes is formed in the opening. After that, a stacked layer structure including the semiconductor substrate and the supporter is cut by dicing along a dicing line that is outside the opening.

Abstract: A method for forming patterns of dense conductor lines and their contact pads is described. Parallel base line patterns are formed over a substrate. Each of the base line patterns is trimmed. Derivative line patterns and derivative transverse patterns are formed as spaces on the sidewalls of the trimmed base line patterns, wherein the derivative transverse patterns are formed between the ends of the derivative line patterns and adjacent to the ends of the trimmed base line patterns. The trimmed base line patterns are removed. At least end portions of the derivative line patterns are removed, such that the derivative line patterns are separated from each other and all or portions of the derivative transverse patterns become patterns of contact pads each connected with a derivative line pattern.

Abstract: A method of patterning a metal layer is disclosed. The method includes providing a substrate and forming a material layer over the substrate. The method includes forming a second material layer over the first material layer. The method includes performing a first patterning process to the second material layer to form a trench in the second material layer. The first patterning process defines a width size of the trench, the width size being measured in a first direction. The method includes performing a second patterning process to the trench to transform the trench. The second patterning process defines a length size of the transformed trench. The length size is measured in a second direction different from the first direction. The method also includes filling the transformed trench with a conductive material.

Abstract: A semiconductor wafer has a first conductive layer formed over its active surface. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A UBM layer is formed around a bump formation area over the second conductive layer. The UBM layer can be two stacked metal layers or three stacked metal layers. The second conductive layer is exposed in the bump formation area. A second insulating layer is formed over the UBM layer and second conductive layer. A portion of the second insulating layer is removed over the bump formation area and a portion of the UBM layer. A bump is formed over the second conductive layer in the bump formation area. The bump contacts the UBM layer to seal a contact interface between the bump and second conductive layer.

Abstract: Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a method for fabricating a semiconductor device comprises forming a dielectric layer on an active side of a semiconductor substrate. The dielectric layer has openings aligned with corresponding wirebond sites at the active side of the substrate. The method further includes forming a plurality of wirebond sites located at the openings in the dielectric layer. The wirebond sites are electrically coupled to an integrated circuit in the semiconductor substrate and electrically isolated from each other. Individual wirebond sites are formed by electrolessly depositing nickel into the openings and forming a wirebond film on the nickel without forming a seam between the nickel and the dielectric layer.

Abstract: A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.

Abstract: A profiled contact for a device, such as a high power semiconductor device is provided. The contact is profiled in both a direction substantially parallel to a surface of a semiconductor structure of the device and a direction substantially perpendicular to the surface of the semiconductor structure. The profiling can limit the peak electric field between two electrodes to approximately the same as the average electrical field between the electrodes, as well as limit the electric field perpendicular to the semiconductor structure both within and outside the semiconductor structure.

Abstract: A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.

Abstract: A bonding pad structure includes a substrate and a first conductive island formed in a first dielectric layer and disposed over the substrate. A first via array having a plurality of vias is formed in a second dielectric layer and disposed over the first conductive island. A second conductive island is formed in a third dielectric layer and disposed over the first via array. A bonding pad is disposed over the second conductive island. The first conductive island, the first via array, and the second conductive island are electrically connected to the bonding pad. The first via array is connected to no other conductive island in the first dielectric layer except the first conductive island. No other conductive island in the third dielectric layer is connected to the first via array except the second conductive island.

Abstract: A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

Abstract: A semiconductor structure includes a substrate, a bond pad over the substrate, and a passivation layer over the substrate and a peripheral region of the bond pad. The bond pad has a bonding region and the peripheral region surrounding the bonding region. The passivation layer has an opening defined therein, and the opening exposes the bonding region of the bond pad. A first vertical distance between an upper surface of the passivation layer and a surface of the bonding region ranges from 30% to 40% of a second vertical distance between a lower surface of the passivation layer and an upper surface of the peripheral region.

Abstract: A substrate structure includes a substrate body and a plurality of conductive pads formed on the substrate body and each having a first copper layer, a nickel layer, a second copper layer and a gold layer sequentially stacked. The thickness of the second copper layer is less than the thickness of the first copper layer. As such, the invention effectively enhances the bonding strength between the conductive pads and solder balls to be mounted later on the conductive pads, and prolongs the duration period of the substrate structure.

Abstract: A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring.

Abstract: A semiconductor device includes first pads having centers offset in a first direction, wherein the first pads are arranged in a second direction crossing the first direction; second pads separated in the first direction from the first pads and arranged in the second direction, wherein centers of the second pads are offset in the first direction; first gate lines coupled to the first pads, respectively; and second gate lines coupled to the second pads, respectively.

Abstract: Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.

Abstract: Embodiments of the present invention relate to a semiconductor chip comprising a plurality of contact pads, which are arranged in an edge area on a surface of the semiconductor chip. In a semiconductor area of the semiconductor chip, every contact pad of the plurality of contact pads has an associated pad cell provided, which includes at least one of a driver or a receiver and is configured to drive output signals or receive input signals on its associated contact pad, if the driver or receiver is connected to the contact pad. Additionally, for a contact pad which is used as a supply contact pad, the driver or receiver of the associated pad cell is not connected to the contact pad or any other contact pad for driving output signals or receiving input signals on the same.

Abstract: A process of cleaning wire bond pads associated with OLED devices, including the steps of depositing on the wire bond pads one or more layers of ablatable material, and ablating the one or more layers with a laser, thereby exposing a clean wire bond pad.