By Forming Silicide Of Refractory Metal (epo) Patents (Class 257/E21.593)
  • Patent number: 8962431
    Abstract: A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second metal over silicon. The first and second metals are of different compositions. The substrate is subjected to conditions which react the second metal with the silicon in the second stack to form metal silicide-comprising material from the second stack. The first metal between the second metal and the silicon in the first stack precludes formation of a silicide comprising the second metal and silicon from the first stack. After forming the metal silicide-comprising material, the first metal, the second metal and the metal silicide-comprising material are subjected to an etching chemistry that etches at least some remaining of the first and second metals from the substrate selectively relative to the metal silicide-comprising material.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, John Mark Meldrim, Rita J. Klein
  • Patent number: 8956968
    Abstract: A method for fabricating a metal silicide interconnect in a stacked 3D non-volatile memory array. A stack of alternating layers of undoped/lightly doped polysilicon and heavily doped polysilicon is formed on a substrate. Memory holes are etched in cell areas of the stack while an interconnect area is protected. Slits are etched in the cell areas and the interconnect areas. A wet etch is performed via the slits or the memory holes in the cell area to remove portions of the undoped/lightly doped polysilicon layers in the cell area, and dielectric is deposited. Silicidation transforms portions of the heavily doped polysilicon layers in the cell area to metal silicide, and transforms portions of the heavily doped and undoped/lightly doped polysilicon layers in the interconnect area to metal silicide. The metal silicide interconnect can be used for routing power and control signals from below the stack to above the stack.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: February 17, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Masaaki Higashitani, Peter Rabkin
  • Patent number: 8888916
    Abstract: Embodiments of the present invention provide apparatus and method for improving gas distribution during thermal processing. One embodiment of the present invention provides an apparatus for processing a substrate comprising a chamber body defining a processing volume, a substrate support disposed in the processing volume, wherein the substrate support is configured to support and rotate the substrate, a gas inlet assembly coupled to an inlet of the chamber body and configured to provide a first gas flow to the processing volume, and an exhaust assembly coupled to an outlet of the chamber body, wherein the gas inlet assembly and the exhaust assembly are disposed on opposite sides of the chamber body, and the exhaust assembly defines an exhaust volume configured to extend the processing volume.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 18, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Ming-Kuei (Michael) Tseng, Norman L. Tam, Yoshitaka Yokota, Agus S. Tjandra, Robert Navasca, Mehran Behdjat, Sundar Ramamurthy, Kedarnath Sangam, Alexander N. Lerner
  • Patent number: 8790969
    Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. Several devices are, thus, provided. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: July 29, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Mondo, Markus Gerhard Andreas Muller, Thomas Kormann
  • Patent number: 8728930
    Abstract: A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second metal over silicon. The first and second metals are of different compositions. The substrate is subjected to conditions which react the second metal with the silicon in the second stack to form metal silicide-comprising material from the second stack. The first metal between the second metal and the silicon in the first stack precludes formation of a silicide comprising the second metal and silicon from the first stack. After forming the metal silicide-comprising material, the first metal, the second metal and the metal silicide-comprising material are subjected to an etching chemistry that etches at least some remaining of the first and second metals from the substrate selectively relative to the metal silicide-comprising material.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, John Mark Meldrim, Rita J. Klein
  • Patent number: 8722534
    Abstract: A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate, forming a first transition metal layer in the recess on corner portions of the recess, and forming a second transition metal layer in the recess over the first transition metal layer to line the recess. The method further includes filling the recess with a fill layer and annealing the substrate so that the first transition metal layer and the second transition metal layer form an alloy portion proximate the corner portions during the annealing, the alloy portion having a reduced wettability for a material of the fill layer than the second transition metal. Additionally, the method includes polishing the substrate to remove portions of the fill layer extending above the recess.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: May 13, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Hoon Kim, Vivian W. Ryan
  • Patent number: 8673694
    Abstract: A thin film transistor array panel includes a passivation layer formed on a plurality of end portions of a plurality of gate lines. A portion of the passivation layer has a porous structure formed between a connection portion of a flexible printed circuit substrate and a thin film transistor substrate such that when the flexible printed circuit substrate and the thin film transistor array panel are connected to each other, the passivation layer having a porous structure and which is formed at the connection portion therebetween connects the flexible printed circuit substrate with the thin film transistor array panel thereby minimizing an exposed area of the metal of the connection portion to improve a corrosion resistance thereof.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: March 18, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun Park, Chun-Gi You
  • Patent number: 8642377
    Abstract: An embodiment of this invention provides a method to produce a conductive thin film, which comprises: providing a substrate; forming a first metal oxide layer on the substrate; forming an indium-free metal layer on the first metal oxide layer; and forming a second metal oxide layer on the indium-free layer, wherein the first metal oxide layer, the indium-free metal layer, and the second oxide layer are all solution processed.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: February 4, 2014
    Assignee: National Taiwan University
    Inventors: Ching-Fuh Lin, Ming-Shiun Lin
  • Patent number: 8617992
    Abstract: Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects. A metal ink may be printed for contacts as well as for local interconnects at the same time, or in the alternative, the printed metal can act as a seed for electroless deposition of other metals if different metals are desired for the contact and the interconnect lines. This approach advantageously reduces the number of processing steps and does not necessarily require any etching.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: December 31, 2013
    Assignee: Kovio, Inc.
    Inventors: Aditi Chandra, Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Mao Takashima, Erik Scher
  • Publication number: 20130334693
    Abstract: A method for forming a raised silicide contact, the method including depositing a layer of silicon using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° and holding the temperature for about 0.1 miliseconds to about 600 seconds in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.
    Type: Application
    Filed: June 18, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Emre Alptekin, Nathaniel Berliner, Christian Lavoie, Kam-Leung Lee, Ahmet Serkan Ozcan
  • Publication number: 20130273734
    Abstract: A method of manufacturing salicide layers includes the following steps. Firstly, a silicon substrate with a patterned stack structure of a silicon layer and a first cap layer sequentially formed thereon is provided. Then, a second cap layer is formed on the exposed silicon substrate. The materials of the first cap layer and the second cap layer are different. Then, the first cap layer is removed to expose the silicon layer. Then, a first metal layer is formed on the silicon layer and reacted with the silicon layer to produce a first salicide layer. Afterward, the second cap layer is removed, and a second metal layer is formed over the surface of the silicon substrate and reacted with the silicon substrate to produce a second salicide layer.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 17, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tse-Yi LU, Chih-Ming CHIEN, Li-Jen YAO
  • Patent number: 8481378
    Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake at a temperature lower or equal to 800° C., a subsequent deposition step will prevent deposition in the first surface region. This allows selective deposition in the second surface region, which is not doped with the Boron (or doped with another dopant or not doped). Several devices are, thus, provided. The method saves a usual photolithography sequence, which according to prior art is required for selective deposition of Si or SiGe in the second surface region.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: July 9, 2013
    Assignees: STMicroelectronics (Crolles 2) SAS, NXP B.V.
    Inventors: Alexandre Mondot, Markus Gerhard Andreas Muller, Thomas Kormann
  • Patent number: 8470707
    Abstract: A process for forming an integrated circuit with reduced sidewall spacers to enable improved silicide formation between minimum spaced transistor gates. A process for forming an integrated circuit with reduced sidewall spacers by first forming sidewall spacer by etching a sidewall dielectric and stopping on an etch stop layer, implanting source and drain dopants self aligned to the sidewall spacers, followed by removing a portion of the sidewall dielectric and removing the etch stop layer self aligned to the reduced sidewall spacers prior to forming silicide.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: June 25, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Weize Xiong, Deborah J. Riley
  • Patent number: 8461012
    Abstract: A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: June 11, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Vishal P. Trivedi
  • Patent number: 8450216
    Abstract: An exemplary structure for a field effect transistor according to at least one embodiment comprises a substrate comprising a surface; a gate structure comprising sidewalls and a top surface over the substrate; a spacer adjacent to the sidewalls of the gate structure; a first contact etch stop layer over the spacer and extending along the surface of the substrate; an interlayer dielectric layer adjacent to the first contact etch stop layer, wherein a top surface of the interlayer dielectric layer is coplanar with the top surface of the gate structure; and a second contact etch stop layer over the top surface of the gate structure.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: May 28, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lee-Wee Teo, Ming Zhu, Bao-Ru Young, Harry-Hak-Lay Chuang
  • Patent number: 8409985
    Abstract: The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten layer to fill the feature. Depositing the tungsten nucleation layer involves exposing the substrate to alternating pulses of a boron-containing reducing agent and a tungsten-containing precursor without using any hydrogen gas, e.g., as a carrier or background gas. Using this process, a conformal tungsten nucleation layer can be deposited to a thickness as small as about 10 Angstroms. The feature may then be wholly or partially filled with tungsten by a hydrogen reduction chemical vapor deposition process. Resistivities of about 14 ??-cm for a 500 Angstrom film may be obtained.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: April 2, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Lana Hiului Chan, Kaihan Ashtiani, Joshua Collins
  • Publication number: 20130005136
    Abstract: A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second metal over silicon. The first and second metals are of different compositions. The substrate is subjected to conditions which react the second metal with the silicon in the second stack to form metal silicide-comprising material from the second stack. The first metal between the second metal and the silicon in the first stack precludes formation of a silicide comprising the second metal and silicon from the first stack. After forming the metal silicide-comprising material, the first metal, the second metal and the metal silicide-comprising material are subjected to an etching chemistry that etches at least some remaining of the first and second metals from the substrate selectively relative to the metal silicide-comprising material.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Inventors: David H. Wells, John Mark Meldrim, Rita J. Klein
  • Patent number: 8334574
    Abstract: Semiconductor fabricating technology is provided, and particularly, a method of fabricating a semiconductor device improving a contact characteristic between a silicon layer including carbon and a metal layer during a process of fabricating a semiconductor device is provided. A semiconductor device including the silicon layer including carbon and the metal layer formed on the silicon layer is provided. A metal silicide layer is interposed between the silicon layer including carbon and the metal layer.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: December 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Sung Park, Se-Keun Park
  • Patent number: 8324058
    Abstract: A method for contacting an FET device is disclosed. The method includes vertically recessing the device isolation, which exposes a sidewall surface on both the source and the drain. Next, silicidation is performed, resulting in a silicide layer covering both the top surface and the sidewall surface of the source and the drain. Next, metallic contacts are applied in such manner that they engage the silicide layer on both its top and on its sidewall surface. A device characterized as being an FET device structure with enlarged contact areas is also disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide on its top surface and on its sidewall surface.
    Type: Grant
    Filed: November 6, 2010
    Date of Patent: December 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Keith Kwong Hon Wong, Ying Zhang
  • Patent number: 8278199
    Abstract: Reliability of a semiconductor element and its product yield are improved by reducing variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. After removing unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of each thermal treatment is set to 10° C./s or more.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shigenari Okada, Takuya Futase, Yutaka Inaba
  • Patent number: 8258626
    Abstract: A copper interconnection structure includes an insulating layer, an interconnection body including copper and a barrier layer surrounding the interconnection body. The barrier layer includes a first barrier layer formed between a first portion of the interconnection body and the insulating layer. The first portion of the interconnection body is part of the interconnection body that faces the insulating layer. The barrier layer also includes a second barrier layer formed on a second portion of the interconnection body. The second portion of the interconnection body is part of the interconnection body not facing the insulating layer. Each of the first and the second barrier layers is formed of an oxide layer including manganese, and each of the first and the second barrier layers has a position where the atomic concentration of manganese is maximized in their thickness direction of the first and the second barrier layers.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: September 4, 2012
    Assignee: Advanced Interconnect Materials, LLC
    Inventors: Junichi Koike, Akihiro Shibatomi
  • Patent number: 8237264
    Abstract: A method of manufacturing a semiconductor device has forming a ferroelectric film over a substrate, placing the substrate having the ferroelectric film in a chamber substantially held in vacuum, introducing oxygen and an inert gas into the chamber, annealing the ferroelectric film in the chamber, and containing oxygen and the inert gas while the chamber is maintained sealed.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: August 7, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • Patent number: 8187970
    Abstract: Methods for forming cobalt silicide materials are disclosed herein. In one example, a method for forming a cobalt silicide material includes exposing a substrate having a silicon-containing material to either a wet etch solution or a pre-clean plasma during a first step and then to a hydrogen plasma during a second step of a pre-clean process. The exemplary method further includes depositing a cobalt metal layer on the silicon-containing material by a CVD process, heating the substrate to form a first cobalt silicide layer comprising CoSi at the interface of the cobalt metal layer and the silicon-containing material during a first annealing process, removing any unreacted cobalt metal from the first cobalt silicide layer during an etch process, and heating the substrate to form a second cobalt silicide layer comprising CoSi2 during a second annealing process.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: May 29, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Seshadri Ganguli, Sang-Ho Yu, See-Eng Phan, Mei Chang, Amit Khandelwal, Hyoung-Chan Ha
  • Patent number: 8158518
    Abstract: Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. The method of forming contacts includes depositing an ink of a silicide-forming metal onto an exposed silicon surface, drying the ink to form a silicide-forming metal precursor, and heating the silicide-forming metal precursor and the silicon surface to form a metal silicide contact. Optionally, the metal precursor ink may be selectively deposited onto a dielectric layer adjacent to the exposed silicon surface to form a metal-containing interconnect. Furthermore, one or more bulk conductive metal(s) may be deposited on remaining metal precursor ink and/or the dielectric layer. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: April 17, 2012
    Assignee: Kovio, Inc.
    Inventors: Aditi Chandra, Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Mao Takashima, Erik Scher
  • Patent number: 8158483
    Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: April 17, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
  • Patent number: 8080452
    Abstract: The invention relates to a method for selective deposition of Si or SiGe on a Si or SiGe surface. The method exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: December 20, 2011
    Assignees: NXP, B.V., STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Mondot, Markus Gerhard Andreas Muller, Thomas Kormann
  • Patent number: 8076239
    Abstract: A method of manufacturing a semiconductor device, includes the steps of forming an insulating film on a semiconductor substrate having a silicide layer, forming a hole in the insulating film on the silicide layer, cleaning an inside of the hole and a surface of the silicide layer, forming a titanium layer on a bottom surface and an inner peripheral surface of the hole by a CVD method, forming a copper diffusion preventing barrier metal layer on the titanium layer in the hole, and burying a copper layer in the hole.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: December 13, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazuo Kawamura, Shinichi Akiyama, Satoshi Takesako
  • Patent number: 8056500
    Abstract: Embodiments of the present invention provide apparatus and method for improving gas distribution during thermal processing. One embodiment of the present invention provides an apparatus for processing a substrate comprising a chamber body defining a processing volume, a substrate support disposed in the processing volume, wherein the substrate support is configured to support and rotate the substrate, a gas inlet assembly coupled to an inlet of the chamber body and configured to provide a first gas flow to the processing volume, and an exhaust assembly coupled to an outlet of the chamber body, wherein the gas inlet assembly and the exhaust assembly are disposed on opposite sides of the chamber body, and the exhaust assembly defines an exhaust volume configured to extend the processing volume.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: November 15, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Ming-Kuei (Michael) Tseng, Norman Tam, Yoshitaka Yokota, Agus Tjandra, Robert Navasca, Mehran Behdjat, Sundar Ramamurthy, Kedarnath Sangam, Alexander N. Lerner
  • Patent number: 8053347
    Abstract: A method of manufacturing a semiconductor device, including forming a plurality of gate structures on a substrate, the gate structures each including a hard mask pattern stacked on a gate conductive pattern, forming an insulating layer pattern between the gate structures at least partially exposing a top surface of the hard mask pattern, forming a trench that exposes at least a top surface of the gate conductive pattern by selectively removing the hard mask pattern, and forming a silicide layer on the exposed gate conductive pattern.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Soo Kang, Byung-Kyu Cho, Choong-Ho Lee, Dong-Uk Choi
  • Patent number: 8053860
    Abstract: An excessive metallic film on a device isolation region is prevented from contributing to silicidation in an end of a source-drain diffusion layer region to thereby form a silicide film with uniform film thickness. There are sequentially conducted a step of forming a device isolation region 3 in a substrate 1 including a silicon layer at least in a surface thereof and filling a first insulator in the device isolation region 3, a step of making height of an upper surface of the first insulator less than height of an upper surface of the substrate 1 and forming a sidewall film 10 on a sidewall of the device isolation region 3, and a step of depositing a metallic film 11 on the substrate 1 and then conducting silicidation through a thermal process.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: November 8, 2011
    Assignee: NEC Corporation
    Inventor: Masayasu Tanaka
  • Patent number: 8039378
    Abstract: To provide a technique capable of improving the reliability of a semiconductor element and its product yield by reducing the variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate 1, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. Subsequently, after removing the unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of the first thermal treatment is set to 10° C./s or more (for example, 30 to 250° C.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: October 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shigenari Okada, Takuya Futase, Yutaka Inaba
  • Patent number: 8030210
    Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: October 4, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Ya Wang, Chung-Hu Ke, Wen-Chin Lee
  • Patent number: 8017506
    Abstract: A thin film transistor device reduced substantially in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of the silicon semiconductor with a metal and irradiating an intense light such as a laser beam to the metal film either from the upper side or from an insulator substrate side to allow the metal coating to react with silicon to obtain a silicide film. The metal silicide layer may be obtained otherwise by tightly adhering a metal coating to the exposed source and drain regions using an insulator formed into an approximately triangular shape, preferably 1 ?m or less in width, and allowing the metal to react with silicon.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: September 13, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiko Takemura, Hongyong Zhang, Satoshi Teramoto
  • Patent number: 7998858
    Abstract: The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: August 16, 2011
    Assignee: Infineon Technologies AG
    Inventors: Martin Gutsche, Franz Kreupl, Harald Seidl
  • Patent number: 7993987
    Abstract: A method includes providing a substrate including a non-insulative, silicon-including region for silicidation, the substrate including one or more contaminants at a top surface thereof. A getter layer is deposited over the non-insulative, silicon-including region, the getter layer reacting with at least one of the one or more contaminants in the non-insulative, silicon-including region at approximately room temperature. The getter layer is removed, and siliciding of the non-insulative, silicon-including region is performed.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: August 9, 2011
    Assignee: International Business Machines Corporation
    Inventors: Randolph F. Knarr, Christian Lavoie, Ahmet S. Ozcan, Filippos Papadatos
  • Patent number: 7955972
    Abstract: The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten layer to fill the feature. Depositing the tungsten nucleation layer involves exposing the substrate to alternating pulses of a boron-containing reducing agent and a tungsten-containing precursor without using any hydrogen gas, e.g., as a carrier or background gas. Using this process, a conformal tungsten nucleation layer can be deposited to a thickness as small as about 10 Angstroms. The feature may then be wholly or partially filled with tungsten by a hydrogen reduction chemical vapor deposition process. Resistivities of about 14 ??-cm for a 500 Angstrom film may be obtained.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: June 7, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Lana Hiului Chan, Kaihan Ashtiani, Joshua Collins
  • Patent number: 7928008
    Abstract: A fabricating method of a polysilicon layer is disclosed which can be applied for fabricating a semiconductor device such as a SRAM and so on. The method for fabricating the semiconductor device includes the steps of: forming a transistor included in the semiconductor device on a semi conductor substrate forming an insulating layer on the transistor; forming contact holes, through which a region of the transistor is exposed, by selectively removing the insulating layer forming a silicon layer in the contact holes forming a metal layer on the insulating layer and the silicon layer; forming a metal suicide layer through heat treatment of the silicon layer and the metal layer; removing the metal layer; forming an amorphous silicon layer on the insulating layer and the metal suicide layer; and forming a polysilicon layer through heat treatment of the amorphous silicon layer.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: April 19, 2011
    Assignee: Terasemicon Corporation
    Inventors: Taek-Yong Jang, Byung-Il Lee, Young-Ho Lee, Seok-Pil Jang
  • Patent number: 7902056
    Abstract: Devices and methods for plasma treated metal silicide layer formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a metal layer on a silicon substrate, exposing the metal layer to a plasma, and thermally treating the silicon substrate and the metal layer to form a metal silicide layer.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: March 8, 2011
    Assignee: Spansion LLC
    Inventors: Takayuki Enda, Tatsuya Inoue, Naoki Takeguchi
  • Patent number: 7897414
    Abstract: A method of manufacturing a semiconductor device has forming a ferroelectric film over a substrate, placing the substrate having the ferroelectric film in a chamber substantially held in vacuum, introducing oxygen and an inert gas into the chamber, annealing the ferroelectric film in the chamber, and containing oxygen and the inert gas while the chamber is maintained sealed.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: March 1, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • Patent number: 7830010
    Abstract: Interconnect structures in which a noble metal-containing cap layer is present directly on a non-recessed surface of a conductive material which is embedded within a low k dielectric material are provided. It has been determined that by forming a hydrophobic surface on a low k dielectric material prior to metal cap formation provides a means for controlling the selective formation of the metal cap directly on the non-recessed surface of a conductive material. That is, the selective formation of the metal cap directly on the non-recessed surface of a conductive material is enhanced since the formation rate of the metal cap on the non-recessed surface of a conductive material is greater than on the hydrophobic surface of the low k dielectric material.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: November 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Satya V. Nitta, Sampath Purushothaman, Muthumanickam Sankarapandian
  • Patent number: 7829430
    Abstract: Devices and methods are presented to fabricate dummy moats in an isolation region on a substrate. Presently, dummy moats are prone to losing impedance after the silicidation process. In high-voltage devices, silicided dummy moats reduce the breakdown voltage between active regions, particularly when the dummy moat overlaps or is in close proximity to a junction. The present devices and methods disclose a dummy moat covered with an oxide layer. During the silicidation process, the dummy moat and other designated isolation regions remain non-silicided. Thus, high and stable breakdown voltages are maintained.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: November 9, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Pendharker, Binghua Hu
  • Patent number: 7811928
    Abstract: Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device includes a silicon substrate, a source region and a drain region. A gate electrode is formed on the silicon substrate. Also, a metal silicide layer is formed on each of the gate electrode, the source region, and the drain region. The metal silicide layer has a thickness uniformity of about 1˜20%. A disclosed fabrication method includes forming a metal layer on a silicon substrate having a gate electrode, a source region, and a drain region; performing a plasma treatment on the metal layer; forming a protective layer on the metal layer; and heat treating the silicon substrate on which the protective layer is formed to thereby form a metal silicide layer. A gas that includes nitrogen is used as a plasma gas during the plasma treatment.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: October 12, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventors: Han-Choon Lee, Jin-Woo Park
  • Patent number: 7803707
    Abstract: The present invention provides metal silicide nanowires, including metallic, semiconducting, and ferromagnetic semiconducting transition metal silicide nanowires. The nanowires are grown using either chemical vapor deposition (CVD) or chemical vapor transport (CVT) on silicon substrates covered with a thin silicon oxide film, the oxide film desirably having a thickness of no greater than about 5 nm and, desirably, no more than about 2 nm (e.g., about 1-2 nm). The metal silicide nanowires and heterostructures made from the nanowires are well-suited for use in CMOS compatible wire-like electronic, photonic, and spintronic devices.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: September 28, 2010
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Song Jin, Andrew L. Schmitt, Yipu Song
  • Patent number: 7799628
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: September 21, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Hsiang-Yi Wang, Cheng-Tung Lin, Chen-Hua Yu
  • Patent number: 7795100
    Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: September 14, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Hedeyuki Kojima, Toru Anezaki
  • Patent number: 7786004
    Abstract: A method of manufacturing a semiconductor device includes forming a first conductive film on a semiconductor substrate via a first insulating film; forming a second conductive film on the first conductive film via a second insulating film; patterning the first and the second conductive films and the second insulating film to form a plurality of gate electrodes; filling a third insulating film between the plurality of gate electrodes; exposing an upper portion of the second conductive film by removing the third insulating film; covering surfaces of the exposed upper portion of the second conductive film with fluoride (F) or carbon (C) or oxygen (O); and forming a metal film on an upper surface of the second conductive film; and forming silicide layers on the upper portion of the second conductive films by thermally treating the metal film.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: August 31, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Jota Fukuhara
  • Patent number: 7749898
    Abstract: A method for forming an interconnect structure includes forming a dielectric layer above a first layer having a conductive region defined therein. An opening is defined in the dielectric layer to expose at least a portion of the conductive region. A metal silicide is formed in the opening to define the interconnect structure. A semiconductor device includes a first layer having a conductive region defined therein, a dielectric layer formed above the first layer, and a metal silicide interconnect structure extending through the dielectric layer to communicate with the conductive region.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: July 6, 2010
    Assignee: Globalfoundries Inc.
    Inventors: Paul R. Besser, Christian Lavoie, Cyril Cabral, Jr., Stephen M. Rossnagel, Kenneth P. Rodbell
  • Patent number: 7750471
    Abstract: Methods and apparatus relating to a single silicon wafer having metal and alloy silicides are described. In one embodiment, two different silicides may be provided on the same wafer. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: July 6, 2010
    Assignee: Intel Corporation
    Inventor: Pushkar Ranade
  • Publication number: 20100167528
    Abstract: A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide. The unreacted layer of metal is removed with the composite structure remaining as the local interconnect.
    Type: Application
    Filed: March 10, 2010
    Publication date: July 1, 2010
    Inventor: Jigish D. Trivedi
  • Patent number: 7745334
    Abstract: By performing sophisticated anneal techniques, such as laser anneal, flash anneal and the like, for a metal silicide formation, such as nickel silicide, the risk of nickel silicide defects in sensitive device regions, such as SRAM pass gates, may be significantly reduced. Also, the activation of dopants may be performed in a highly localized manner, so that undue damage of gate insulation layers may be avoided when activating and re-crystallizing drain and source regions.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: June 29, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Patrick Press, Karla Romero, Martin Trentzsch, Karsten Wieczorek, Thomas Feudel, Markus Lenski, Rolf Stephan