Abstract: The present disclosure provides a semiconductor device, a semiconductor assembly and method of manufacturing the semiconductor assembly. The semiconductor device includes a substrate, a conductive feature in the substrate, an isolation liner between the substrate and the conductive feature, and a main component in the substrate. The conductive feature includes first to third blocks. The first block has a uniform first critical dimension, wherein the main component is disposed around the first block. The second block has a uniform second critical dimension greater than the first critical dimension. The third block is interposed between the first block and the second block and has varying third critical dimensions.

Abstract: A substrate processing method for area selective deposition includes providing a substrate containing a first film, a second film, and a third film, forming a first blocking layer on the first film, forming a second blocking layer on the second film, where the second blocking layer is different from the first blocking layer, and selectively forming a material film on the third film. In one example, the first film contains a metal film, second film contains a metal-containing liner that surrounds the metal film, and the third film includes a dielectric film that surrounds the metal-containing liner.

Abstract: The present disclosure provides a semiconductor device, a semiconductor assembly and method of manufacturing the semiconductor assembly. The semiconductor device includes a substrate, a conductive feature in the substrate, an isolation liner between the substrate and the conductive feature, and a main component in the substrate. The conductive feature includes first to third blocks. The first block has a uniform first critical dimension, wherein the main component is disposed around the first block. The second block has a uniform second critical dimension greater than the first critical dimension. The third block is interposed between the first block and the second block and has varying third critical dimensions.

Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a transistor including a source contact, a drain contact, and a channel region including an oxide semiconductor material as the channel material. At least one of the drain contact or the source contact includes a conductive material, such as ruthenium, to reduce the Schottky effects at the interface with the channel material.

Abstract: Provided are embodiments for an MOL interconnect structure having low metal-to-metal interface resistance interconnect structure including one or more contacts of one or more devices formed on a substrate. A dielectric layer is formed on one or more devices. One or more trenches are formed in the dielectric layer. The MOL interconnect structure also includes a barrier layer formed on one or more portions of the dielectric layer, along with a metallization layer, wherein the metallization layer forms a metal-to-metal interface with the one or more contacts.

Abstract: A method includes forming a first metal into a first trench in a dielectric layer, performing a thermal treatment to the first metal such that an average grain size of the first metal is increased, and performing a first chemical mechanical polish (CMP) process to the first metal after the performing the thermal treatment.

Abstract: A method includes: forming a first conductive structure in a first dielectric layer; forming a conductive protection structure that is coupled to at least part of the first conductive structure; forming a second dielectric layer over the first dielectric layer; forming a via hole extending through at least part of the second dielectric layer to expose a portion of the conductive protection structure; cleaning the via hole; and refilling the via hole with a conductive material to form a via structure.

Abstract: Metallic layers can be selectively deposited on surfaces of a substrate relative to a second surface of the substrate. In preferred embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In preferred embodiments, a first precursor forms a layer or adsorbed species on the first surface and is subsequently reacted or converted to form a metallic layer. Preferably the deposition temperature is selected such that a selectivity of above about 90% is achieved.

Abstract: An antifuse one-time programmable (OTP) semiconductor memory comprises a PN junction diode formed in an active area of a semiconductor substrate proximate metal-oxide-semiconductor (MOS) capacitor wherein MOS gate conductor and MOS channel region are of the same conductivity type. A vertical bipolar junction transistor (BJT) is present in each cell, comprising said PN junction diode and a semiconductor layer below said PN junction diode. In a programmed cell, BJT emitter, base and collector are connected to the bit line, word line and common collector terminal, respectively. In an unprogrammed cell, BJT is an open-base BJT.

Abstract: An interconnect structure and method of making the same. A preferred interconnect structure has a first interconnect including a first dual damascene via and narrow line and a second interconnect at the same level as the first including a second dual damascene via and wider line. The first and second interconnects may have different aspect ratio and may have different line heights while being co-planar with each other. The second line of the second interconnect may abut or partially surround the first line of the first interconnect. The first interconnect includes a refractory metal material as the main conductor, whereas the second interconnect includes a lower resistivity material as its main conductor.

Abstract: A Cu wiring forming method of forming Cu wiring that is to be arranged in contact with tungsten wiring, by filling Cu into a recess formed in a substrate, includes: removing a tungsten oxide formed on a surface of the tungsten wiring; forming a nitriding preventing film at least on the surface of the tungsten wiring in the recess; forming a barrier film that prevents diffusion of Cu, on a surface in the recess from above the nitriding preventing film; forming a liner film on the barrier film; and filling a Cu film on the liner film.

Abstract: A method of fabricating ESD suppression device includes forming conductive pillars dispersed in a dielectric material. The gaps formed between each pillar in the device behave like spark gaps when a high voltage ESD pulse occurs. When the voltage of the pulse reaches the “trigger voltage” these gaps spark over, creating a very low resistance path. In normal operation, the leakage current and the capacitance is very low, due to the physical gaps between the conductive pillars. The proposed method for fabricating an ESD suppression device includes micromachining techniques to be on-chip with device ICs.

Abstract: A semiconductor device includes a plurality of conductive layers and a plurality of insulating layers formed alternately with each other, at least one channel layer passing through the plurality of conductive layers and the plurality of insulating layers, and at least one first charge blocking layer surrounding the at least one channel layer, wherein a plurality of first regions, interposed between the at least one channel layer and the plurality of conductive layers, and a plurality of second regions, interposed between the at least one channel layer and the plurality of insulating layers, are alternately defined on the at least one first charge blocking layer, and each of the plurality of first regions has a greater thickness than each of the plurality of second regions.

Abstract: Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the graphene and non-graphene regions may be nested within one another. In some embodiments an electrically insulative material may be over an upper surface of the laminate structure, and an opening may extend through the insulative material to a portion of the laminate structure. Electrically conductive material may be within the opening and in electrical contact with at least one of the non-graphene regions of the laminate structure. Some embodiments include methods of forming electrical interconnects in which non-graphene material and graphene are alternately formed within a trench to form nested non-graphene and graphene regions.

Abstract: In a semiconductor integrated circuit device including fuse elements for performing laser trimming processing, a dummy fuse formed of a first polycrystalline Si film is formed between the fuse elements formed of a second polycrystalline Si film, and a nitride film is formed on the dummy fuse. In this manner, the step difference of an interlayer film caused by the presence and absence of the fuse element formed of the polycrystalline Si film is eliminated, to thereby prevent SOG films having moisture-absorption characteristics on an inner surface of a fuse opening region and on an internal element side from connecting to each other.

Abstract: Provided is a production method for a semiconductor device comprising a metal silicide layer. According to one embodiment of the present invention, the production method for a semiconductor device comprises the steps of: forming an insulating layer on a substrate, on which a polysilicon pattern has been formed, in such a way that the polysilicon pattern is exposed; forming a silicon seed layer on the exposed polysilicon pattern that has been selectively exposed with respect to the insulating layer; forming a metal layer on the substrate on which the silicon seed layer has been formed; and forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed.

Abstract: A method for forming a pattern according to an embodiment, includes forming above a first film film patterns of a second film; forming film patterns of the first film by etching the first film using the film patterns of the second film as a mask; converting the film patterns of the second film into film patterns whose width are narrower than the film patterns of the first film by performing a slimming process; forming film patterns of a third film on both sidewalls of the film patterns of the first film and the film patterns of the second film after the slimming process; and etching the first film using the film patterns of the third film as a mask after the film patterns of the second film being removed.

Abstract: A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the first metal film, a layer containing Ti and Si is formed on the surface of the conductor.

Abstract: A semiconductor component including a first layer (10) of a semiconductor material as a substrate, a second layer (12) running on said first layer (10), and at least two intermediate layers (14, 16) made of the materials of the first and second layers running between the first and second layer, where the first intermediate layer (16) facing the second layer (12) may contain a eutectic mixture (18) made of the materials of the first and second layers. The invention is also directed to an electroconductive contact (15, 15a, 15b) forming an electroconductive connection to the first layer and originating at or running through the second layer, as well as to a method for producing the metal-semiconductor contact.

Abstract: A method and structure of a non-intrinsic anti-fuse structure. The anti-fuse structure has a first electrode, a second electrode, a first dielectric, and second dielectric. The first and second dielectrics have an interface which couples electrodes. The length along the interface which couples the electrodes is called the predetermined length. When the anti-fuse is programmed a conductive link forms along the interface to connect the first and second electrodes. The anti-fuse structure can be single-level or dual-level. The predetermined length can be less than spacing between adjacent electrodes when a dual-level structure is used. The anti-fuse structures have the advantage that they can be programmed at lower voltages than intrinsic structures and no extra steps are needed to integrate the anti-fuses with active structures.

Abstract: Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.

Abstract: A method for fabricating a device includes forming a silicide layer on a substrate, forming a conductive layer over exposed portions of the substrate and the silicide layer, patterning and removing exposed portions of the conductive layer and the silicide layer with a first process, and patterning and removing exposed portions of the conductive layer with a second process.

Abstract: The function of logic cells may be changed by altering their metal routing. Logic cells altered in this manner may be used to correct, substitute, or otherwise alter the operation of logic blocks or scan paths without completely re-working an integrated circuit. The process may be referred to as an engineering change order (ECO) process. According to an exemplary process a buffer may be reconfigured to operate as a NAND gate, a NOR gate, or an INVERTER, for example, and may be configured to operate in a circuit in need of such a logic function.

Abstract: A method of fabricating ESD suppression device includes forming conductive pillars dispersed in a dielectric material. The gaps formed between each pillar in the device behave like spark gaps when a high voltage ESD pulse occurs. When the voltage of the pulse reaches the “trigger voltage” these gaps spark over, creating a very low resistance path. In normal operation, the leakage current and the capacitance is very low, due to the physical gaps between the conductive pillars. The proposed method for fabricating an ESD suppression device includes micromachining techniques to be on-chip with device ICs.

Abstract: Methods are disclosed for forming an antifuse that includes first and second conductive regions having spaced-apart curved portions, with a first dielectric region therebetween, forming in combination with the curved portions a curved breakdown region adapted to switch from a substantially non-conductive initial state to a substantially conductive final state in response to a predetermined programming voltage. A sense voltage less than the programming voltage is used to determine the state of the antifuse as either OFF (high impedance) or ON (low impedance). A shallow trench isolation (STI) region is desirably provided adjacent the breakdown region to inhibit heat loss from the breakdown region during programming. Lower programming voltages and currents are observed compared to antifuses using substantially planar dielectric regions. In a further embodiment, a resistive region is inserted in one lead of the antifuse with either planar or curved breakdown regions to improve post-programming sense reliability.

Abstract: A method for forming a functional element includes a first step of forming an insulating layer composed of an insulator phase of a transition metal oxide serving as a metal-to-insulator transition material, the transition metal oxide being mainly composed of vanadium dioxide, and a second step of causing part of the insulating layer to transition to a metallic phase, in which the insulator phase differs from the metallic phase in terms of electrical resistivity and/or light transmittance.

Abstract: Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.

Abstract: A method for controlling the electrical conduction between two electrically conductive portions may include placing of an at least partially ionic crystal between the two electrically conductive portions. The crystal may include at least one surface region coupled to the two electrically conductive portions. The surface region is insulating under the application of an electrical field to the surface region, and electrically conductive in the absence of the electrical field. An application or not of an electrical field to the at least one surface region reduces or establishes the electrical conduction.

Abstract: A method for manufacturing an electronic device is disclosed. A design description of the electronic device is generated using one or more computer aided design tools. Physical device data are generated that represent a physical description of the electronic device, which includes data determining connection points for connecting the electronic device to one or more external circuits. A physical embodiment of the electronic device is produced in accordance with the physical device data. Physical test member data is determined that represents conductors and contact points of a test member for testing the electronic device. The test member is produced in accordance with the test member data. The electronic device is tested with the test member.

Abstract: It is an object of the present invention to provide an organic transistor having a low drive voltage. It is also another object of the present invention to provide an organic transistor, in which light emission can be obtained, which can be manufactured simply and easily. According to an organic light-emitting transistor, a composite layer containing an organic compound having a hole-transporting property and a metal oxide is used as part of the electrode that injects holes among source and drain electrodes, and a composite layer containing an organic compound having an electron-transporting property and an alkaline metal or an alkaline earth metal is used as part of the electrode that injects electrons, where either composite layer has a structure of being in contact with an organic semiconductor layer.

Abstract: Embodiments of the present invention provide a semiconductor device that includes a transistor device having a first, a second, and a third node; and an interconnect structure having at least one wire and the wire having a first and a second end with the first end of the wire being connected to one of the first, the second, and the third node of the transistor device. The wire is conductive and adapted to provide an operating current in a first direction during a normal operating mode, and adapted to provide a repairing current in a second direction opposite to the first direction during a repair mode of the semiconductor device. In one embodiment the transistor device is a bipolar transistor with the first, second, and third nodes being an emitter, a base, and a collector of the bipolar transistor. The wire is connected to one of the emitter and the collector. Method of operating the semiconductor device and current supplying circuit for the semiconductor device are also disclosed.

Abstract: An antifuse is provided having a unitary monocrystalline semiconductor body including first and second semiconductor regions each having the same first conductivity type, and a third semiconductor region between the first and second semiconductor regions which has a second conductivity type opposite from the first conductivity type. An anode and a cathode can be electrically connected with the first semiconductor region. A conductive region including a metal, a conductive compound of a metal or an alloy of a metal can contact the first semiconductor region and extend between the cathode and the anode. The antifuse can further include a contact electrically connected with the second semiconductor region.

Abstract: Methods are disclosed for forming an antifuse that includes first and second conductive regions having spaced-apart curved portions, with a first dielectric region therebetween, forming in combination with the curved portions a curved breakdown region adapted to switch from a substantially non-conductive initial state to a substantially conductive final state in response to a predetermined programming voltage. A sense voltage less than the programming voltage is used to determine the state of the antifuse as either OFF (high impedance) or ON (low impedance). A shallow trench isolation (STI) region is desirably provided adjacent the breakdown region to inhibit heat loss from the breakdown region during programming. Lower programming voltages and currents are observed compared to antifuses using substantially planar dielectric regions. In a further embodiment, a resistive region is inserted in one lead of the antifuse with either planar or curved breakdown regions to improve post-programming sense reliability.

Abstract: A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines.

Abstract: Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.

Abstract: Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided.

Abstract: A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate; a wiring formed in predetermined pattern above the semiconductor substrate, a first insulating film lying right under the wiring, and a second insulating film lying in a peripheral portion other than a portion right under the wiring, in which a surface layer of the first insulating film lying in a boundary surface between the first insulating film and the second insulating film is chemically modified to reinforce the surface layer.

Abstract: A semiconductor device manufacturing method includes forming an interlayer dielectric film above a semiconductor substrate; forming a first wiring trench with a first width and a second wiring trench with a second width that is larger than the first width inr the interlayer dielectric film; forming a first seed layer that includes a first additional element in the first wiring trench and the second wiring trench; forming a first copper layer over the first seed layer; removing the first copper layer and the first seed layer in the second wiring trench while leaving the first copper layer and the first seed layer in the first wiring trench; forming a second seed layer in the second wiring trench after removing the first copper layer and the first seed layer in the second wiring trench; and forming a second copper layer over the second seed layer.

Abstract: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.

Abstract: A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.

Abstract: Trench anti-fuse structures, design structures embodied in a machine readable medium for designing, manufacturing, or testing a programmable integrated circuit. The anti-fuse structure includes a trench having a plurality of sidewalls that extend into a substrate, a doped region in the semiconductor material of the substrate proximate to the sidewalls of the trench, a conductive plug in the trench, and a dielectric layer on the sidewalls of the trench. The dielectric layer is disposed between the conductive plug and the doped region. The dielectric layer is configured so that a programming voltage applied between the doped region and the conductive plug causes a breakdown of the dielectric layer within a region of the trench. The trench sidewalls are arranged with a cross-sectional geometrical shape that is independent of position between a bottom wall of the deep trench and a top surface of the substrate.

Abstract: An interconnect structure with improved reliability is provided. The interconnect structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metallic wiring in the dielectric layer; a pre-layer over the metallic wiring, wherein the pre-layer contains boron; and a metal cap over the pre-layer, wherein the metal cap contains tungsten, and wherein the pre-layer and the metal cap are formed of different materials.

Abstract: A method of forming metal wirings of a nonvolatile memory device include forming a first insulating layer over a semiconductor substrate including a first junction area and a second junction area, forming first and second contact holes through which the first and second junction areas are respectively exposed in the first insulating layer, forming first and second contact plugs within the first and second contact holes, etching a part of the second contact plug, thus forming a recess, forming a second insulating layer to fill the recess, forming a third insulating layer over the semiconductor substrate including the first and second insulating layers, forming a first trench through which the first contact plug is exposed a second trench through which the second contact plug is exposed by etching the third insulating layer, and forming first and second metal wirings within the first and second trenches, respectively.

Abstract: A two-step semiconductor electroplating process deposits copper onto wafers coated with a semi-noble metal in manner that is uniform across the wafer and free of voids after a post electrofill anneal. A seed-layer plating bath nucleates copper uniformly and conformably at a high density in a very thin film using a unique pulsed waveform. The wafer is then annealed before a second bath fills the features. The seed-layer anneal improves adhesion and stability of the semi-noble to copper interface, and the resulting copper interconnect stays void-free after a post electrofill anneal.

Abstract: A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO2 film provided on the silicon substrate, copper films embedded in the SiO2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO2 film, and SiON films covering an upper face of the TiN films.

Abstract: Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.

Abstract: A method forms an anti-fuse structure comprises a plurality of parallel conductive fins positioned on a substrate, each of the fins has a first end and a second end. A second electrical conductor is electrically connected to the second end of the fins. An insulator covers the first end of the fins and a first electrical conductor is positioned on the insulator. The first electrical conductor is electrically insulated from the first end of the fins by the insulator. The insulator is formed to a thickness sufficient to break down on the application of a predetermined voltage between the second electrical conductor and the first electrical conductor and thereby form an uninterrupted electrical connection between the second electrical conductor and the first electrical conductor through the fins.

Abstract: An electronic device includes a plurality of stacked substrates. Each of the substrates includes a semiconductor substrate, a columnar conductor, and a ring-shaped insulator. The columnar conductor extends along a thickness direction of the semiconductor substrate. The ring-shaped insulator includes an inorganic insulating layer mainly composed of a glass. The inorganic insulating layer fills a ring-shaped groove that is provided in the semiconductor substrate to surround the columnar conductor.

Abstract: An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.