Formed Through Semiconductor Substrate (epo) Patents (Class 257/E21.597)
  • Patent number: 10381443
    Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Hiroyuki Ogawa, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
  • Patent number: 10283710
    Abstract: A method of forming a resistive memory device includes forming an alternating stack of insulating layers and sacrificial material layers that extend along a first horizontal direction over a substrate, forming a laterally alternating sequence of vertical conductive lines and dielectric pillar structures that alternate along the first horizontal direction on sidewalls of the alternating stack, forming lateral recesses by removing the sacrificial material layers selective to the insulating layers, selectively growing resistive memory material portions from physically exposed surfaces of the vertical conductive lines in the lateral recesses, and forming electrically conductive layers over the resistive memory material portions in the lateral recesses.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: May 7, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shin Kikuchi, Seje Takaki
  • Patent number: 10276528
    Abstract: A semiconductor device and a manufacturing method for the semiconductor device are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump a spacer and surrounds the bump and disposed between the etching stop layer and the bump.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Yu Ku, Cheng-Lung Yang, Chen-Shien Chen, Hon-Lin Huang, Chao-Yi Wang, Ching-Hui Chen, Chien-Hung Kuo
  • Patent number: 10163956
    Abstract: An apparatus comprises a first semiconductor chip including a first substrate, a plurality of first inter-metal dielectric layers and a plurality of first metal lines, a second semiconductor chip having a surface in contact with a surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second inter-metal dielectric layers and a plurality of second metal lines and a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion over a first side of a hard mask layer and a second portion over a second side of the hard mask layer, wherein the hard mask layer is a ring-shaped layer, and wherein the conductive plug is formed in a center opening of the ring-shaped layer.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Shih Pei Chou, Min-Feng Kao, Szu-Ying Chen
  • Patent number: 10155660
    Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ping Chun Yeh, Lien-Yao Tsai, Shao-Chi Yu
  • Patent number: 10147682
    Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) having a back-side through-silicon-via (BTSV) with a direct physical connection between a metal interconnect layer and a back-side conductive bond pad. The IC has metal interconnect layers arranged within an inter-level dielectric structure disposed onto a front-side of a substrate. A dielectric layer is arranged along a back-side of the substrate, and a conductive bond pad is arranged over the dielectric layer. A BTSV extends from one of the metal interconnect layers through the substrate and the dielectric layer to the conductive bond pad. A conductive bump is arranged onto the conductive bond pad, which has a substantially planar lower surface extending from over the BTSV to below the conductive bump. Directly connecting the conductive bond pad to the BTSV reduces a size of the conductive bond thereby improving a routing capability of the conductive bond pad.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: December 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang
  • Patent number: 10147751
    Abstract: A method of image sensor package fabrication includes providing an image sensor, including a pixel array disposed in a semiconductor material, and a transparent shield adhered to the semiconductor material. The pixel array is disposed between the semiconductor material and the transparent shield. The method further includes removing portions of the transparent shield to form recessed regions in the transparent shield, where lateral bounds of the transparent shield extend beyond lateral bounds of the pixel array, and wherein the recessed regions are disposed in portions of the transparent shield that extend beyond the lateral bounds of the pixel array. The recessed regions are filled with a light blocking layer.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: December 4, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chia-Chun Miao, Yin Qian, Chao-Hung Lin, Chen-Wei Lu, Dyson H. Tai, Ming Zhang, Jin Li
  • Patent number: 10083982
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 25, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Keisuke Shigemura, Junichi Ariyoshi, Masanori Tsutsumi, Michiaki Sano, Yanli Zhang, Raghuveer S. Makala
  • Patent number: 10000376
    Abstract: A component is produced by creating a first layer composite that includes a first electrically conductive substrate and having a trench filled with an insulating material by creating a second layer composite that includes the first layer composite and a structure layer. The structure layer includes an active structure and is electrically conductive at least in a first region that adjoins a first surface of the first substrate and includes in the first region of the first substrate a first electrically conductive contact face on a second surface of the first substrate, which is located opposite the first surface. The first region of the first substrate is electrically insulated laterally from other regions of the first substrate by the trench.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: June 19, 2018
    Assignee: Northrop Grumman LITEF GmbH
    Inventor: Wolfram Geiger
  • Patent number: 9978804
    Abstract: A method of manufacturing an electronic device, comprising fixing a first wafer on a second wafer to form a space theirbetween, via a surrounding member configured to surround the space, forming an opening on a bottom side of the first wafer to expose a conductive member included in the first wafer, and then forming an electrode connected to the conductive member, wherein, in the fixing, the first wafer includes a trench intersecting the surrounding member, on an upper side of the first surface, and, in the forming, the electrode is formed under a condition that the space communicates with an external space via the trench.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 22, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hidemasa Oshige, Nobutaka Ukigaya
  • Patent number: 9972641
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each memory stack structure includes a memory film and a vertical semiconductor channel. An isolation trench laterally extends along a horizontal direction and divides at least two topmost electrically conductive layers. Two conductive rail structures are located on lengthwise sidewalls of the isolation trench and are electrically shorted to respective segments of the at least two topmost electrically conductive layers.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: May 15, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Jin Liu, Raghuveer S. Makala, Murshed Chowdhury, Johann Alsmeier
  • Patent number: 9878900
    Abstract: A manufacturing method for a micromechanical sensor device and a corresponding micromechanical sensor device. The method includes providing a substrate including at least one first through a fourth parallel trenches; depositing a layer onto the front side, the trenches being sealed, and structuring the layer, contact structures being formed in the layer above the second and fourth trenches; oxidizing of outwardly free-standing side surfaces of the contact structures as well as of the second and fourth trenches, at least in areas; depositing and structuring a first metallic contacting material, the contact structures being filled with the first metallic contacting material, at least in areas; opening the second trench and the fourth trench; galvanic deposition of a second metallic contacting material into the second and fourth trenches, resulting in the formation of a pressure-sensitive capacitive capacitor structure; and opening the first trench from the front side of the substrate.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: January 30, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventor: Zhenyu Wu
  • Patent number: 9859363
    Abstract: A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: January 2, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhenyu Lu, Kota Funayama, Chun-Ming Wang, Jixin Yu, Chenche Huang, Tong Zhang, Daxin Mao, Johann Alsmeier, Makoto Yoshida, Lauren Matsumoto
  • Patent number: 9817928
    Abstract: Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: November 14, 2017
    Assignee: SYNOPSYS, INC.
    Inventors: Jamil Kawa, Victor Moroz
  • Patent number: 9807917
    Abstract: The invention specifies an electronic component which has a first electrode (10), a second electrode (20), an active region (30), which is electrically coupled to the first electrode (10) and to the second electrode (20), and a housing (100), wherein the housing (100) contains carbon layers which are monoatomic at least in subregions.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: October 31, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Gudrun Henn
  • Patent number: 9773768
    Abstract: A method includes placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer. The first composite wafer is bonded to a second wafer, and the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding. The method further includes de-bonding the first carrier from the first plurality of device dies, encapsulating the first plurality of device dies in an encapsulating material, and forming an interconnect structure over the first plurality of device dies and the encapsulating material.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Yung-Chi Lin
  • Patent number: 9761509
    Abstract: A method for is used for forming a semiconductor device having a through-substrate via. The method includes providing a preliminary structure having an ILD layer on a substrate and a buffer layer on the ILD layer; forming an opening through the buffer layer, the ILD layer, and the substrate; forming a liner structure layer over the substrate, wherein an exposed surface of the opening is covered by the liner structure layer; depositing a conductive material over the substrate to fill the opening; performing a polishing process, to polish over the substrate and stop at the buffer layer, wherein the liner structure layer and the conductive material remaining in the opening form a conductive via; performing an etching back process, to remove the buffer layer and expose the ILD layer, wherein a top portion of the conductive via is also exposed and higher than the ILD layer.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: September 12, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Kuei-Sheng Wu, Ming-Tse Lin
  • Patent number: 9666522
    Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hsien Huang, Hsien-Wei Chen, Ching-Wen Hsiao, Der-Chyang Yeh, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 9648741
    Abstract: An electronic device includes; a first substrate; a second substrate Located facing the first substrate; a resin layer formed between the first substrate and the second substrate and having a first thermal expansion coefficient; a conductor via penetrating the first substrate and the resin layer; a barrier film covering a side surface of the conductor via; a first film formed between the resin layer and the barrier film and having viscoelasticity; and a second film formed between the first film and the barrier film and having a second thermal expansion coefficient lower than the first thermal expansion coefficient.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: May 9, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Yoriko Mizushima
  • Patent number: 9640580
    Abstract: An image sensor package includes a die having an active side surface and a backside surface opposite to each other and having a bonding pad disposed on the active side surface, a through via penetrating the die and being electrically connected to the bonding pad, and a first dielectric layer disposed between the through via and the die. The first dielectric layer extends to cover the backside surface of the die. A redistribution line is disposed on the first dielectric layer and is electrically connected to the through via. The redistribution line extends onto the first dielectric layer on the backside surface of the die. A second dielectric layer is disposed on the first dielectric layer to cover the redistribution line and to extend onto an outer sidewall of the die. Related methods are also provided.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: May 2, 2017
    Assignee: SK HYNIX INC.
    Inventors: Seung Hyun Lee, Na Yeon Kim
  • Patent number: 9595472
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device comprises forming a first pattern and a second pattern to be placed apart on a semiconductor substrate; and forming an arch pattern in which the tops of the first pattern and of the second pattern touch by making the first pattern and the second pattern bend in directions in which they face each other.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: March 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuya Ohtsuki, Takashi Ohashi
  • Patent number: 9570390
    Abstract: The semiconductor device comprises a substrate of semiconductor material, a dielectric layer on the substrate, an electrically conductive contact pad arranged in the dielectric layer, a hot plate arranged in the dielectric layer, a recess of the substrate at the location of the hot plate, and an integrated circuit, which operates the hot plate. An electrically conductive layer is arranged on a side of the substrate opposite the dielectric layer. The substrate is provided with a via hole above the contact pad, and an electrically conductive material connecting the electrically conductive layer with the contact pad is applied in the via hole. The recess and the via hole are formed in the same process step.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: February 14, 2017
    Assignee: AMS AG
    Inventors: Franz Schrank, Martin Schrems
  • Patent number: 9559041
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer if formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: January 31, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masamichi Ishihara
  • Patent number: 9548313
    Abstract: A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first material and second material layers over the select gate layer, where the first material, the second material and the third material are different from each other, and etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such that the select gate layer acts as an etch stop layer during the step of etching.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: January 17, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shinsuke Yada, Shigehiro Fujino, Hajime Kimura, Masanori Terahara, Ryoichi Honma, Hiroyuki Ogawa, Ryousuke Itou
  • Patent number: 9543229
    Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: January 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
  • Patent number: 9536809
    Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.
    Type: Grant
    Filed: August 30, 2015
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
  • Patent number: 9530726
    Abstract: A semiconductor device includes a via structure having a top surface with a planar portion and a protrusion portion that is surrounded by the planar portion, and includes a conductive structure including a plurality of conductive lines contacting at least a part of the top surface of the via structure.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: December 27, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-jin Moon, Byung-Iyul Park, Dong-chan Lim, Deok-young Jung, Gil-heyun Choi, Dae-lok Bae, Pil-kyu Kang
  • Patent number: 9484227
    Abstract: A method includes placing a first device die and a second device die over a carrier, with a scribe line between the first device die and the second device die. The first device die and the second device die are encapsulated with an encapsulating material, which has a portion in the scribe line. The method further includes forming a dielectric layer over the encapsulating material, performing a first die-saw to form a first trench in the scribe line, performing a second die-saw to form a second trench in the scribe line, and performing a third die-saw on the scribe line to separate the first device die from the second device die.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: November 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Shen Cheng, An-Jhih Su, Chung-Shi Liu, Hsiu-Jen Lin, Hsien-Wei Chen, Ming-Da Cheng, Wei-Yu Chen
  • Patent number: 9397038
    Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114?) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: July 19, 2016
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Charles G. Woychik, Arkalgud R. Sitaram, Hong Shen, Zhuowen Sun, Liang Wang, Guilian Gao
  • Patent number: 9349699
    Abstract: A method of forming an integrated circuit structure is provided. The method includes providing a substrate, the substrate having a conductive pad thereon. A dielectric buffer layer is formed over at least a portion of the conductive pad, and an under-bump-metallurgy (UBM) is formed directly coupled to the conductive pad, wherein the UBM extends over at least a portion of the dielectric buffer layer. Thereafter, a conductive pillar is formed over the UBM, and one or more conductive materials are formed over the conductive pillar. The substrate may be attached to a carrier substrate using an adhesive.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hon-Lin Huang, Ching-Wen Hsiao, Kuo-Ching Hsu, Chen-Shien Chen
  • Patent number: 9006866
    Abstract: A semiconductor device and a method for fabricating the same are disclosed, which can prevent migration of copper (Cu) ion when forming a Through Silicon Via (TSV). The semiconductor device includes a through silicon via (TSV) formed to pass through a semiconductor substrate; an oxide film located at a lower sidewall of the TSV; and a first prevention film formed to cover an upper portion of the TSV, an upper sidewall of the TSV, and an upper surface of the oxide film.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: April 14, 2015
    Assignee: SK Hynix Inc.
    Inventor: Dong Ryeol Lee
  • Patent number: 8993432
    Abstract: A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yun Hou, Wei-Cheng Wu, Hsien-Pin Hu, Jung Cheng Ko, Shin-Puu Jeng, Chen-Hua Yu, Kim Hong Chen
  • Patent number: 8987851
    Abstract: The invention provides a radio-frequency (RF) device package and a method for fabricating the same. An exemplary embodiment of a radio-frequency (RF) device package includes a base, wherein a radio-frequency (RF) device chip is mounted on the base. The RF device chip includes a semiconductor substrate having a front side and a back side. A radio-frequency (RF) component is disposed on the front side of the semiconductor substrate. An interconnect structure is disposed on the RF component, wherein the interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure. A through hole is formed through the semiconductor substrate from the back side of the semiconductor substrate, and is connected to the interconnect structure. A TSV structure is disposed in the through hole.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: March 24, 2015
    Assignee: MediaTek Inc.
    Inventors: Ming-Tzong Yang, Cheng-Chou Hung, Tung-Hsing Lee, Wei-Che Huang, Yu-Hua Huang
  • Patent number: 8980746
    Abstract: To achieve the foregoing and in accordance with the purpose of the present invention, a method for forming copper filled through silicon via features in a silicon wafer is provided. Through silicon vias are etched in the wafer. An insulation layer is formed within the through silicon vias. A barrier layer is formed within the through silicon vias. An oxide free silicon, germanium, or SiGe adhesion layer is deposited over the barrier layer. A seed layer is deposited over the adhesion layer then the wafers is annealed. The features are filled with copper or copper alloy. The stack is annealed.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: March 17, 2015
    Assignee: Lam Research Corporation
    Inventor: Artur Kolics
  • Patent number: 8980670
    Abstract: An electromechanical transducer includes multiple elements each including at least one cellular structure, the cellular structure including: a semiconductor substrate, a semiconductor diaphragm, and a supporting portion for supporting the diaphragm so that a gap is formed between one surface of the substrate and the diaphragm. The elements are separated from one another at separating locations of a semiconductor film including the diaphragm. Each of the elements includes in a through hole passing through a first insulating layer including the supporting portion and the semiconductor substrate: a conductor which is connected to the semiconductor film including the diaphragm; and a second insulating layer for insulating the conductor from the semiconductor substrate.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: March 17, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazutoshi Torashima, Takahiro Akiyama
  • Patent number: 8975153
    Abstract: A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Hong-Seng Shue, Kun-Ming Huang, Tzu-Cheng Chen, Ming-Che Yang, Po-Tao Chu
  • Patent number: 8975729
    Abstract: A semiconductor wafer has an integrated through substrate via (TSV). The semiconductor wafer includes a substrate. A dielectric layer may be formed on a first side of the substrate. A through substrate via may extend through the dielectric layer and the substrate. The through substrate via may include a conductive material and an isolation layer. The isolation layer may at least partially surround the conductive material. The isolation layer may have a tapered portion.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 10, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Vidhya Ramachandran, Shiqun Gu
  • Patent number: 8969171
    Abstract: A method for forming a semiconductor device includes providing a semiconductor-on-insulator (SOI) structure, and forming at least one hard mask (HM) layer over the SOI structure. The SOI structure includes an insulator layer and a semiconductor layer over the insulator layer. The method further comprises forming a trench inside the at least one HM layer and the semiconductor layer, and depositing a spacer layer in the trench. The spacer layer comprises a bottom surface portion over the bottom surface of the trench, and a side wall portion along the side wall of the trench. The method further comprises etching the bottom surface portion of the spacer layer while the side wall portion of the spacer layer remains, and etching the insulator layer to extend the trench into the insulator layer.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Tai Tseng, Chung-Yen Chou, Chia-Shiung Tsai
  • Patent number: 8962480
    Abstract: A method includes forming an ESD active device on a substrate, forming a ground plane on a backside of the substrate and forming at least one through wafer via electrically connected to a negative power supply of the ESD active device and the ground plane to provide a low series resistance path to the substrate.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Patent number: 8963292
    Abstract: Present embodiments relate to a semiconductor device having a backside redistribution layer and a method for forming such a layer. Specifically, one embodiment includes providing a substrate comprising a via formed therein. The substrate has a front side and a backside. The embodiment may further include forming a trench on the backside of the substrate, disposing an insulating material in the trench, and forming a trace over the insulating material in the trench.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Steve Oliver, Warren Farnworth
  • Patent number: 8957504
    Abstract: An integrated structure with a silicon-through via includes a substrate, a through-silicon via penetrating the substrate, a conductive protective structure surrounding the through-silicon via and a first and a second conductive dummy patterns with different shapes disposed between the through-silicon via and the conductive protective structure.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 17, 2015
    Assignee: IP Enval Consultant Inc.
    Inventors: Huang Chao-Yuan, Ho Yueh-Feng, Yang Ming-Sheng, Chen Hwi-Huang
  • Patent number: 8956974
    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stop layer and a dielectric liner including dielectric material along sidewalls of openings, e.g., through-substrate openings, of the semiconductor device and excess dielectric material outside the openings. The method further includes forming a metal layer including metal plugs within the openings and excess metal. The excess metal and the excess dielectric material are simultaneously chemically-mechanically removed using a slurry including ceria and ammonium persulfate. The slurry is selected to cause selectivity for removing the excess dielectric material relative to the stop layer greater than about 5:1 as well as selectivity for removing the excess dielectric material relative to the excess metal from about 0.5:1 to about 1.5:1.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Wayne H. Huang, Anurag Jindal
  • Patent number: 8951916
    Abstract: A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: February 10, 2015
    Assignee: Tela Innovations, Inc.
    Inventor: Michael C. Smayling
  • Patent number: 8952499
    Abstract: An integrated circuit is provided with a substrate, an electrode, two diffusion areas, and a resistance heater. The substrate includes a first surface and second surface that are substantially parallel to each other. The electrode is laminated onto the first surface. The two diffusion areas are disposed within the substrate in the vicinity of the electrode to form one transistor with the electrode. The resistance heater is located on an area of the second surface across the substrate from the electrode. The resistance heater produces heat by allowing electric current to flow.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: February 10, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takashi Morimoto, Takashi Hashimoto
  • Patent number: 8940636
    Abstract: A semiconductor package includes a semiconductor wafer having a plurality of semiconductor die. A contact pad is formed over and electrically connected to an active surface of the semiconductor die. A gap is formed between the semiconductor die. An insulating material is deposited in the gap between the semiconductor die. An adhesive layer is formed over a surface of the semiconductor die and the insulating material. A via is formed in the insulating material and the adhesive layer. A conductive material is deposited in the via to form a through hole via (THV). A conductive layer is formed over the contact pad and the THV to electrically connect the contact pad and the THV. The plurality of semiconductor die is singulated. The insulating material can include an organic material. The active surface of the semiconductor die can include an optical device.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: January 27, 2015
    Assignee: STATS ChipPAC, Ltc.
    Inventors: Reza A. Pagaila, Zigmund R. Camacho, Lionel Chien Hui Tay, Byung Tai Do
  • Patent number: 8940637
    Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: January 27, 2015
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Lup San Leong, Zheng Zou, Alex Kai Hung See, Hai Cong, Xuesong Rao, Yun Ling Tan, Huang Liu
  • Patent number: 8927427
    Abstract: A method including introducing a dopant into a region of a substrate, etching a deep trench in the substrate through the region, gettering impurities introduced during etching of the deep trench using a pentavalent ion formed from a reaction between an element of the substrate and the dopant, wherein the charge of the pentavalent ion attracts the impurities, and filling the deep trench with a conductive material.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Troy L. Graves-Abe, Brian J. Greene, Chandrasekharan Kothandaraman
  • Patent number: 8921984
    Abstract: In a connecting portion between an interconnection and a first bump which is a part of a through electrode penetrating a semiconductor chip and which penetrates a semiconductor substrate, a protruding portion protruding from the interconnection to the side of the first bump is provided. The protruding portion may be made of an insulating material and may be made of a conductive material.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: December 30, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Koji Torii, Nobuyuki Nakamura
  • Patent number: 8916979
    Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang
  • Patent number: 8912047
    Abstract: A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: December 16, 2014
    Assignee: Infineon Technologies AG
    Inventors: Khalil Hosseini, Hans-Joachim Schulze