Abstract: Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.

Abstract: A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC.

Abstract: Embodiments of the present invention are directed to provide a semiconductor device including a semiconductor chip formed of a conductive material, a connector terminal around the semiconductor chip, which is formed of a same material for forming the semiconductor chip, an insulating member for electrically insulating the semiconductor chip from the connector terminal, and a first connection member for electrically coupling the semiconductor chip with the connector terminal. Simplified step of manufacturing the connector terminal may further simplify the steps of manufacturing the semiconductor device.

Abstract: Embodiments relate to a passivation fabricating method. In the passivation fabricating method according to embodiments, a first oxide film may be formed by repeating deposition and etching of an oxide film on a silicon substrate in which an upper metal pad may be formed and a second oxide film may be formed by performing only deposition on the first oxide film. A thickness of the first oxide film may be set to be above 5 k?. A first passivation layer may be formed by planarizing the first and second oxide films. In the planarizing process, a thickness of the first passivation layer may be 4 k?. A second passivation layer of a nitride film may be formed on the first passivation layer and the first and second passivations may be selectively etched so as to expose the upper metal pad.

Abstract: A method for simultaneous formation of a self-aligned contact of a core region and a local interconnect of a peripheral region of an integrated circuit includes etching a cap dielectric layer to simultaneously form a hole in the core region and a trench in the peripheral region of the cap dielectric layer, etching a dielectric layer to simultaneously form a hole in the core region and a trench in the peripheral region of the dielectric layer of the dielectric layer, etching a liner layer simultaneously on a shoulder of sidewall spacers associated with the hole and with the trench of the dielectric layer without etching the liner layer at a bottom area of the hole and the trench, performing an oxygen flushing to remove polymer residues, and etching simultaneously through the liner layer that lines the bottom area of the hole and the trench.

Abstract: Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etching for the conductive layer after employing the photoresist layer pattern as a mask, thereby forming a wiring pattern, partially removing the photoresist layer pattern through secondary dry etching, thereby forming a passivation layer on a surface of the wiring pattern, performing tertiary dry etching for the wiring pattern and a diffusion barrier after employing the photoresist layer pattern as a mask, thereby forming a metal wiring, and removing the photoresist layer pattern.

Abstract: A semiconductor device includes a circuit block formed in a peripheral edge portion of a semiconductor chip, a circuit block pad formed on the circuit block providing an electrical connection for said circuit block, and a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and electrically connected to a lead frame by a bonding wire, the laterally offset bonding pad thereby functioning as a substitute wire bonding pad for the circuit block.

Abstract: A semiconductor integrated circuit device including: a semiconductor substrate on which a circuit is formed; a plurality of functional device arrays stacked on the semiconductor substrate; and vertical wirings so disposed outside of the functional device arrays as to couple the signal lines of the functional device arrays to the circuit, wherein the vertical wirings include multi-layered metal pieces, each layer of which has a plurality of the metal pieces dispersedly arranged in a stripe-shaped contact trench formed on an interlayer insulating film in the elongated direction.

Abstract: A method of manufacturing a semiconductor device has forming a capacitor having electrodes and a ferroelectric film provided therebetween above a substrate, forming a pad electrode electrically connected to one of the electrodes of the capacitor above the substrate, forming a protective film covering the pad electrode over the substrate, forming an opening in the protective film exposing at least a part of the pad electrode, bringing a measurement terminal into contact with the exposed surface of the pad electrode, etching the surface of the pad electrode after the measurement terminal is brought into contact therewith, and forming a hydrogen absorbing film on the protective film and the pad electrode exposed through the opening.

Abstract: The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region and connects the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first conductive interconnect structure cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof. The conductive interconnect preferably comprises doped polysilicon and can be formed by processing steps including photolithographic patterning, etching, and polysilicon deposition.

Abstract: A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of the protective film. On the metal film, a metal bump is formed. The metal film is formed to have a two-layer structure of the first and second metal films. Materials of the lower and upper layers are selected mainly in consideration of adhesion to the protective film and adhesion to the metal bump, respectively. Film formation conditions thereof are set to provide metal films with a desired quality and thickness. Thus, penetration of moisture from the pad or the periphery into a ferroelectric capacitor can be prevented and therefore, occurrence of potential inversion abnormalities due to penetrated moisture can be effectively suppressed.

Abstract: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.

Abstract: A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

Abstract: The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections.

Abstract: A semiconductor substrate, an interwiring insulating film formed on the semiconductor substrate, a first protective film formed on the interwiring insulating film having an opening and a pad metal formed on the opening are provided. A groove is formed in a portion corresponding to a peripheral portion of the pad metal, and the groove is covered with the pad metal. Thus, without decreasing bonding properties, insulation between pads can be maintained as well as cracks in a protective film around pads can be prevented.

Abstract: An electrical bonding pad for an integrated circuit, comprising an encapsulation layer for receiving electrical signals and for covering a portion of a stack of conductive layers. The pad further comprises a conductive area in the stack, with the conductive area being at least partially covered by the encapsulation layer. The conductive area is intended for the passage of electrical signals received by the encapsulation layer and traveling towards a circuit core, and is electrically insulated from the encapsulation layer in a manner that at least partially decouples the electrical signals received from the encapsulation layer.

Abstract: A metal layer is formed on an upper surface of a resin layer provided to cover a plurality of semiconductor chips at a side on which an internal connecting terminal is disposed and the internal connecting terminal, and the metal layer is pressed to cause the metal layer in a corresponding portion to a wiring pattern to come in contact with the internal connecting terminal, and to then bond the metal layer in a portion provided in contact with the internal connecting terminal to the internal connecting terminal in a portion provided in contact with the metal layer.

Abstract: A semiconductor device includes a first power supply which is disposed in a first direction, a first pad array which is disposed in the first direction, adjacent to the first power supply line, a second power supply line extending in the first direction, a first buffer circuit which is disposed between pads included in the first pad array, a second pad array which is disposed in the first direction, a third power supply line extending along the second pad array such that the second pad array is interposed between the second power supply line and the third power supply line, and a second buffer circuit which is disposed between pads included in the second pad array, and which is operated by a voltage between the second and third power supply lines.

Abstract: A chip structure including a chip, a first dielectric layer and at least one first conductive layer is provided. The chip has an active surface, a backside and at least one bonding pad disposed on the active surface. The first dielectric layer is disposed on the active surface and has at least one first opening, wherein the first opening correspondingly exposes the bonding pad. The first conductive layer covers an inner wall of the first opening and the bonding pad so as to form a concave structure in the first opening. When the chip structure is bonded to a substrate, the solder bump of the substrate is inlaid into the concave structure of the chip. Moreover, a fabrication process of the chip structure, a flip chip package structure and a fabrication process thereof, a package structure of a light emitting/receiving device and a chip stacked structure are also provided.

Abstract: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Abstract: A silicon interposer producing method comprising the steps of forming through holes 12 in a silicon wafer 11, forming an oxide coating 13 on the silicon wafer 11, providing a power feeding layer 14 for plating on one of the surfaces of the through holes 12, supplying a low thermal expansion filler 15 having a thermal expansion coefficient lower than the thermal expansion coefficient of the conductive material 16 of through-hole electrodes 17 to the through holes 12, filling the conductive material 16 into the through holes 12 by plating to form the through-hole electrodes 17, and removing the power feeding layer 14 for plating.

Abstract: A method for forming a semiconductor device with a bonding pad is disclosed. A first substrate having a device area and a bonding area is provided, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are formed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is formed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is formed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad. An opening through the first substrate is formed to expose the lowermost metal pattern.

Abstract: The present invention provides a manufacturing method for forming an integrated circuit device and to a corresponding integrated circuit device. The manufacturing method for forming an integrated circuit device comprises the steps of: forming a first level on a substrate; forming a second level above the first level; forming a cap layer on the second level which covers a first region of the level and leaves a second region uncovered; and simultaneously etching a first contact hole in the first region and a second contact hole in the second region such that the etching is selective to the cap layer in the second region and proceeds to a greater depth in the first region.

Abstract: A bonding pad includes an insulation layer with a trench, and a conductive pattern one portion of which is buried into the trench and the other portion of which is formed in a plate shape over the insulation layer.

Abstract: A method for making an interconnect is provided. The method includes depositing a conductive layer on a substrate, depositing a protective layer on the conductive layer, patterning the protective layer to form openings to the conductive layer, depositing contact pads on the conductive layer through the openings in the protective layer, the contact pads comprising a conductive material, and patterning the conductive layer and the protective layer to form electrical traces on the substrate.

Abstract: A manufacturing method of an electronic component package, includes: forming electrode pads on a main surface of a first electronic component; forming first bonding wires shaped in loop so as to be electrically connected with the electrode pads and elongated upward from the electrode pads and such that both ends of the first bonding wires are on the electrode pad, respectively; forming a resin layer over the main surface of the first electronic component so as to embed the first bonding wires; removing the resin layer so as to expose ends of the first bonding wires from the resin layer and removing the end of each of the first bonding wires so that two wires are elongated from on each of the electrode pads; and forming a metallic layer on the surface of the resin layer after removing so that the first bonding wires are electrically connected with the metallic layer.

Abstract: A local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local interconnection layer and the active region on an insulation film of a semiconductor substrate. Methods of forming the local interconnection wire can include forming a first etching mask pattern that has a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with an insulation film. The etching mask simultaneously has a length the same as or shorter than the length between outer ends of the gate electrodes. The insulation film exposed in the first etching mask pattern is subsequently etched so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a recess pattern.

Abstract: Low volume production of electronic devices having ball attachments, e.g. solder ball arrays, is advantageously achieved using a specific method. In particular a stencil having holes in, for example, the ball grid array pattern is formed by laser ablation of the holes in materials such as paper and polymers. The stencil holes are aligned with corresponding pads on the electronic device. Balls such as solder balls are introduced into the holes and heated to induce adhesion of the balls to the corresponding pads.

Abstract: A method of manufacturing an interconnect substrate by electroless plating, including: (a) forming a catalyst layer with a specific pattern on a substrate; (b) immersing the substrate in a first electroless plating solution including a first metal to deposit the first metal on the catalyst layer to form a first metal layer; and (c) immersing the substrate in a second electroless plating solution including a second metal to deposit the second metal on the first metal layer to form a second metal layer, an ionization tendency of the first metal being higher than an ionization tendency of the second metal.

Abstract: A method of assembling a microelectronic flip-chip arrangement includes attaching a chip having a defined length to a supporting substrate, wherein the chip forms a chip shadow line of the defined length on the supporting substrate, creating a first non-wettable zone on an outer portion of the bottom surface of the chip, creating a second non-wettable zone on a portion of the supporting substrate outside the chip shadow line, underfilling the chip and forming a fillet, wherein the fillet does not extend beyond the chip shadow line, and hardening the underfill including the fillet.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor device having a bonding pad and an interlayer insulating layer disposed on the semiconductor device. The interlayer insulating layer has an opening which exposes the bonding pad and has at least one cavity therein. A redistributed interconnection is disposed on the interlayer insulating layer and electrically connected to the exposed bonding pad. The redistributed interconnection is disposed over the cavity. A method of fabricating the semiconductor package is also provided.

Abstract: A method for fabricating a polysilicon silicon liquid crystal display device is disclosed in which a contact hole connecting source and drain electrodes to an active layer is formed without a stepped portion. An insulation layer containing a porous silicon nitride layer is formed. Wet etching the contact hole through the porous silicon nitride layer and an underlying silicon oxide layer does not generate the stepped portion as the etch rates of the porous silicon nitride layer and the silicon oxide layer are the same. Because the stepped portion is not generated at a contact hole, disconnection of source and drain electrodes formed in the contact hole is prevented, thereby preventing deterioration of the liquid crystal display device from occurring.

Abstract: A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.

Abstract: Methods, systems, and apparatuses for semiconductor wafers and integrated circuit chip packaging techniques are provided. A wafer is fabricated that supports multiple different packaging techniques. The wafer is formed to have a plurality of integrated circuit regions. A first plurality of terminals is formed on a surface of the wafer in a central region of each integrated circuit region. A second plurality of terminals is formed on the surface of the wafer in a peripheral region of each integrated circuit region. For each integrated circuit region, each terminal of the second plurality of terminals is electrically coupled through the wafer to at least one terminal of the first plurality of terminals. The integrated circuit regions can be separated into chips that can be packaged in multiple ways. In an aspect, a wafer may be fabricated that supports wire-bond packaging or wafer level ball grid array (WLBGA) packaging for a common chip/die configuration of the wafer.

Abstract: A semiconductor device includes conductive lines on a substrate, sidewall spacers on sidewalls of the conductive lines, contacts between the conductive lines, the contacts separated from the conductive lines by the sidewall spacers and electrically connected to active regions of the substrate, contact pads on and electrically connected to corresponding contacts, protection patterns contacting side surfaces of the contact pads, the protection patterns being disposed between the contact pads in a first direction crossing the conductive lines, and storage nodes on and electrically connected to corresponding contact pads.

Abstract: An adhesive film is formed on an electrode film, and a coating film is formed thereon. Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them is used as a constituent material of the adhesive film. Gold, silver, platinum or an alloy of them is used as a constituent material of the coating film.

Abstract: Methods of forming interconnect structures include forming a first metal wiring pattern on a first dielectric layer and forming a capping layer (e.g., SiCN layer) on the first copper wiring pattern. An adhesion layer is deposited on the capping layer, using a first source gas containing octamethylcyclotetrasilane (OMCTS) at a volumetric flow rate in a range from about 500 sccm to about 700 sccm and a second gas containing helium at a volumetric flow rate in a range from about 1000 to about 3000 sccm. The goal of the deposition step is to achieve an adhesion layer having an internal compressive stress of greater than about 150 MPa therein, so that the adhesion layer is less susceptible to etching/cleaning damage and moisture absorption during back-end processing steps. Additional dielectric and metal layers are then deposited on the adhesion layer.

Abstract: Disclosed is a liquid crystal display device having a signal line of low electrical resistivity and high adhesion with an underlayer, wherein a copper alloy film is formed on an underlayer, and an oxide film, silicide film or nitride film, which are additive metal elements of the copper alloy, is formed at the boundary between the underlayer and the copper alloy film whereby the signal line is formed with a multi-layer film of the copper alloy film and the oxide film, the silicide film, or the nitride film.

Abstract: A semiconductor device has: a circuit portion having semiconductor elements formed on a semiconductor substrate; insulating lamination formed above the semiconductor substrate and covering the circuit portion; a multilevel wiring structure formed in the insulating lamination and including wiring patterns and via conductors; and a pad electrode structure formed above the semiconductor substrate and connected to the multilevel wiring structure. The pad electrode structure includes pad wiring patterns and pad via conductors interconnecting the pad wiring patterns, the uppermost pad wiring pattern includes a pad pattern and a sealing pattern surrounding the pad pattern in a loop shape. Another pad wiring pattern has continuous extended pad pattern of a size overlapping the sealing pattern. The pad via conductors include a plurality of columnar via conductors disposed in register with the pad pattern and a loop-shaped wall portion disposed in register with the sealing pattern.

Abstract: A semiconductor package and a method of fabricating the same. The method includes providing a semiconductor substrate on which a chip pad is formed. A wire redistribution layer connected to the chip pad is formed. An insulating layer which includes an opening exposing a portion of the wire redistribution layer is formed. A metal ink is applied within the opening to thereby form a bonding pad. The applied metal ink within the opening and the insulating layer can be cured simultaneously.

Abstract: A semiconductor device formed in a semiconductor substrate for dissipating electrostatic discharge and/or accumulated charge in an integrated circuit is provided. In one embodiment, the device comprises a semiconductor substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal lines and wherein the via plugs interconnect the metal lines; and a dummy pad formed over the plurality of layers of metal lines, the dummy pad having a diode connected thereto and to ground for providing a discharge path for the electrostatic discharge and/or accumulated charge.

Abstract: A silicide layer (first silicide layer, second silicide layer) is laminated on top laminate surfaces of gates of a transmission transistor and a reset transistor, respectively. Each of the first silicide layer and the second silicide layer respectively formed on each of the gates extends in a direction along the main surface of the semiconductor substrate among at least a portion of a plurality of image pixels, connecting gates with one another among the respective image pixels. On the other hand, a signal outputter is not in contact with any silicide layers, has the top laminate surface that is covered with an insulating layer, and is connected with other transistors via a metal wiring layer.

Abstract: A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first interlayer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

Abstract: A circuit substrate for attachment to an integrated circuit chip comprises an electrical trace, a mounting pad and a dielectric layer. The mounting pad has a first surface, one or more sidewalls and a second surface. The first surface is attached to the electrical trace. The dielectric layer substantially covers the one or more sidewalls of the mounting pad and has an uppermost surface that is substantially coplanar with the second surface of the mounting pad.

Abstract: In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.

Abstract: The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a nitride, boride, carbide, or oxide comprising layer is atomic layer deposited onto the exposed elemental silicon containing surface to a thickness no greater than 15 Angstroms. Such layer is exposed to plasma and a conductive reaction layer including at least one of an elemental metal or metal rich silicide is deposited onto the plasma exposed layer. Metal of the conductive reaction layer is reacted with elemental silicon of the substrate effective to form a conductive metal silicide comprising contact region electrically connecting the conductive reaction layer with the substrate. Other aspects and implementations are contemplated.

Abstract: A method for forming interconnects onto attachment points of a wafer includes the steps of providing a mold with a plurality of cavities having a predetermined shape, depositing a release agent on surfaces of the cavities, filling the cavities with an interconnect material to form the interconnects, removing the release agent from the mold, and attaching the interconnects to the attachment points of the wafer. An adhesive layer can optionally be deposited in addition to the release layer. The adhesive layer can be used, for example, to bond the chip to a package.

Abstract: A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.

Abstract: A method is provided for forming wafer level package that incorporates dual compliant layers and a metal cap layer on top of I/O pads. The wafer level package includes a plurality of metal cap layers formed on top of a plurality of I/O pads to function as stress buffering and avoiding sharp corners in metal traces formed on top of the metal cap layers. A first compliant layer and a second compliant layer are formed under the metal trace to provide the necessary standoff and to accommodate differences in coefficients of thermal expansion of the various materials on an IC die. The wafer level package is particularly suitable for copper devices or in devices wherein copper lines are used.

Abstract: Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds.