Bump Or Ball Contacts (epo) Patents (Class 257/E23.021)
  • Patent number: 10679866
    Abstract: A semiconductor package includes a carrier, at least and adhesive portion, a plurality of micro pins and a die. The carrier has a first surface and second surface opposite to the first surface. The adhesive portion is disposed on the first surface, and the plurality of the micro pins is disposed in the adhesive portions. The die is disposed on the remaining adhesive portion free of the micro pins.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling Hwang, Bor-Ping Jang, Chung-Shi Liu, Hsin-Hung Liao, Ying-Jui Huang
  • Patent number: 10651267
    Abstract: There is provided a production method of a capacitor structure, having the following steps: forming a bottom electrode on a substrate; forming a sacrificial layer, which covers at least one part of the bottom electrode, on the substrate; forming a top electrode, which traverses the bottom electrode and covers at least one part of the sacrificial layer, on the substrate, such that a sacrificial layer is present at a part where an orthographic projection of the top electrode on the substrate and an orthographic projection of the bottom electrode on the substrate overlap; removing the sacrificial layer with a sacrificial layer removing solution to form an air gap. There are also provided a capacitor structure and a sensor.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: May 12, 2020
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Youting Zhang, Weijie Ma, Ming Zhang, Shichao Fei, Haifeng Hu, Jun Chen
  • Patent number: 10416192
    Abstract: Embodiments disclosed herein are directed to compliant probe structures for making temporary or permanent contact with electronic circuits and the like. In particular, embodiments are directed to various designs of cantilever-like probe structures. Some embodiments are directed to methods for fabricating such probe or cantilever structures. In some embodiments, for example, cantilever probes have extended base structures, slide in mounting structures, multi-beam configurations, offset bonding locations to allow closer positioning of adjacent probes, compliant elements with tensional configurations, improved over travel, improved compliance, improved scrubbing capability, and/or the like.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: September 17, 2019
    Assignee: Microfabrica Inc.
    Inventors: Richard T. Chen, Ezekiel J. J. Kruglick, Christopher A. Bang, Dennis R. Smalley, Pavel B. Lembrikov
  • Patent number: 10354965
    Abstract: The present disclosure describes an bonding pad formation method that incorporates an tantalum (Ta) conductive layer to block mobile ionic charges generated during the aluminum-copper (AlCu) metal fill deposition. For example, the method includes forming one or more interconnect layers over a substrate and forming a dielectric over a top interconnect layer of the one or more interconnect layers. A first recess is formed in the dielectric to expose a line or a via from the top interconnect layer. A conductive layer is formed in the first recess to form a second recess that is smaller than the first recess. A barrier metal layer is formed in the second recess to form a third recess that is smaller than the second recess. A metal is formed to fill the third recess.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih Wei Bih, Chun-Chih Lin, Sheng-Wei Yeh, Yen-Yu Chen, Chih-Wei Lin, Wen-Hao Cheng
  • Patent number: 10121871
    Abstract: A semiconductor device according to the present invention includes: a semiconductor layer including a first conductivity type semiconductor region and a second conductivity type semiconductor region joined to the first conductivity type semiconductor region; and a surface electrode connected to the second conductivity type region on one surface of the semiconductor layer, including a first Al-based electrode, a second Al-based electrode, a barrier metal interposed between the first Al-based electrode and the second Al-based electrode, and a plated layer on the second Al-based electrode.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: November 6, 2018
    Assignees: ROHM CO., LTD., LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Akihiro Hikasa, Kazusuke Kato
  • Patent number: 10031179
    Abstract: A testing method including the following steps is provided. A lead frame is provided, wherein the lead frame includes a frame body and a plurality of lead frame units which are connected with each other through the frame body and are arranged in array. Each of the lead frame units includes at least one first pin connected with the frame body and a plurality of second pins which are connected with each other. A plurality of controllers are bonded with the lead frame units and each of the controllers is electrically connected with the corresponding lead frame unit. The frame body of each of the lead frame units is electrically isolated from the second pins. A first electrical testing is performed to each of the lead frame units carrying the controllers.
    Type: Grant
    Filed: December 27, 2015
    Date of Patent: July 24, 2018
    Assignee: INGENII TECHNOLOGIES CORPORATION
    Inventor: Cheng-Ta Yu
  • Patent number: 9978702
    Abstract: The present invention relates to a method and an apparatus for a resurfaceable contact pad that uses an epoxy to encapsulate contact pads so that the epoxy and encapsulated contact pads are coplanar on a silicon redistribution interposer. These redistribution interposers electrically connect a wafer semi-conductor to a probe card where it is necessary to convert the course pad arrangement of one with a fine pad arrangement of the other through the use of an interposer board. The present invention relates to an apparatus and a method creates resurfaceable contact pads which may be resurfaced one or multiple times with an abrasive sanding operation to recreate a coplanar surface should any contact pad surfaces become damaged, allowing for a more cost-effective repair.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: May 22, 2018
    Assignee: RGD Circuts, Inc.
    Inventor: James V Russell
  • Patent number: 9941176
    Abstract: A method for selective bump formation on a wafer includes performing a wafer test on the wafer. Known good dies (KGDs) on the wafer are identified based on the wafer test performed. Solder bumps are formed on the KGDs.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chin-Ming Lin
  • Patent number: 9865559
    Abstract: Provided is a method for manufacturing a stretchable wire, the method including removing a portion of a photoresist layer on a substrate to form a photoresist pattern comprising at least one pattern slit, applying a liquid-phase conductive material on the photoresist pattern to form a liquid-phase conductive structure in the pattern slit, forming a stretchable first insulating layer on the liquid-phase conductive structure, after removing the photoresist pattern, and separating the liquid-phase conductive structure and the first insulating layer from the substrate.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: January 9, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chan Woo Park, Jae Bon Koo, Bock Soon Na, Rae-Man Park, Ji-Young Oh, Sang Seok Lee, Soon-Won Jung
  • Patent number: 9779951
    Abstract: A method for manufacturing a semiconductor device includes: forming a first major electrode on a first major surface of a semiconductor substrate; forming a second major electrode on a second major surface of the semiconductor substrate opposite to the first major surface; carrying out a surface activating treatment to activate surfaces of the first and second major electrodes; carrying out a surface cleaning treatment to clean up the surfaces of the first and second major electrodes; and after the surface activating treatment and the surface cleaning treatment, simultaneously forming first and second Ni films on the first and second major electrodes respectively by a wet film forming method, wherein a ratio of crystalline Ni contained in the first and second Ni films is 2% or more.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: October 3, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazunari Nakata, Yoshiaki Terasaki, Masatoshi Sunamoto
  • Patent number: 9530753
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; mounting an integrated circuit structure on the first substrate; mounting a second substrate on the integrated circuit structure; coupling a vertical chip to the first substrate and to the second substrate; and forming a package body for encapsulating the integrated circuit structure, the vertical chip, and a portion of the second substrate.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 27, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DaeSup Kim, YoungJoon Kim, DaeSik Choi
  • Patent number: 9459282
    Abstract: Provided is an electrical contact member which is capable of maintaining stable conductivity over a long period of time, while achieving low adhesion to a test subject, in particular, an electrical contact member which is capable of maintaining stable electrical contact over a long period of time by suppressing increase in the contact resistance, while achieving low adhesion to a test subject even after repeated contact at high temperatures around 85° C. or after being left in the atmosphere for a long period of time. The present invention relates to an electrical contact member, which repeatedly comes into contact with a test subject, and wherein the surface of the electrical contact member, said surface coming into contact with the test subject, is configured of a carbon coating film that contains Pd.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: October 4, 2016
    Assignee: Kobe Steel, Ltd.
    Inventors: Norihiro Jiko, Takayuki Hirano
  • Patent number: 9202791
    Abstract: An ESD protection device includes a semiconductor substrate including input/output electrodes and a rewiring layer located on the top surface of the semiconductor substrate. An ESD protection circuit is provided in the top layer of the semiconductor substrate, and the input/output electrodes are connected to the ESD protection circuit. The rewiring layer includes interlayer wiring lines, in-plane wiring lines, and post-shaped electrodes. First ends of the interlayer wiring lines provided in the thickness direction are connected to the input/output electrodes provided on the top surface of the semiconductor substrate and the second ends are connected to first ends of the in-plane wiring lines extending in the plane direction. The distance between the centers of the first and second post-shaped electrodes is larger than the distance between the centers of the first and second input/output electrodes.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: December 1, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Noboru Kato, Jun Sasaki, Kosuke Yamada
  • Patent number: 9041229
    Abstract: Systems, manufactures, methods and/or techniques for a merged fiducial for chip packages are described. According to some embodiments, an integrated circuit package may include a package substrate having a first side and a second side, a plurality of conductive traces coupled to the first side and a plurality of balls disposed on the second side. The balls may be adapted to electrically connect the laminate package to a circuit board. The integrated circuit package may include a plurality of ball pads disposed on the second side, the ball pads being adapted to electrically connect the plurality of balls to the plurality of conductive traces. One or more of the ball pads may be uniquely shaped when compared to the rest of the plurality of ball pads, optionally, to serve as a fiducial to designate an A1 pin or ball of the laminate package.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 26, 2015
    Assignee: Amkor Technology, Inc.
    Inventor: Joseph G. Johnson
  • Patent number: 9029928
    Abstract: A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: May 12, 2015
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Laurent Marechal, Yvon Imbs, Romain Coffy
  • Patent number: 9029199
    Abstract: A method for manufacturing a semiconductor device includes: preparing a semiconductor wafer including a plurality of semiconductor chips arranged in the shape of a matrix, the semiconductor wafer having a first bump electrode formed on one face thereof; forming a depressed portion on a first face of the semiconductor wafer, the depressed portion partitioning the semiconductor wafer into respective semiconductor chips; placing the first face of the semiconductor wafer onto a support tape; and cutting the semiconductor wafer along the depressed portion from a second face opposite to the first face of the semiconductor wafer by the use of a dicing blade having a width smaller than the width of the depressed portion to thereby divide the semiconductor wafer into a plurality of semiconductor chips.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: May 12, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Shinichi Sakurada
  • Patent number: 9006097
    Abstract: A method of forming a bump structure includes providing a semiconductor substrate and forming an under-bump-metallurgy (UBM) layer on the semiconductor substrate. The method further includes forming a mask layer on the UBM layer, wherein the mask layer has an opening exposing a portion of the UBM layer. The method further includes forming a copper layer in the opening of the mask layer and removing a portion of the mask layer to form a space between the copper layer and the mask layer. The method further includes performing an electrolytic process to fill the space with a metal layer and removing the mask layer.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Ming-Da Cheng, Chih-Wei Lin, Jacky Chang, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 9000585
    Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Jeffrey S. Zimmerman
  • Patent number: 8994171
    Abstract: A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hua Chang, Cheng-Lin Huang, Nai-Wei Liu, Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 8994173
    Abstract: A layer of material can protect a surface of a passivation layer against damage during a final via plug process. The protective layer can be a conductive bump limiting metallurgy (BLM) base layer and can include titanium tungsten (TiW), though other materials can be employed. Examples include applying the protective layer after formation of a via opening and prior to formation of a via opening, and can include applying more protective material after conductor plug formation to enhance protection. Photosensitive and non-photosensitive passivation layers can be so protected.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
  • Patent number: 8981566
    Abstract: Disclosed is a discrete semiconductor device package (100) comprising a semiconductor die (110) having a first surface and a second surface opposite said first surface carrying a contact (112); a conductive body (120) on said contact; an encapsulation material (130) laterally encapsulating said conductive body; and a capping member (140, 610) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap (150) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: March 17, 2015
    Assignee: NXP B.V.
    Inventors: Tim Boettcher, Sven Walczyk, Roelf Anco Jacob Groenhuis, Rolf Brenner, Emiel De Bruin
  • Patent number: 8975757
    Abstract: Solder used for flip chip bonding inside a semiconductor package was a Sn—Pb solder such as a Pb-5Sn composition. Lead-free solders which have been studied are hard and easily form intermetallic compounds with Sn, so they were not suitable for a flip chip connection structure inside a semiconductor package, which requires stress relaxation properties. This problem is eliminated by a flip chip connection structure inside a semiconductor package using a lead-free solder which is characterized by consisting essentially of 0.01-0.5 mass percent of Ni and a remainder of Sn. 0.3-0.9 mass percent of Cu and 0.001-0.01 mass percent of P may be added to this solder composition.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: March 10, 2015
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Minoru Ueshima, Masayuki Suzuki, Yoshie Yamanaka, Shunsaku Yoshikawa, Tokuro Yamaki, Tsukasa Ohnishi
  • Patent number: 8975092
    Abstract: A semiconductor assembly includes a first substrate and a chip. The chip is coupled to and spaced apart from the substrate. Further, the chip has a first surface facing the substrate. The chip also has a warpage profile indicating stress imparted on the chip following a reflow operation. The assembly includes a back layer disposed on the chip on a second surface substantially opposite from the first surface. The back layer has a non-uniform thickness. Additionally, the thickness of the back layer on each of a plurality of elements of the chip is based on the warpage profile.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 10, 2015
    Assignee: Fujitsu Limited
    Inventors: Chihiro Uchibori, Michael G. Lee
  • Patent number: 8975738
    Abstract: A structure may include a spacer element overlying a first portion of a first surface of a substrate; first terminals at a second surface of the substrate opposite the first surface; and second terminals overlying a third surface of the spacer element facing away from the first surface. Traces extend from the second terminals along an edge surface of the spacer element that extends from the third surface towards the first surface, and may be electrically coupled between the second terminals and the first terminals or electrically conductive elements at the first surface. The spacer element may at least partially define a second portion of the first surface, which is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some of the conductive elements are at the second portion and may permit connection with such microelectronic element.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 8970042
    Abstract: A circuit board is provided including a core insulation film having a thickness and including a first surface and an opposite second surface, an upper stack structure and a lower stack structure. The upper stack structure has a thickness and has an upper conductive pattern having a thickness and an overlying upper insulation film stacked on the first surface of the core insulation film. The lower stack structure has a thickness and has a lower conductive pattern having a thickness and an overlying lower insulation film stacked on the second surface of the core insulation film. A ratio P of a sum of the thicknesses of the upper conductive pattern and the lower conductive pattern to a sum of the thicknesses of the core insulation film, the upper stack structure and the lower stack structure is in a range from about 0.05 to about 0.2.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bok-Sik Myung, Chul-Woo Kim, Kyung-Tae Na, Young-Bae Kim, Yong-Hoon Kim, Hee-Seok Lee
  • Patent number: 8970037
    Abstract: A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, filling the opening on the electrode; and a dome-shaped bump containing Sn and Ti, covering the under bump metal layer, wherein at least part of the under bump metal layer has a portion sandwiched between the external electrode and the insulating covering layer.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: March 3, 2015
    Assignee: TDK Corporation
    Inventors: Kenichi Yoshida, Makoto Orikasa, Hideyuki Seike, Yuhei Horikawa, Hisayuki Abe
  • Patent number: 8963326
    Abstract: A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 24, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Xusheng Bao, Ma Phoo Pwint Hlaing, Jian Zuo
  • Patent number: 8962471
    Abstract: A two-layer structure bump including a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on a substrate and a second bump layer of a sintered body of a powder of a second conductive metal, which is any of gold and silver, formed on the first bump layer. The bulk body composing the first bump layer is formed through any of plating, sputtering, or CVD. The sintered body composing the second bump layer is formed by sintering the powder of the second conductive metal having a purity of not lower than 99.9 wt % and an average particle diameter of 0.005 ?m to 1.0 ?m. The second bump layer has a Young's modulus 0.1 to 0.4 times that of the first bump layer.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: February 24, 2015
    Assignee: Tanaka Kikinzoku Kogyo K.K.
    Inventors: Toshinori Ogashiwa, Masayuki Miyairi
  • Patent number: 8957503
    Abstract: A package includes a semiconductor device including an active surface having a contact pad. A redistribution layer (RDL) structure includes a first post-passivation interconnection (PPI) line electrically connected to the contact pad and extending on the active surface of the semiconductor device. An under-bump metallurgy (UBM) layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: February 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ying Yang, Hsien-Wei Chen, Tsung-Yuan Yu, Shih-Wei Liang
  • Patent number: 8952516
    Abstract: A microelectronic package can include a substrate having first and second opposed surfaces, and first and second microelectronic elements having front surfaces facing the first surface. The substrate can have a plurality of substrate contacts at the first surface and a plurality of terminals at the second surface. Each microelectronic element can have a plurality of element contacts at the front surface thereof. The element contacts can be joined with corresponding ones of the substrate contacts. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. The element contacts of the first microelectronic element can be arranged in an area array and are flip-chip bonded with a first set of the substrate contacts. The element contacts of the second microelectronic element can be joined with a second set of the substrate contacts by conductive masses.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: February 10, 2015
    Assignee: Tessera, Inc.
    Inventors: Wael Zohni, Belgacem Haba
  • Patent number: 8952537
    Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 10, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Feng Chan, Mu-Hsuan Chan, Chun-Tang Lin, Yi-Che Lai
  • Patent number: 8946079
    Abstract: A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: February 3, 2015
    Assignee: Tera Probe, Inc.
    Inventors: Shinji Wakisaka, Takeshi Wakabayashi
  • Patent number: 8941232
    Abstract: The mechanisms for forming metal bumps to connect to a cooling device (or a heat sink) described herein enable substrates with devices to dissipate heat generated more efficiently. In addition, the metal bumps allow customization of bump designs to meet the needs of different chips. Further, the usage of metal bumps between the semiconductor chip and cooling device enables advanced cooling by passing a cooling fluid between the bumps.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Hua Chou, Yi-Jen Lai, Chun-Jen Chen, Perre Kao
  • Patent number: 8937387
    Abstract: The disclosure concerns a semiconductor device having conductive vias. In an embodiment, the semiconductor device includes a substrate having at least one conductive via formed therein. The conductive via has a first end substantially coplanar with an inactive surface of the substrate. A circuit layer is disposed adjacent to an active surface of the substrate and electrically connected to a second end of the conductive via. A redistribution layer is disposed adjacent to the inactive surface of the substrate, the redistribution layer having a first portion disposed on the first end an electrically connected thereto, and a second portion positioned upward and away from the first portion. A die is disposed adjacent to the inactive surface of the substrate and electrically connected to the second portion of the redistribution layer.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: January 20, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Che-Hau Huang, Ying-Te Ou
  • Patent number: 8928123
    Abstract: A substrate has a first surface and a second surface opposed to each other. A blind hole is formed in the substrate extending from the first surface at a location for each through via. Each blind hole is filled with a conductive filler; a deepest part of each filler forming a bump portion made of a solder material. Part of the substrate extending from the second surface is removed to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding solder bump.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: January 6, 2015
    Assignees: STMicroelectronics S.r.l., Politecnico di Milano
    Inventors: Gian Pietro Vanalli, Giovanni Campardo, Aldo Losavio, Paolo Pulici, Pier Paolo Stoppino
  • Patent number: 8922012
    Abstract: In an integrated circuit (IC) chip and a flip chip package having the same, no wiring line is provided and the first electrode pad does not make contact with the wiring line in a pad area of the IC chip. Thus, the first bump structure makes contact with the first electrode regardless of the wiring line in the pad area. The second electrode pad makes contact with the wiring line in a pseudo pad area of the IC chip. Thus, the second bump structure in the pseudo pad area makes contact with an upper surface of the second electrode at a contact point(s) spaced apart from the wiring line under the second electrode.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: December 30, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Jin-Woo Park, Eun-Chul Ahn, Dong-Kil Shin, Sun-Won Kang, Jong-Ho Lee
  • Patent number: 8922010
    Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: December 30, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Tadahiro Morifuji, Shigeyuki Ueda
  • Patent number: 8921221
    Abstract: A photoresist layer is applied over a solder resist layer on a substrate such as a wafer. Openings in the solder resist and photoresist layers are filled with flux-free molten solder using IMS. The process is applicable to fine pitch applications and chip size packaging substrates. A protection layer may be employed to facilitate removal of the photoresist layer from the substrate. An oversized substrate including an adhesive layer on a peripheral area may be employed for providing greater adhesion of a dry film layer to the peripheral area of the substrate than the central portion thereof. The peripheral area is removed following IMS.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mark H. McLeod, Jae-Woong Nah
  • Patent number: 8921158
    Abstract: Semiconductor devices are described that are configured to have a state of operation defined by a connection between at least one inner bump assembly and a selected outer bump assembly. In an implementation, the semiconductor device, which may be a wafer-level (chip-scale) package semiconductor device, includes an integrated circuit chip, a plurality of outer bump assemblies disposed on the chip, and one or more inner bump assemblies disposed on the chip so that the inner bump assemblies are at least partially surrounded by the outer bump assemblies. At least one of the inner bump assemblies is configured to be connected to a selected outer bump assembly to cause the integrated circuit chip to have a desired state of operation.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: December 30, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Kymberly T. Christman, Roderick B. Hogan, Anand Chamakura
  • Patent number: 8922008
    Abstract: A bump structure includes a first bump and a second bump. The first bump is disposed on a connection pad of a substrate. The first bump includes a lower portion having a first width, a middle portion having a second width smaller than the first width, and an upper portion having a third width greater than the second width. The second bump is disposed on the upper portion of the first bump.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Yun Myung, Yong-Hwan Kwon, Jong-Bo Shim, Moon-Gi Cho
  • Patent number: 8916969
    Abstract: Semiconductor devices, packaging methods and structures are disclosed. In one embodiment, a semiconductor device includes an integrated circuit die with a surface having a peripheral region and a central region. A plurality of bumps is disposed on the surface of the integrated circuit die in the peripheral region. A spacer is disposed on the surface of the integrated circuit die in the central region.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ren Chen, Ming Hung Tseng, Yi-Jen Lai
  • Patent number: 8912652
    Abstract: Embodiments relate to a method for manufacturing a semiconductor device including at least one of: (1) Forming a lower electrode pattern on a substrate. (2) Forming an etch stop film on/over the lower electrode pattern. (3) Forming a first interlayer insulating layer on/over the etch stop film. (4) Forming an upper electrode pattern on/over the first interlayer insulating layer. (5) Forming a second interlayer insulating layer on/over the upper electrode pattern. (6) Forming an etch blocking layer positioned between the lower electrode pattern and the upper electrode pattern which passes through the second interlayer insulating layer and the first interlayer insulating layer. (7) Forming a cavity which exposes a side of the etch blocking layer by etching the second interlayer insulating layer and the first interlayer insulating layer. (8) Forming a contact ball in the cavity.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: December 16, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Ki Wan Bang
  • Patent number: 8907479
    Abstract: A die has a top surface, and a metal pillar having a portion protruding over the top surface of the die. A sidewall of the metal pillar has nano-wires. The die is bonded to a package substrate. An underfill is filled into the gap between the die and the package substrate.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Horng Chang, Tin-Hao Kuo
  • Patent number: 8907489
    Abstract: A wiring substrate includes: a substrate layer made of glass or silicon and including: a first surface formed with a first hole; and a second surface formed with a second hole and being opposite to the first surface, wherein the first hole is communicated with the second hole; a connection pad formed in the second hole; a first wiring layer formed in the first hole and electrically connected to the connection pad; a first insulation layer formed on the first surface of the substrate layer to cover the first wiring layer; and a second wiring layer formed on the first insulation layer and electrically connected to the first wiring layer. A diameter of the first hole is gradually decreased from the first surface toward the second surface, and a diameter of the second hole is gradually decreased from the second surface toward the first surface.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: December 9, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yuji Kunimoto, Naoyuki Koizumi
  • Patent number: 8901734
    Abstract: An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad. A first conductive material is deposited in the channel of the photoresist layer to form a column of conductive material. The remainder of the photoresist layer is removed. A masking layer is formed around the column of conductive material while exposing the interconnect pad within the column of conductive material. A second conductive material is deposited over the first conductive layer. The second conductive material extends above the column of conductive material. The masking layer is removed. The second conductive material is reflowed to form a column interconnect structure over the semiconductor device.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: December 2, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: SungWon Cho, TaeWoo Kang
  • Patent number: 8901735
    Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ying Ching Shih, Po-Hao Tsai, Chin-Fu Kao, Cheng-Lin Huang, Cheng-Chieh Hsieh, Kuo-Ching Hsu, Jing-Cheng Lin, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 8901733
    Abstract: In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: December 2, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Ching-Cheng Huang, Chuen-Jye Lin, Ming-Ta Lei, Mou-Shiung Lin
  • Patent number: 8896104
    Abstract: A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: November 25, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Haruki Ito, Nobuaki Hashimoto
  • Patent number: 8896118
    Abstract: An electronic assembly includes a copper pillar attach substrate that has a dielectric layer and a solder resist layer overlying the dielectric layer. The solder resist layer has a plurality of solder resist openings. A plurality of parallel traces are formed on the dielectric layer. Each trace has a first end portion, a second end portion and an intermediate portion. The first and second end portions of each trace are covered by the solder resist layer and the intermediate portions are positioned in the solder resist openings. Each of the intermediate portions has at least one conductive coating layer on it and has a height measured from the dielectric layer to the top of the topmost conductive coating layer that is at least as great as the solder resist layer thickness.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Nima Shahidi
  • Patent number: 8890315
    Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: November 18, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Won Kyoung Choi, Pandi C. Marimuthu