Bases Or Plates Or Solder Therefor (epo) Patents (Class 257/E23.026)
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Patent number: 7799612Abstract: Methods and systems of applying a plurality of pieces of die attach film to a plurality of singulated dice are provided. The method can involve making intervals between rows and columns of a plurality of pieces of die attach film. The interval can be made by expanding an underlaid expandable film on which the plurality of pieces of die attach film are placed or by removing portions of the die attach film between rows and columns of the plurality of pieces of die attach film. The method can further involve placing a plurality of singulated dice back side down on the plurality of pieces of die attach film.Type: GrantFiled: June 25, 2007Date of Patent: September 21, 2010Assignee: Spansion LLCInventors: Sally Foong, Tan Kiah Ling, Kee Cheng Sim, Wong Kwet Nam, Yue Ho Foong
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Patent number: 7786564Abstract: A semiconductor device according to the present invention is provided with a semiconductor chip in which a plurality of electrode pads is provided on a principal surface, a plurality of bump electrodes provided on the electrode pads of the semiconductor chip, a square-shaped wiring board which is disposed on a side of the principal surface of the semiconductor chip, and in which at least two sides of an outer circumference that face each other are positioned in an area on the principal surface of the semiconductor chip, a plurality of external terminals which is provided on the wiring board, and which are electrically connected to a plurality of the bump electrodes through a wiring of the wiring board, and sealing material which is provided between the semiconductor chip and the wiring board, and which covers a connection part between the bump electrode and the wiring.Type: GrantFiled: July 18, 2008Date of Patent: August 31, 2010Assignee: Elpida Memory, Inc.Inventors: Mitsuhisa Watanabe, Ichiro Anjoh
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Publication number: 20100213620Abstract: A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.Type: ApplicationFiled: February 18, 2010Publication date: August 26, 2010Applicant: SUMITOMO METAL MINING CO., LTD.Inventors: Yoichiro Hamada, Shigeru Hosomomi
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Patent number: 7777301Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.Type: GrantFiled: April 8, 2008Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muncy, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
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Patent number: 7772692Abstract: A semiconductor device comprises: a semiconductor element; a mounting substrate with the semiconductor element mounted thereon; a first high thermal conductivity member formed on a surface of the mounting substrate; and a first cooling member thermally connected to at least a part of the first high thermal conductivity member. The first high thermal conductivity member is thermally connected to the semiconductor element, and the first high thermal conductivity member has an outer edge which is located outside an outer edge of the semiconductor element.Type: GrantFiled: August 27, 2007Date of Patent: August 10, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tomonao Takamatsu, Hideo Aoki, Kazunari Ishimaru
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Patent number: 7759775Abstract: A high current semiconductor power SOIC package is disclosed. The package includes a relatively thick lead frame formed of a single gauge material having a thickness greater than 8 mils, the lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die soldered thereto; a pair of lead bonding areas being disposed in a same plane of a top surface of the die; large diameter bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum; and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame.Type: GrantFiled: October 6, 2006Date of Patent: July 20, 2010Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Ming Sun, Xiaotian Zhang, Lei Shi
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Patent number: 7759793Abstract: Regarding a semiconductor device, especially the present invention suppresses disconnection of the connection structure concerned in the semiconductor device which has the electric and mechanical connection structure using solder, and aims at improving connection reliability. And to achieve the above objects, the semiconductor device has the solder bump which electrically connects a semiconductor chip and a package substrate, the under-filling resin with which it filled up between the semiconductor chip and the package substrate, and a solder ball which electrically connects a package substrate with the outside, and the solder bump's elastic modulus is made lower than the elastic modulus of a solder ball.Type: GrantFiled: December 13, 2004Date of Patent: July 20, 2010Assignee: Renesas Technology Corp.Inventor: Eiji Hayashi
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Patent number: 7745930Abstract: A semiconductor device package includes a substrate with one or more pads and at least one semiconductor device that has one or more of its electrodes electrically connected to the substrate pads. The package also includes one or more terminals in electrical connection with the substrate pads and that provide for external connection to the device.Type: GrantFiled: April 24, 2006Date of Patent: June 29, 2010Assignee: International Rectifier CorporationInventors: Norman Glyn Connah, Mark Pavier, Phillip Adamson, Hazel D Schofield
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Patent number: 7732937Abstract: A semiconductor package including a leadframe having first and second major surfaces and a mold lock opening extending between the first and second major surfaces. The semiconductor package includes a semiconductor die coupled to the first major surface, and an encapsulating material formed about the semiconductor chip and a portion of the first major surface of the leadframe and filling all but a portion of the mold lock opening, the unfilled portion of the mold lock opening forming a vent extending from the second major surface to the first major surface, the vent providing a pathway for air to escape from between the second major surface and a surface to which the second major surface is to be attached.Type: GrantFiled: March 4, 2008Date of Patent: June 8, 2010Assignee: Infineon Technologies AGInventors: Bernd Goller, Markus Dinkel, Wae Chet Yong, Teck Sim Lee, Boon Kian Lim
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Patent number: 7732894Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.Type: GrantFiled: February 13, 2008Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muney, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
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Patent number: 7727813Abstract: A method for making a device is disclosed. One embodiment provides a substrate having a first element protruding from the substrate. A semiconductor chip has a first electrode on a first surface and a second electrode on a second surface opposite to the first surface. The semiconductor chip is placed over the first element of the substrate with the first surface of the semiconductor chip facing the substrate. The second electrode of the semiconductor chip is electrically coupled to the substrate, and the substrate is at least partially removed.Type: GrantFiled: November 26, 2007Date of Patent: June 1, 2010Assignee: Infineon Technologies AGInventors: Ralf Otremba, Xaver Schloegel, Rupert Fischer, Tien Lai Tan
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Patent number: 7723158Abstract: In a method for producing bases with external contacts for surface mounting on circuit mounts, bases with external contacts are electrodeposited on semiconductor wafers or semiconductor chips. Subsequently, electrodeposited bases with external contacts are heat treated on the semiconductor wafers or the semiconductor chips at temperatures below the melting temperature of the deposited contact base material. Thereafter, a so-called RTP process is carried out in the form of a high-temperature interval in which the melting temperature is reached. Subsequently, the surfaces of the bases with external contacts are wet etched, the overall method being terminated by a cooling and drying operation. The bases with external contacts thus produced can be reliably surface mounted on circuit mounts.Type: GrantFiled: October 25, 2006Date of Patent: May 25, 2010Assignee: Infineon Technologies AGInventors: Thomas Gutt, Sokratis Sgouridis
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Patent number: 7713859Abstract: A process for forming a solder bump on an under bump metal structure in the manufacture of a microelectronic device comprising exposing the under bump metal structure to an electrolytic bath comprising a source of Sn2+ ions, a source of Ag+ ions, a thiourea compound and/or a quaternary ammonium surfactant; and supplying an external source of electrons to the electrolytic bath to deposit a Sn—Ag alloy onto the under bump metal structure.Type: GrantFiled: August 9, 2006Date of Patent: May 11, 2010Assignee: Enthone Inc.Inventors: Thomas B. Richardson, Marlies Kleinfeld, Christian Rietmann, Igor Zavarine, Ortrud Steinius, Yun Zhang, Joseph A. Abys
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Patent number: 7705443Abstract: An electrical connection inside a semiconductor device is established by lead frames formed of plural conductor plates. The lead frames are disposed three-dimensionally so that the respective weld parts thereof are exposed toward a laser light source used in the laser welding. The laser welding is then performed by irradiating a laser beam. According to the above, welding can be performed readily in a reliable manner. The productivity of the semiconductor device and the manufacturing method of the semiconductor device can be thus enhanced. In addition, because the lead frames have the cooling effect, they have the capability of a heat spreader. It is thus possible to provide a semiconductor device and a manufacturing method of the semiconductor device with high productivity.Type: GrantFiled: October 16, 2007Date of Patent: April 27, 2010Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Toshiyuki Yokomae, Katsumichi Ueyanagi, Eiji Mochizuki, Yoshinari Ikeda
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Publication number: 20100044884Abstract: An integrated circuit package employs a solder pad that includes a predetermined three dimensional surface that is adapted to receive solder. In one example, the predetermined three dimensional surface includes at least one predetermined hill or protruding portion and a valley portion, such as a lower portion, having a predetermined relative height between the hill portion and a valley portion. The predetermined three dimensional surface can be configured in any suitable configuration and may include contoured patterns, non-patterns, or any other suitable configuration as desired. A related method is also described.Type: ApplicationFiled: August 19, 2008Publication date: February 25, 2010Applicant: ATI Technologies ULCInventors: Adam R. Zbrzezny, Roden R. Topacio
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Patent number: 7663242Abstract: A solder preform having multiple layers including a solder layer filled with additives interposed between two unfilled layers for improved wettability. A solder preform having a sphere which contains a solder material filled with additives, and an unfilled surface layer for improved wettability. A thermal interface material having a bonding component and an additive component which is a CTE modifying component and/or a thermal conductivity enhancement component. Active solders containing intrinsic oxygen getters.Type: GrantFiled: March 6, 2007Date of Patent: February 16, 2010Inventors: Brian G. Lewis, Bawa Singh, John P. Laughlin, David V. Kyaw, Anthony E. Ingham, Attiganal N. Sreeram, Leszek Hozer, Michael J. Liberatore, Gerard R. Minogue
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Patent number: 7648856Abstract: Methods for attaching microfeature dies to external devices are disclosed. The external devices can include other microfeature dies, support members or other suitable devices. A particular method includes attaching the solder to the at least one of the microfeature die in the support member by changing a phase of the solder. The method can further include contacting the solder with the other of the microfeature die and the support member and urging the microfeature die and the support member toward each other to provide a first bond between the die and the support member via the solder. The method can still further include changing a phase of the solder to provide a second bond between the microfeature die and the support member, with the second bond being stronger than the first bond.Type: GrantFiled: August 28, 2006Date of Patent: January 19, 2010Assignee: Micron Technology, Inc.Inventor: Rick C. Lake
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Publication number: 20090321962Abstract: A microelectronic package is provided. The microelectronic package includes a substrate having a plurality of solder bumps disposed on a top side of the substrate and a die disposed adjacent to the top side of the substrate. The die includes a plurality of glassy metal bumps disposed on a bottom side of the die wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer. The liquid solder layer is to attach the die with the substrate.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Inventor: Daewoong Suh
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Patent number: 7601612Abstract: A method for forming a solder joint for a package arrangement with a dispersed Sn microstructure provides a flip chip on a package, with a flip chip having solder bumps to be connected by eutectic solder joints to pads on the package. The eutectic solder is reflowed at a solder bump/pad interface with a eutectic reflow profile that is configured to achieve eutectic solder joints having substantially evenly distributed Sn grains. The eutectic reflow profile includes an increased cooling rate and decreased hold time with a higher peak temperature. A defined ratio of the pad openings in the solder mask to the under bump metallurgy is provided. The eutectic reflow profile and the defined ratio prolong fatigue life in the package arrangement.Type: GrantFiled: October 24, 2005Date of Patent: October 13, 2009Assignee: GlobalFoundries Inc.Inventors: Raj N. Master, Junaida A. Bakar, Diong H. Ding, Srinivasan Parthasarathy
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Patent number: 7595553Abstract: An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region.Type: GrantFiled: November 8, 2007Date of Patent: September 29, 2009Assignee: Sanyo Electric Co., Ltd.Inventors: Masayuki Nagamatsu, Ryosuke Usui
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Publication number: 20090230539Abstract: In recent years, as electronic equipment becomes thinner, an area for mounting a semiconductor device used in the electronic equipment is required to be smaller, and a thickness of an encapsulating resin for encapsulating a semiconductor substrate having a circuit formed thereon and the like also becomes smaller. The encapsulating resin is marked with a product number, a manufacturer name, or the like. There arises a problem in that, in the marking, an infrared laser beam applied to the encapsulating resin passes through the encapsulating resin, generates heat in the semiconductor substrate, and destructs the formed circuit. By providing a thin film for refracting the infrared laser beam on a rear surface of the semiconductor substrate, the optical path of the infrared laser beam is made longer to reduce heat generated in the semiconductor substrate.Type: ApplicationFiled: February 12, 2009Publication date: September 17, 2009Applicant: NEC ELECTRONICS CORPORATIONInventor: TOMOHIRO KAMIMURA
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Publication number: 20090200681Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.Type: ApplicationFiled: April 20, 2009Publication date: August 13, 2009Inventors: Qing Zhou, Wei Shi, Daoqiang Lu, Jiangqi He
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Publication number: 20090194871Abstract: A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 Kg, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds.Type: ApplicationFiled: December 24, 2008Publication date: August 6, 2009Applicant: UTAC - United Test and Assembly Test Center, Ltd.Inventors: Denver Paul C. Castillo, Soon Hua Bryan Tan, Rodel Manalac, Kian Teng Eng, Pang Hup Ong, Soo Pin Chow, Wolfgang Johannes Hetzel, Werner Josef Reiss, Florian Ammer
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Patent number: 7569920Abstract: An electronic component includes a vertical semiconductor power transistor and a further semiconductor device arranged on the transistor to form a stack. The first vertical semiconductor power transistor has a semiconductor body having a first side and a second side and device structures, at least one first electrode positioned on the first side and at least one second electrode positioned on the second side. The semiconductor body further has at least one electrically conductive via. The via extends from the first side to the second side of the semiconductor body and is galvanically isolated from the device structures of the semiconductor body and from the first electrode and the second electrode.Type: GrantFiled: May 10, 2006Date of Patent: August 4, 2009Assignee: Infineon Technologies AGInventors: Ralf Otremba, Klaus Schiess
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Patent number: 7554172Abstract: An electrode plate for an electricity storage and discharge device, which includes a plurality of I/O convergence terminals evenly distributed along a periphery of the electrode plate, and a plurality of conductive structures, each conductive structure for one of the I/O convergence terminals, wherein each conductive structure is of a radial pattern that centers on the one of the I/O convergence terminals, and radiates towards the interior of the electrode plate.Type: GrantFiled: April 7, 2005Date of Patent: June 30, 2009Inventor: Tai-Her Yang
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Patent number: 7550845Abstract: In a ball grid array (BGA) package, a first stiffener is attached to a surface of a substrate. A second stiffener is attached to the surface of the substrate to be co-planar with the first stiffener. The second stiffener is separated from the first stiffener by a channel therebetween. An integrated circuit (IC) die is mounted to a surface of the second stiffener.Type: GrantFiled: October 31, 2002Date of Patent: June 23, 2009Assignee: Broadcom CorporationInventors: Sam Ziqun Zhao, Reza-ur Rahman Khan
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Publication number: 20090115056Abstract: A device mounting board includes an insulating layer formed of an insulating resin, a glass cloth covering the surface of the insulating layer, and an electrode provided in a through hole extending through the glass cloth. The angle of contact with solder of the glass cloth is larger than that of the resin. Thus, solder bumps are formed on the electrode of the device mounting board 10 with high precision.Type: ApplicationFiled: October 31, 2008Publication date: May 7, 2009Inventors: Kouichi Saitou, Mayumi Nakasato, Ryosuke Usui
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Publication number: 20090102329Abstract: In a rectifier for an automotive alternator, each of the rectifying elements includes a semiconductor chip and a lead electrode that connects the semiconductor chip to a corresponding one of terminals. The lead electrode has a joining portion joined to a second surface of the semiconductor chip and a lead body portion extending in a direction perpendicular to the second surface. The corresponding terminal has a joining portion that protrudes out of a terminal base and extends in the direction parallel to the second surface to be joined to the lead body portion. The joining portion of the corresponding terminal is formed of first and second terminal plates that are laminated in the direction perpendicular to the second surface. The first terminal plate is located farther from the semiconductor chip than the second terminal plate and has a larger coefficient of thermal expansion than the second terminal plate.Type: ApplicationFiled: October 16, 2008Publication date: April 23, 2009Applicant: DENSO CORPORATIONInventor: Harumi Kume
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Publication number: 20090051038Abstract: A semiconductor device includes a semiconductor constituent having a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. An under-layer insulating film is provided under and around the semiconductor constituent. A plurality of under-layer wires are provided under the under-layer insulating film and electrically connected to the electrodes for external connection of the semiconductor constituent. An insulating layer is provided around the semiconductor constituent and on the under-layer insulating film. A frame-like insulating substrate is embedded in an upper surface of the insulating layer and positioned around the semiconductor constituent. A plurality of upper-layer wires are provided on the insulating substrate. A base plate on which the semiconductor constituent and the insulating layer are mounted is removed.Type: ApplicationFiled: August 20, 2008Publication date: February 26, 2009Applicant: Casio Computer Co., Ltd.Inventor: Hiroyasu Jobetto
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Patent number: 7492043Abstract: A power module flip chip package is provided. The power module flip chip package includes a package carrier having a front surface and a back surface facing the front surface, and a power semiconductor device electrically connected to the front surface of the package carrier via conductive bumps. The conductive bumps are electrically connected to a gate terminal, a source terminal, and a drain terminal of the power semiconductor device. The power module flip chip package has reduced resistance and inductance and improved reliability.Type: GrantFiled: August 26, 2004Date of Patent: February 17, 2009Assignee: Fiarchild Korea Semiconductor, LtdInventors: Seung-yong Choi, Jonathan A. Noquil
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Publication number: 20080315390Abstract: A package includes a sensor die with a micro component, such as a MEMS device, coupled to an integrated circuit which may include, for example, CMOS circuitry, and one or more electrically conductive bond pads near the periphery of the sensor die. A semiconductor cap structure is attached to the sensor die. The front side of the cap structure is attached to the sensor die by a seal ring to hermetically encapsulate an area of the sensor die where the micro component is located. The bond pads on the sensor die are located outside the area encapsulated by the seal ring. Electrical leads, which extend along outer side edges of the semiconductor cap structure from its front side to its back side, are coupled to the micro component via the bond pads.Type: ApplicationFiled: June 20, 2008Publication date: December 25, 2008Inventors: Jochen Kuhmann, Matthias Heschel
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Patent number: 7414319Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a metal containment wall and a solder terminal, and a connection joint that electrically connects the routing line and the pad. The metal containment wall includes a cavity, and the solder terminal contacts the metal containment wall in the cavity and is spaced from the routing line.Type: GrantFiled: August 26, 2005Date of Patent: August 19, 2008Assignee: Bridge Semiconductor CorporationInventors: Charles W. C. Lin, Chia-Chung Wang
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Patent number: 7411297Abstract: Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting from the surface and arranged in arrays on the surface. In one embodiment, a method includes forming a coating on the interconnect elements of the microfeature workpiece, producing a layer over the surface of the microfeature workpiece after forming the coating, and removing the coating from at least a portion of the individual interconnect elements. The coating has a surface tension less than a surface tension of the interconnect elements to reduce the extent to which the material in the layer wicks up the interconnect elements and produces a fillet at the base of the individual interconnect elements.Type: GrantFiled: April 20, 2006Date of Patent: August 12, 2008Assignee: Micron Technology, Inc.Inventors: Shijian Luo, Tongbi Jiang
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Publication number: 20080174030Abstract: The present invention provides a multi-chip stacking structure. The multichip stacking structure comprises: a chip carrier; a first and a second chip modules respectively having a plurality of first and a plurality of second chips, wherein each chips has a bond pad and the chips are stacked on the chip carrier in a step-like manner to expose the bond pads; and a plurality of bonding wires for electrically connecting the bond pads of the first and the second chip modules to the chip carrier, wherein a bottom chip of the second chip module is stacked on a top chip of the first chip module by an adhesive layer having fillers therein to support the bottom chip, and the bottom chip is deviated from the top chip horizontally in a direction toward the bonding wires of the first chip module.Type: ApplicationFiled: January 23, 2008Publication date: July 24, 2008Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Chung-Lun Liu, Chin-Huang Chang, Yi-Feng Chang, Jung-Pin Huang, Chih-Ming Huang
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Publication number: 20080164609Abstract: Methods for making solder balls, which can be used to bump semiconductor wafers are disclosed. Methods for bumping semiconductor wafers with the solder balls are also disclosed. The solder balls can be made using an injection molded soldering (IMS) process.Type: ApplicationFiled: January 8, 2007Publication date: July 10, 2008Applicant: International Business Machines CorporationInventors: Peter A. Gruber, Barry A. Hochlowski, David T. Naugle
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Patent number: 7388293Abstract: An interposer to be interposed between a semiconductor chip to be mounted thereon and a packaging board has an interposer portion made of a semiconductor material and an interposer portion provided around the foregoing interposer portion integrally therewith. On both surfaces of the interposer portions, wiring patterns are formed via insulating layers. The wiring patterns are electrically connected via through holes formed at required positions in the interposer portions. The outer interposer portion is made of an insulator or a metal body. Further, external connection terminals are bonded to one surface of the interposer.Type: GrantFiled: June 14, 2005Date of Patent: June 17, 2008Assignee: Shinko Electric Industries, Co.Inventors: Katsuya Fukase, Shinichi Wakabayashi
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Publication number: 20080122056Abstract: Provided is a semiconductor device package comprising a printed circuit board, the printed circuit board including a window at a central portion and a connection part, a semiconductor chip including center-type bonding pads, wherein the semiconductor chip is mounted on an upper surface of the printed circuit board such that the center-type bonding pads are exposed by the window, bonding wires electrically connecting the center-type bonding pads with the printed circuit board through the window, a lower molding material at a lower surface of the printed circuit board, the lower molding material encapsulating the center-type bonding pads and the bonding wires, and an upper molding material encapsulating the semiconductor chip and the upper surface of the printed circuit board, wherein the lower molding material and the upper molding material are connected to each other through the connection part of the printed circuit board.Type: ApplicationFiled: November 9, 2007Publication date: May 29, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Shle-Ge Lee, Dong-Kil Shin, Min-Young Son
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Patent number: 7298049Abstract: A submount that enables the reliable mounting of a semiconductor light-emitting device on it, and a semiconductor unit incorporating the submount. A submount 3 comprises (a) a substrate 4; and (b) a solder layer 8 formed on the top surface 4f of the substrate 4. The solder layer 8 before melting has a surface roughness, Ra, of at most 0.18 ?m. It is more desirable that the solder layer 8 before melting have a surface roughness, Ra, of at most 0.15 ?m, yet more desirably at most 0.10 ?m. A semiconductor unit 1 comprises the submount 3 and a laser diode 2 mounted on the solder layer 8 of the submount 3.Type: GrantFiled: March 3, 2003Date of Patent: November 20, 2007Assignee: Sumitomo Electric Industries, Ltd.Inventors: Teruo Amoh, Takashi Ishii, Kenjiro Higaki, Yasushi Tsuzuki
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Patent number: 7298039Abstract: In order to provide a low-cost and high heat-radiating electronic circuit device featuring high compactness, little warpage, high air tightness, high moldability, high mass productivity, high reliability against thermal shocks, and high oil-proof reliability, a module structure made by packing a whole multi-layer circuit board which connects a semiconductor operating element, semiconductor memory elements, and passive elements thereon and part of a supporting material on which said multi-layer circuit board is placed into a single package by transfer-molding; wherein said multi-layer circuit board and said supporting material are bonded together with a compound metallic material made up from copper oxide and at least one metal selected from a set of gold, silver, and copper.Type: GrantFiled: August 4, 2004Date of Patent: November 20, 2007Assignee: Hitachi, Ltd.Inventors: Nobutake Tsuyuno, Toshiaki Ishii, Toshiya Satoh, Mitsuhiro Masuda
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Publication number: 20070259480Abstract: A method of coupling an integrated circuit (IC) assembly to a printed wiring board (PWB) is provided. The method comprises applying a solder paste to at least one IC assembly interfacial attach pad having a first size on a surface of the IC assembly and applying a solder paste to at least one PWB interfacial attach pad having a second size on a surface of the PWB. The method also comprises reflow attaching the at least one IC assembly interfacial attach pad to the at least one PWB interfacial attach pad, wherein the difference between the size of the at least one PWB interfacial attach pad and the size of the at least one IC assembly interfacial attach pad substantially inhibits self-alignment and lift-off forces.Type: ApplicationFiled: May 2, 2006Publication date: November 8, 2007Applicant: Honeywell International Inc.Inventor: Lance Sundstrom
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Patent number: 7242085Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10A). A metal base (10A) can have side portions (12) with connection electrodes (15A) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The connection electrode (15A) can be formed on a projecting piece (16) that is bent outward away from remaining portions of the side portion (12). The semiconductor device can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.Type: GrantFiled: September 22, 2004Date of Patent: July 10, 2007Assignee: NEC Electronics CorporationInventor: Futoshi Hosoya
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Publication number: 20070080469Abstract: With a semiconductor package according to an aspect of the present invention comprising a board having circuit lines, solder resist formed on a surface of the board, and a chip mounted on the board and having at least one bump attached to at least a portion of the circuit lines, where the solder resist comprises a perimeter groove, which exposes at least a portion of the circuit lines, and an extension groove, which is connected to the perimeter groove, and where encapsulant is filled in the perimeter groove and the extension groove, the filling characteristics of the encapsulant is improved for greater reliability in the electrical connections between the chip and the board.Type: ApplicationFiled: September 28, 2006Publication date: April 12, 2007Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung-Gu Kim, Je-Gwang Yoo, Yong-Bin Lee, Yoo-Keum Wee, Seok-Hwan Huh, Chang-Sup Ryu
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Publication number: 20070035012Abstract: A system may include an integrated heat spreader that includes a portion of solder material and a thermal conductor, wherein a voidless interface exists between the solder material and a first side of the thermal conductor.Type: ApplicationFiled: October 13, 2006Publication date: February 15, 2007Inventors: Carl Deppisch, Edward Martin, Sabina Houle, James Mellody, Marvin Burgess, Maureen Brown, Robert DeBlieck, David Carroll
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Patent number: 7170183Abstract: Disclosed are a wafer level stacked package and its manufacturing method. As one example, in such a wafer level stacked package, a first semiconductor die is electrically connected to an upper surface of a substrate and a second semiconductor die is electrically connected to a lower surface of the substrate. That is, with respect to one substrate, semiconductor dies can be stacked on upper and lower surfaces of the substrate. Also, underfill is formed between the respective semiconductor dies and the substrate, thereby enhancing bonding forces between the respective semiconductor dies and the substrate. In addition to stacking the semiconductor dies, packages can be stacked with each other. That is, it is possible to stack a plurality of completed wafer level packages with each other in an up-and-down direction.Type: GrantFiled: May 13, 2005Date of Patent: January 30, 2007Assignee: Amkor Technology, Inc.Inventors: Bong Chan Kim, Yoon Joo Kim, Ji Young Chung
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Publication number: 20060175711Abstract: A method for bonding an IC chip to a substrate where the method comprises the steps of providing an IC chip with a plurality of bumps each having a buffer layer and a conductive layer, providing a substrate having a plurality of conductive elements arranged corresponding to the plurality of bumps, placing a non-conductive film between the plurality of conductive devices and their corresponding bumps, and pressing and heating the IC chip and the substrate so that the plurality of bumps are in contact with the plurality of conductive elements respectively. The bonding structure is formed between a first and second substrate where the structure has a buffer layer having an opening and formed on the first substrate, a conductive layer formed on the buffer layer, and a non-conductive film formed between the conductive layer and the second substrate as a bonding medium for the bonding structure.Type: ApplicationFiled: February 8, 2005Publication date: August 10, 2006Applicant: HannStar Display CorporationInventors: Pao-Yun Tang, Shu-Lin Ho, Hsiu-Sheng Hsu, Nan-Cheng Huang