Additional Leads Being Bump Or Wire (epo) Patents (Class 257/E23.033)
  • Patent number: 10141237
    Abstract: This application provides a fingerprint recognition module and a manufacturing method therefor. The fingerprint recognition module includes a flexible printed circuit (FPC) board, a die, an adhesive layer, and a cover plate. The manufacturing method includes the following steps: (a) directly welding the die to the FPC board, and electrically connecting the die to the FPC board; (b) coating the adhesive layer on an upper surface of the die; (c) covering the adhesive layer with a cover plate, to adhere the cover plate to the adhesive layer; and (d) applying low pressure injection modeling encapsulation to an encapsulation space defined between the cover plate and the FPC board, so as to form an encapsulation layer in the encapsulation space and produce a waterproof effect.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: November 27, 2018
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventor: Tsung-Yi Lu
  • Patent number: 9780069
    Abstract: A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: October 3, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Motoharu Haga, Shingo Yoshida, Yasumasa Kasuya, Toichi Nagahara, Akihiro Kimura, Kenji Fujii
  • Patent number: 9035472
    Abstract: In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takaharu Nagasawa
  • Patent number: 9029903
    Abstract: A light emitting diode package including a package body with a cavity, a plurality of light emitting diode (LED) chips in the cavity, a plurality of wires connected to the plurality of LED chips, and a plurality of lead frames in the package body, wherein the lead frames comprise a first lead frame electrically connected to a first electrode of a first LED chip, a second lead frame electrically connected to a second electrode of the first LED chip and a second electrode of a second LED chip, a third lead frame electrically connected to a first electrode of the second LED chip, and fourth lead frame electrically connected to a second electrode of a third LED chip. Further, ends of the lead frames are exposed outside of the package body and penetrate the package body, and the first electrodes are P electrodes and the second electrodes are N electrodes.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: May 12, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Won-Jin Son
  • Patent number: 9030028
    Abstract: A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallization layer is formed on the second surface of the semiconductor substrate. The metallization layer has a thickness which is greater than the device thickness.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Rudolf Zelsacher, Paul Ganitzer
  • Patent number: 8975738
    Abstract: A structure may include a spacer element overlying a first portion of a first surface of a substrate; first terminals at a second surface of the substrate opposite the first surface; and second terminals overlying a third surface of the spacer element facing away from the first surface. Traces extend from the second terminals along an edge surface of the spacer element that extends from the third surface towards the first surface, and may be electrically coupled between the second terminals and the first terminals or electrically conductive elements at the first surface. The spacer element may at least partially define a second portion of the first surface, which is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some of the conductive elements are at the second portion and may permit connection with such microelectronic element.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 8975116
    Abstract: An electronic unit is produced including at least one electronic component at least partially embedded in an insulating material. A film assembly is provided with at least one conductive layer and a carrier layer. The conductive layer includes openings in the form of holes for receiving bumps, which are connected to contact surfaces of the at least one electronic component. The at least one component is placed on the film assembly such that the bumps engage with the openings of the conductive layer. The at least one component is partially embedded from the side opposite of the bumps into a dielectric layer. The carrier layer of the film assembly is removed such that the surface of the bumps is exposed. A metallization layer is then deposited on the side of the remaining conductive layer having the exposed bumps and so as to produce conductor tracks that overlap with the bumps.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 10, 2015
    Assignees: Technische Universität Berlin, Fraunhofer-Gesellschaft zur Foerderung der angewandt Forschung e.V.
    Inventors: Andreas Ostmann, Dionysios Manessis, Lars Böttcher, Stefan Karaszkiewicz
  • Patent number: 8927967
    Abstract: An electrochemically-gated field-effect transistor includes a source electrode, a drain electrode, a gate electrode, a transistor channel and an electrolyte. The transistor channel is located between the source electrode and the drain electrode. The electrolyte completely covers the transistor channel and has a one-dimensional nanostructure and a solid polymer-based electrolyte that is employed as the electrolyte.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: January 6, 2015
    Assignee: Karlsruhe Institute of Technology
    Inventors: Subho Dasgupta, Horst Hahn, Babak Nasr
  • Patent number: 8921986
    Abstract: A semiconductor power chip, may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; and an insulation layer disposed on top of the semiconductor die and being patterned to provide openings to access the plurality of second and third contact elements and the at least one first contact element.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 30, 2014
    Assignee: Microchip Technology Incorporated
    Inventors: Gregory Dix, Roger Melcher
  • Patent number: 8860193
    Abstract: Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: October 14, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Shiann-Ming Liou, Huahung Kao
  • Patent number: 8841760
    Abstract: A stacked semiconductor device includes a unit component including a wiring portion formed by electrically connecting a die pad of and a lead of a lead frame, and a semiconductor package whose connection terminal is connected to the lead, wherein the unit component is stacked, and the leads located to upper and lower sides are connected mutually via an electrode.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 23, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Kei Murayama
  • Patent number: 8836093
    Abstract: The present invention relates to the field of semiconductor chip packages, and more specifically to a lead frame and flip chip package device thereof. In one embodiment, a lead frame for electrically connecting a chip to outside leads, can include a plurality of lead fingers, where each of the plurality of lead fingers comprises a plurality of outburst regions extending from an edge thereof. In one embodiment, a flip chip package device can include: a chip and a plurality of solder bumps, where one surface of the chip is connected to a first surface of each of the plurality of solder bumps; and the lead frame, where second surfaces of each of the plurality solder bumps are connected with corresponding outburst regions of the lead frame to connect the chip to the lead frame through the solder bumps.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: September 16, 2014
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
    Inventor: Xiaochun Tan
  • Patent number: 8816483
    Abstract: A method for fixing a semiconductor chip on a circuit board is provided, which includes following steps. The circuit board is provided, which sequentially includes a substrate having a chip connecting portion, at least one metal wire and an insulating layer. An organic insulating material is formed on the insulating layer of the outside edge of the chip connecting portion. An anisotropic conductive film (ACF) is then formed to cover the chip connecting portion and a portion of the organic insulating material. Finally, a semiconductor chip is hot-pressed on the ACF. The organic insulating material formed on the insulating layer is used to prevent the metal wires beneath the insulating layer from occurring of corrosion. A semiconductor chip package structure is also provided.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: August 26, 2014
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Chi-Chao Liu, Chih-Jui Wang, Long-Chi Chen
  • Patent number: 8810013
    Abstract: An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: August 19, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Eric Yang, Jinghai Zhou, Hunt Hang Jiang
  • Patent number: 8796839
    Abstract: An apparatus that comprises a power ground/arrangement that comprises a first semiconductor die configured as a central processing unit (CPU). The power/ground arrangement further comprises a first metal layer that provides only one of (i) a power signal and (ii) a ground signal, and a second metal layer that provides the other one of (i) the power signal and (ii) the ground signal. The apparatus further comprises a second semiconductor die configured as a memory that is coupled to the power/ground arrangement. The second semiconductor die is configured to receive power signals and ground signals from the power/ground arrangement. The second semiconductor die is further configured to provide signals to the CPU via the power/ground arrangement and to receive signals from the CPU via the power/ground arrangement. The second semiconductor die is coupled to the power/ground arrangement only along a single side of the second semiconductor die.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: August 5, 2014
    Assignee: Marvell International Ltd.
    Inventors: Sehat Sutardja, Albert Wu
  • Patent number: 8791556
    Abstract: An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 29, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8786062
    Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: July 22, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Chia-Hsiung Hsieh, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh
  • Patent number: 8710637
    Abstract: To suppress a short circuit between neighboring wires which is caused when the loop of a wire is formed into multiple stages in a semiconductor device in which a wiring board and one semiconductor chip mounted over a main surface thereof are electrically coupled with the wire. In a semiconductor device in which a chip is mounted on an upper surface of a wiring board and a bonding lead of the wiring board and a bonding pad of the chip are electrically coupled with wires, a short circuit between the neighboring wires is suppressed by making larger the diameter of the longest wire arranged in a position closest to a corner part of the chip than the diameter of the other wires.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: April 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yukinori Tashiro, Yoshinori Miyaki
  • Publication number: 20140103509
    Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An opening is formed in a first surface of the encapsulant by etching or LDA. A plurality of bumps is optionally formed over the semiconductor die. A bump is recessed within the opening of the encapsulant. A conductive ink is formed over the first surface of the encapsulant, bump and sidewall of the opening. The conductive ink can be applied by a printing process. An interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The interconnect structure is electrically connected to the semiconductor die. A semiconductor package is disposed over the first surface of the encapsulant with a plurality of bumps electrically connected to the conductive ink layer. The semiconductor package may contain a memory device.
    Type: Application
    Filed: October 16, 2012
    Publication date: April 17, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Insang Yoon, Flynn Carson, Il Kwon Shim, SeongHun Mun
  • Patent number: 8698294
    Abstract: An integrated circuit package system provides a known good die module by providing a leadframe, providing a first die, attaching the first die to the leadframe, and encapsulating at least the first die. A second die is attached to the known good die module such that the known good die module is a substrate for the second die. The second die is electrically attached to the known good die module. At least the second die is additionally encapsulated.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: April 15, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Jose Alvin Caparas, Arnel Trasporto, Jeffrey D. Punzalan
  • Publication number: 20140097526
    Abstract: A method of assembling a packaged integrated circuit (IC) includes printing a viscous dielectric polymerizable material onto a die pad of a leadframe having metal terminals positioned outside the die pad. An IC die having a top side including a plurality of bond pads is placed with its bottom side onto the viscous dielectric polymerizable material. Bond wires are wire bonded between the plurality of bond pads and the metal terminals of the leadframe.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: WAN MOHD MISUARI SULEIMAN, AZDHAR DAHALAN
  • Patent number: 8692370
    Abstract: A semiconductor element (10) is secured to an island (7), and a plurality of through-holes (8) are formed in the portion of the island (7), which surrounds the area to which the semiconductor element (10) is secured. Further, the electrode pads of the semiconductor element (10) and leads (4) are electrically connected by copper wires (11). In this structure, the cost of materials is reduced by using the copper wires (11) in comparison with gold wires. Further, a part of a resin package (2) is embedded in through-holes (8), so that the island (7) can be easily supported within the resin package (2).
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: April 8, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Takashi Kitazawa, Yasushige Sakamoto, Motoaki Wakui
  • Patent number: 8692387
    Abstract: A semiconductor package and method of assembling a semiconductor package includes encapsulating a first pre-packaged semiconductor die stacked on top of and interconnected with a second semiconductor die. The first packaged semiconductor die is positioned and fixed relative to a lead frame with a temporary carrier such as tape. The second semiconductor die is attached and interconnected directly to the first packaged semiconductor die and lead frame. The interconnected first packaged die and second semiconductor die, and lead frame are encapsulated to form the semiconductor package. Different types of semiconductor packages such as quad flat no-lead (QFN) and ball grid array (BGA) may be formed, which provide increased input/output (I/O) count and functionality.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: April 8, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shunan Qiu, Guoliang Gong, Xuesong Xu, Xingshou Pang, Beiyue Yan, Yinghui Li
  • Publication number: 20140091442
    Abstract: An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Bok Eng Cheah, Shanggar Periaman, Kooi Chi Ooi
  • Patent number: 8664760
    Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Cheng-Chieh Hsieh, Kuo-Ching Hsu, Ying-Ching Shih, Po-Hao Tsai, Chin-Fu Kao, Cheng-Lin Huang, Jing-Cheng Lin
  • Patent number: 8648458
    Abstract: An integrated circuit leadframe device supports various chip arrangements. As consistent with various embodiments, a leadframe includes a plurality of banks of conductive integrated circuit chip connectors. Each bank has a plurality of conductive strips respectively having an end portion, the end portions of each of the strips in the bank being substantially parallel to one another and arranged at an oblique angle to end portions of strips in at least one of the other banks. Each of the end portions has a tip extending to an interior portion of the leadframe device and separated from the other tips by a gap.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: February 11, 2014
    Assignee: NXP B.V.
    Inventor: Barry Lin
  • Publication number: 20140027889
    Abstract: A reconstituted wafer level package for a versatile high-voltage capable component is disclosed. The reconstituted wafer package includes a dice substantially encapsulated by a mold material except for a first face. A dielectric layer is disposed on the first face of the dice. The package further includes an array of ball bumps formed on an exterior facing portion of the dielectric layer. Further, a field plate is disposed within the dielectric material and interposed between the first face of the dice and the ball bump array. The field plate may be spaced from the dice by a predetermined distance to prevent dielectric breakdown of the material of the dielectric layer.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 30, 2014
    Inventors: Mark R. Boone, Mohsen Askarinya, Larry E. Tyler
  • Patent number: 8604596
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a hole, a lead extension, and an exterior pad under the lead extension with the hole abutting the lead extension; connecting an electrical interconnect between an integrated circuit and the lead extension; forming an encapsulation over the integrated circuit and surrounding the electrical interconnect and through the hole; and removing a bottom portion of the lead frame resulting in a stand-off lead from the lead extension with the exterior pad on the stand-off lead.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: December 10, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Patent number: 8571229
    Abstract: A semiconductor device includes at least a die carried by a substrate, a plurality of bond pads disposed on the die, a plurality of conductive components, and a plurality of bond wires respectively connected between the plurality of bond pads and the plurality of conductive components. The plurality of bond pads respectively correspond to a plurality of signals, and include a first bond pad configured for transmitting/receiving a first signal and a second bond pad configured for transmitting/receiving a second signal. The plurality of conductive components include a first conductive component and a second conductive component. The first conductive component is bond-wired to the first bond pad, and the second conductive component is bond-wired to the second bond pad. The first conductive component and the second conductive component are separated by at least a third conductive component of the plurality of conductive components, and the first signal is asserted when the second signal is asserted.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: October 29, 2013
    Assignee: Mediatek Inc.
    Inventors: Chien-Sheng Chao, Tse-Chi Lin, Yin-Chao Huang
  • Publication number: 20130277814
    Abstract: A method for fixing a semiconductor chip on a circuit board is provided, which includes following steps. The circuit board is provided, which sequentially includes a substrate having a chip connecting portion, at least one metal wire and an insulating layer. An organic insulating material is formed on the insulating layer of the outside edge of the chip connecting portion. An anisotropic conductive film (ACF) is then formed to cover the chip connecting portion and a portion of the organic insulating material. Finally, a semiconductor chip is hot-pressed on the ACF. The organic insulating material formed on the insulating layer is used to prevent the metal wires beneath the insulating layer from occurring of corrosion. A semiconductor chip package structure is also provided.
    Type: Application
    Filed: October 4, 2012
    Publication date: October 24, 2013
    Applicant: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Chi-Chao LIU, Chih-Jui WANG, Long-Chi CHEN
  • Patent number: 8536717
    Abstract: A method of assembling an integrated circuit package is disclosed. The method comprises placing a die on a substrate of the integrated circuit package; coupling a plurality of wire bonds from a plurality of bond pads on the die to corresponding bond pads on the substrate; applying a non-conductive material to the plurality of wire bonds; and encapsulating the die and the plurality of wire bonds. An integrated circuit package is also disclosed.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: September 17, 2013
    Assignee: XILINX, Inc.
    Inventors: Shin S. Low, Inderjit Singh
  • Patent number: 8525313
    Abstract: A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has conductive traces. The frequency extending device is disposed adjacent to the side of the chip and overlying the paddle. The lands are disposed adjacent to the side of the paddle. The contacts are connected to the conductive traces. The conductive traces are connected to the lands. The frequency extending device is configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by bond wires each having a length greater than or substantially equal to the distance between the contacts and the lands.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: September 3, 2013
    Assignee: Semtech Corporation
    Inventors: Binneg Y. Lao, William W. Chen
  • Patent number: 8525306
    Abstract: To suppress a short circuit between neighboring wires which is caused when the loop of a wire is formed into multiple stages in a semiconductor device in which a wiring board and one semiconductor chip mounted over a main surface thereof are electrically coupled with the wire. In a semiconductor device in which a chip is mounted on an upper surface of a wiring board and a bonding lead of the wiring board and a bonding pad of the chip are electrically coupled with wires, a short circuit between the neighboring wires is suppressed by making larger the diameter of the longest wire arranged in a position closest to a corner part of the chip than the diameter of the other wires.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: September 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yukinori Tashiro, Yoshinori Miyaki
  • Patent number: 8508024
    Abstract: A chip package structure for being disposed on a carrier includes a package substrate and a chip. The package substrate includes a laminated layer, a patterned conductive layer, a solder-mask layer, at least one outer pad and a padding pattern. The patterned conductive layer is disposed on a first surface of the laminated layer and has at least one inner pad. The solder resist layer is disposed on the first surface and has at least one opening exposed the inner pad. The outer pad is disposed on the solder resist layer, located within the opening, and is connected with the inner pad. The padding pattern is disposed on the solder resist layer. A height of the padding pattern relative to the first surface is greater than that of the outer pad. The chip is located on a second surface of the laminated layer and electrically connected to the package substrate.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: August 13, 2013
    Assignee: VIA Technologies, Inc
    Inventor: Wen-Yuan Chang
  • Patent number: 8497571
    Abstract: A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a top surface, a bottom surface and a plurality of apertures formed at the bottom surface, wherein the bottom surface of the insulating layer comprises a disposing area and a non-disposing area. Each of the apertures is located at the disposing area and comprises a lateral wall and a base surface. A first thickness is formed between the base surface and the insulating layer, a second thickness is formed between the top surface and the bottom surface, and the second thickness is larger than the first thickness. The chip disposed on the top surface comprises a chip surface and a plurality of bumps. The heat dissipation paste at least fills the apertures and contacts the base surface.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: July 30, 2013
    Assignee: Chipbond Technology Corporation
    Inventors: Chin-Tang Hsieh, Hou-Chang Kuo, Dueng-Shiu Tzou, Chia-Jung Tu, Gwo-Shyan Sheu
  • Patent number: 8487322
    Abstract: A luminous body comprises a transparent plastic moulding with indentations, and LED DIEs disposed within the indentations. One side of each LED DIE lies approximately flush with an upper side of the moulding, and each LED DIE is connected to an electricity supply via electrical conductors disposed on the moulding. A method for producing such a luminous body is also disclosed.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: July 16, 2013
    Assignee: Bayer Intellectual Property GmbH
    Inventors: Andrea Maier-Richter, Eckard Foltin, Michael Roppel, Peter Schibli
  • Patent number: 8481367
    Abstract: Provided is a method of manufacturing a circuit device in which a circuit element is resin-sealed with sealing resins formed integrally with each other. In the present invention, a resin sheet and a circuit board are housed in a cavity of a mold, and thereafter a first sealing resin formed of a tablet in melted form is injected into the cavity. At the time of injecting the first sealing resin, a second sealing resin formed of the resin sheet in melted form is not yet cured and is maintained in liquid form. Accordingly, the injected first sealing resin and the second sealing resin are mixed at the boundary therebetween, preventing the generation of a gap in the boundary portion and therefore preventing the deterioration of the moisture resistance and withstand voltage at the boundary portion.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 9, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Katsuyoshi Mino, Akira Iwabuchi, Ko Nishimura
  • Patent number: 8471372
    Abstract: A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, wherein the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a first insulating portion and a second insulating portion, the first insulating portion comprises a first upward surface, a first downward surface, a first thickness and a recess formed on the first downward surface, wherein the recess comprises a bottom surface. The second insulating portion comprises a second upward surface, a second downward surface and a second thickness larger than the first thickness. The trace layer is at least formed on the second insulating portion, the chip disposed on top of the substrate is electrically connected with the trace layer and comprises a plurality of bumps, and the heat dissipation paste is disposed at the recess.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: June 25, 2013
    Assignee: Chipbound Technology Corporation
    Inventors: Chin-Tang Hsieh, Hou-Chang Kuo, Dueng-Shiu Tzou, Chia-Jung Tu, Gwo-Shyan Sheu
  • Patent number: 8471271
    Abstract: Provided is a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes a package main body with a cavity, a plurality of light emitting diode chips, a wire, and a plurality of lead frames. The plurality of light emitting diode chips are mounted in the cavity. The wire is connected to an electrode of at least one light emitting diode chip. The plurality of lead frames are formed in the cavity, and at least one lead frame is electrically connected to the light emitting diode chip or a plurality of wires.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: June 25, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Won-Jin Son
  • Patent number: 8466449
    Abstract: There is provided a nitride semiconductor device including: an n-type nitride semiconductor layer; a p-type nitride semiconductor layer; and an active layer formed between the n-type and p-type nitride semiconductor layers, the active layer including a plurality of quantum well layers and at least one quantum barrier layer deposited alternately with each other, wherein the active layer includes a first quantum well layer, a second quantum well layer formed adjacent to the first quantum well layer toward the p-type nitride semiconductor layer and having a quantum level higher than a quantum level of the first quantum well layer, and a tunneling quantum barrier layer formed between the first and second quantum well layers and having a thickness enabling a carrier to be tunneled therethrough.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: June 18, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo Min Lee, Hee Seok Park, Jae Woong Han, Seong Suk Lee, Cheol Soo Sone
  • Patent number: 8461669
    Abstract: An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: June 11, 2013
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Eric Yang, Jinghai Zhou, Hunt Hang Jiang
  • Publication number: 20130134567
    Abstract: The present invention relates to the field of semiconductor package structures, and more specifically to a lead frame and a semiconductor package structure thereof. In one embodiment, a lead frame can include a plurality of parallel-arrayed lead fingers with a plurality of grooves situated on surfaces of the lead fingers, where the depths of the grooves can be smaller than the thickness of the lead fingers. In one embodiment, a flip chip semiconductor package structure can include a chip, a group of bumps, and the above-described lead frame. The first surfaces of the bumps can be coupled to the front surface of the chip, and the second surfaces of the bumps can be coupled to the upper surface of the lead frame.
    Type: Application
    Filed: November 12, 2012
    Publication date: May 30, 2013
    Applicant: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Silergy Semiconductor Technology (Hangzhou) L
  • Patent number: 8446005
    Abstract: A semiconductor device includes: a first transistor; a second transistor; an interlayer insulating film covering the transistors; a rectangular-shaped first bus formed on the interlayer insulating film and connected to first source/drain regions; a rectangular-shaped second bus formed on the interlayer insulating film with spacing from the first bus and connected to third source/drain regions; an inter-bus interconnect formed between the first and second buses for connecting these buses; a first contact pad provided on the first bus, to which a wire is connected; and a second contact pad provided on the second bus, to which a wire is connected. The inter-bus interconnect is in contact with part of the side of the first bus facing the second bus and part of the side of the second bus facing the first bus. The first and second contact pads are respectively in contact with part of the first and second buses.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: May 21, 2013
    Assignee: Panasonic Corporation
    Inventor: Tomoharu Yokouchi
  • Publication number: 20130099367
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation.
    Type: Application
    Filed: June 19, 2012
    Publication date: April 25, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua, Emmanuel Espiritu
  • Publication number: 20130069212
    Abstract: A semiconductor device in which a flip chip is mounted which can change a potential of a specific terminal without changing a design of a package external. The semiconductor device includes an IC chip having a bump for an external terminal, and a package in which the IC chip is mounted. The package includes an inner lead portion that supplies a first signal or a second signal to the external terminal. The inner lead portion has a pattern of an inner lead that can change a signal to be supplied to the external terminal to the first signal or the second signal according to a position at which the IC chip is mounted.
    Type: Application
    Filed: July 27, 2012
    Publication date: March 21, 2013
    Inventor: Azuma ARAYA
  • Publication number: 20130062746
    Abstract: A semiconductor device includes a substrate having a first side and a second side, the second side having a mounting location for at least one semiconductor element, and the first side having a plurality of locations electrically connected to locations on the second side. A plurality of electrically conductive interconnects are provided at the locations, each having a first end attached at the location and a second end spaced from the substrate, and an encapsulant partially encapsulates the plurality of interconnects and has a surface lying in a first plane. The second ends are located on the side of the first plane opposite from the substrate first side, an annular space in the encapsulant surrounds each of the plurality of electrically conductive interconnects, and the annular space has a bottom located between the first plane and the substrate first side. Also a method for making such a semiconductor device.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 14, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Mark Wendell Schwarz, Jianwen Xu
  • Publication number: 20130037917
    Abstract: A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices.
    Type: Application
    Filed: September 1, 2012
    Publication date: February 14, 2013
    Inventor: Yan Xun Xue
  • Patent number: 8368191
    Abstract: A semiconductor device of a multi-pin structure using a lead frame is provided. The semiconductor device comprises a tab having a chip supporting surface, the chip supporting surface whose dimension is smaller than a back surface of a semiconductor chip, a plurality of leads arranged around the tab, the semiconductor chip mounted over the chip supporting surface of the tab, a plurality of suspending leads for supporting the tab, four bar leads arranged outside the tab so as to surround the tab and coupled to the suspending leads, a plurality of wires for coupling between the semiconductor chip and the leads, and a sealing body for sealing the semiconductor chip and the wires with resin, with first slits being formed respectively in first coupling portions of the bar leads for coupling with the suspending leads.
    Type: Grant
    Filed: November 28, 2010
    Date of Patent: February 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Noriyuki Takahashi
  • Publication number: 20130026614
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T.
    Type: Application
    Filed: March 21, 2012
    Publication date: January 31, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Sheng-Yu Wu, Yen-Liang Lin
  • Publication number: 20130020689
    Abstract: A Quad Flat Pack (QFP) device includes a semiconductor die attached to a flag of a lead frame. Bonding pads of the die are electrically connected to inner and outer rows of leads of the lead frame with bond wires. The die, die flag, bond wires and portions of the inner and outer leads are covered with a mold compound, which defines a package body. The outer leads are similar to the gull-wing leads of a conventional QFP device while the inner leads form contact points at a bottom surface of the package body. A cut is performed on an inner side of the inner leads to separate the inner leads from the die pad.
    Type: Application
    Filed: June 6, 2012
    Publication date: January 24, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Penglin Mei, Liwei Liu, Dehong Ye