Additional Leads Being Wiring Board (epo) Patents (Class 257/E23.036)
  • Patent number: 10707153
    Abstract: A semiconductor device includes: one or more semiconductor dice, a die pad supporting the semiconductor die or dice, a package molded onto the semiconductor die or dice supported by said die pad, wherein the die pad is exposed at the surface of the package, and the exposed die pad with an etched pattern therein to form at least one electrical contact land in the die pad.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 7, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 9465117
    Abstract: A radiation detecting apparatus includes a radiation detector including a scintillator for converting radiation that has passed through a subject into visible light, and a substantially rectangular shaped photoelectric transducer board for converting the visible light into radiographic image information, and a casing housing the radiation detector therein. The casing is of a substantially rectangular shape and includes an upper plate, a lower plate, and a frame interconnecting the upper plate and the lower plate. The frame has a recess defined therein, which faces and is spaced from a corner of the photoelectric transducer board, the recess being concave in a direction away from the corner.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: October 11, 2016
    Assignee: FUJIFILM Corporation
    Inventor: Hiroshi Nakahashi
  • Patent number: 9363900
    Abstract: A mounting device in which a conductive film that is not separated is formed on a resin substrate. Alloy thin films, which contain more than 50% by atom of Cu, 5% by atom or more and 30% by atom or less of Ni, and 3% by atom or more and 10% by atom or less of Al, are formed on a base consisting of a resin so as to be brought into contact with a surface of the base by sputtering. Conductive films consisting of copper are formed on surfaces of the alloy thin films so as to obtain a wiring film having a two-layer structure and a metal plug filled in a connection hole. The alloy thin films have high adhesion to a resin; and hence, the wiring film and the metal plug are not separated.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: June 7, 2016
    Assignee: ULVAC, INC.
    Inventors: Satoru Takasawa, Shuhei Ichikawa, Isao Sugiura, Satoru Ishibashi, Junichi Nitta
  • Patent number: 9035472
    Abstract: In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takaharu Nagasawa
  • Patent number: 8999763
    Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at least one topological feature, such as a depression in a surface of the interposer, a die coupled to the surface of the interposer, and an encapsulant material formed over the die and the interposer, and disposed in the at least one depression to resist movement of the encapsulant material relative to the interposer. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: April 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Steven Eskildsen, Aravind Ramamoorthy
  • Patent number: 8975742
    Abstract: A printed wiring board includes a substrate, a first buildup formed on a first surface of the substrate and including the outermost conductive layer, and a second buildup layer formed on a second surface of the substrate and including the outermost conductive layer. The outermost layer of the first buildup has pads positioned to connect a semiconductor component, the first buildup has a component mounting region directly under the component such that the outermost layer of the first buildup has a portion in the region, the outermost layer of the second buildup has a portion directly under the region, and the portions satisfy the ratio in the range of from 1.1 to 1.35, where the ratio is obtained by dividing a planar area of the portion of the second buildup by a planar area of the portion of the first buildup.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 10, 2015
    Assignee: IBIDEN Co., Ltd.
    Inventors: Toshiki Furutani, Takeshi Furusawa
  • Patent number: 8975738
    Abstract: A structure may include a spacer element overlying a first portion of a first surface of a substrate; first terminals at a second surface of the substrate opposite the first surface; and second terminals overlying a third surface of the spacer element facing away from the first surface. Traces extend from the second terminals along an edge surface of the spacer element that extends from the third surface towards the first surface, and may be electrically coupled between the second terminals and the first terminals or electrically conductive elements at the first surface. The spacer element may at least partially define a second portion of the first surface, which is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some of the conductive elements are at the second portion and may permit connection with such microelectronic element.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 8912639
    Abstract: Aspects of a method and system for configuring a transformer embedded in a multi-layer integrated circuit package are provided. In this regard, a windings ratio of a transformer embedded in a multi-layer IC package bonded to an IC may be configured, via logic, circuitry, and/or code in the IC, based on signal levels at one or more terminals of the transformer. The transformer may comprise a plurality of inductive loops fabricated in transmission line media. The integrated circuit may be flip-chip bonded to the multi-layer package. The IC may comprise a signal strength indicator enabled to measure signal levels input to or output by the transformer. The windings ratio may be configured via one or more switches in the IC and/or in the multi-layer package. The IC and/or the multi-layer package may comprise ferromagnetic material which may improve magnetic coupling of the transformer.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: December 16, 2014
    Assignee: Broadcom Corporation
    Inventor: Ahmadreza Rofougaran
  • Patent number: 8866277
    Abstract: A package substrate includes: a first conductive layer having plural first terminal pattern portions connected to a semiconductor part loaded on a first principal surface through plural first external connection conductors, which is formed on the first principal surface; a second conductive layer having plural second terminal patterns connected to a system substrate mounted on a second principal surface opposite to the first principal surface through a second external connection conductor, which is formed on the second principal surface; an intermediate conductive layer formed between the first conductive layer and the second conductive layer; interlayer insulating layers formed between the first conductive layer and the intermediate conductive layer as well as between the second conductive layer and the intermediate conductive layer; and plural interlayer connection conductors stacked for connecting between the first conductive layer and the second conductive layer so as to pierce through the interlayer insu
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: October 21, 2014
    Assignee: Sony Corporation
    Inventor: Mitsuhiro Hanabe
  • Patent number: 8796832
    Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: August 5, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Susumu Baba, Masachika Masuda, Hiromichi Suzuki
  • Patent number: 8779602
    Abstract: There are provided steps of providing a dielectric layer and a wiring layer on a surface of a support to form an intermediate body, removing the support from the intermediate body to obtain a wiring board, and carrying out a roughening treatment over a surface of the support before the intermediate body forming step.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: July 15, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Kentaro Kaneko
  • Patent number: 8546922
    Abstract: A wiring board including a core substrate made of an insulative material and having a penetrating portion, a first interlayer insulation layer formed on the surface of the core substrate, a first conductive circuit formed on the surface of the first interlayer insulation layer, a first via conductor formed in the first interlayer insulation layer, and an electronic component accommodated in the penetrating portion of the core substrate and including a semiconductor element, a bump body mounted on the semiconductor element, a conductive circuit connected to the bump body, an interlayer resin insulation layer formed on the conductive circuit, and a via conductor formed in the interlayer resin insulation layer. The first via conductor has a tapering direction which is opposite of a tapering direction of the via conductor in the electronic component.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: October 1, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Toshiki Furutani, Daiki Komatsu, Nobuya Takahashi, Masatoshi Kunieda, Naomi Fujita, Koichi Tsunoda, Minetaka Oyama, Toshimasa Yano
  • Patent number: 8502398
    Abstract: There are provided steps of providing a dielectric layer and a wiring layer on a surface of a support to form an intermediate body, removing the support from the intermediate body to obtain a wiring board, and carrying out a roughening treatment over a surface of the support before the intermediate body forming step.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: August 6, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Kentaro Kaneko
  • Patent number: 8471392
    Abstract: An image pickup apparatus according to an embodiment includes: an image pickup device chip including an image pickup device formed on a first principal surface thereof and an external terminal for the image pickup device formed on a second principal surface thereof; a wiring board including a distal end portion including a connection pad, a flexure portion flexed at an angle of no less than 90 degrees, and an extending portion, the wiring board including a wiring layer extending from the distal end portion to the extending portion via the flexure portion, the wiring board being kept within a space immediately above the second principal surface of the image pickup device chip; a bonding layer that joins the second principal surface of the image pickup device chip and the distal end portion of the wiring board; and a bonding wire that electrically connects the external terminal and the connection pad.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: June 25, 2013
    Assignee: Olympus Corporation
    Inventor: Kazuaki Kojima
  • Publication number: 20130140687
    Abstract: According to one embodiment, provided is a semiconductor device including a lower layer wiring, and an upper layer wiring that is drawn in the same direction as a direction in which the lower layer wiring is drawn. Intermediate wirings include at least a first intermediate wiring and a second intermediate wiring. Conductors include at least a plurality of first conductors connecting between the lower layer wiring and the first intermediate wiring, a plurality of second conductors connecting between the upper layer wiring and the second intermediate wiring, and a plurality of third conductors which connect between the first intermediate wiring and the second intermediate wiring, and are less in number than the first conductors or the second conductors on a drawn side of the lower layer wiring and the upper layer wiring.
    Type: Application
    Filed: August 28, 2012
    Publication date: June 6, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoki WAKITA, Shigeyuki HAYAKAWA
  • Patent number: 8390105
    Abstract: A lead frame substrate, including: a metal plate having a first surface and a second surface; a semiconductor element mount portion and a semiconductor element electrode connection terminal that are formed on the first surface; an external connection terminal formed on the second surface and electrically connected to the semiconductor element electrode connection terminal; a conducting wire that connects the semiconductor element electrode connection terminal and the external connection terminal to each other; a resin layer formed on the metal plate; a hole portion that is partly formed in the second surface of the metal plate and does not penetrate the metal plate; and a plurality of protrusions that are formed on a bottom surface of the hole portion and protrude in a direction away from the metal plate, the protrusions having a height lower than a position of the second surface, not being in electrical conduction with the conducting wire, and being dispersed separately.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: March 5, 2013
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Junko Toda, Susumu Maniwa, Yasuhiro Sakai, Takehito Tsukamoto
  • Publication number: 20120286411
    Abstract: According to one embodiment, there is provided a semiconductor device including a wiring board, a semiconductor chip mounted on a first surface of the wiring board, first external electrodes provided on the first surface of the wiring board, second external electrodes provided on a second surface of the wiring board, and a sealing resin layer sealing the semiconductor chip together with the first external electrodes. The sealing resin layer has a recessed portion exposing a part of each of the first external electrodes. The plural semiconductor devices are stacked to form a semiconductor module with a POP structure. In this case, the first external electrodes of the lower-side semiconductor device and the second external electrodes of the upper-side semiconductor device are electrically connected.
    Type: Application
    Filed: March 16, 2012
    Publication date: November 15, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Watanabe, Takashi Imoto, Naoto Takebe, Yuuki Kuro, Yusuke Doumae, Katsunori Shibuya, Yoshimune Kodama, Yuji Karakane, Masatoshi Kawato
  • Patent number: 8293547
    Abstract: An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: October 23, 2012
    Assignee: Xilinx, Inc.
    Inventors: James Karp, Steven P. Young, Bernard J. New, Scott S. Nance, Patrick J. Crotty
  • Patent number: 8258608
    Abstract: In a lead frame used for manufacturing a semiconductor device by forming a circuit pattern group including unit lead frames having plural upper side terminal parts in the periphery of a semiconductor element mounting region in one line or plural lines and an outer frame surrounding the circuit pattern group in a state of having a gap in a lead frame material and then mounting a semiconductor element every the unit lead frame and carrying out necessary wiring and enclosing the entire surface of the circuit pattern group in which the semiconductor element is mounted and a part of the outer frame with a resin from an upper surface side and further etching from a lower surface side and forming lower side terminal parts joined to the upper side terminal parts of the circuit pattern group, the circuit pattern group and the outer frame are had and the inner edge of the outer frame is formed in an uneven portion in plan view and bonding between the resin and the outer frame is enhanced.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: September 4, 2012
    Assignee: Mitsui High-Tec, Inc.
    Inventor: Keiji Takai
  • Patent number: 8232634
    Abstract: A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: July 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Noriyuki Takahashi, Mamoru Shishido
  • Patent number: 8198714
    Abstract: Aspects of a method and system for configuring a transformer embedded in a multi-layer integrated circuit package are provided. In this regard, a windings ratio of a transformer embedded in a multi-layer IC package bonded to an IC may be configured, via logic, circuitry, and/or code in the IC, based on signal levels at one or more terminals of the transformer. The transformer may comprise a plurality of inductive loops fabricated in transmission line media. The integrated circuit may be flip-chip bonded to the multi-layer package. The IC may comprise a signal strength indicator enabled to measure signal levels input to or output by the transformer. The windings ratio may be configured via one or more switches in the IC and/or in the multi-layer package. The IC and/or the multi-layer package may comprise ferromagnetic material which may improve magnetic coupling of the transformer.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: June 12, 2012
    Assignee: Broadcom Corporation
    Inventor: Ahmadreza Rofougaran
  • Publication number: 20120091572
    Abstract: The semiconductor package includes a package wiring board having an element housing recessed portion on its top surface to house a semiconductor element; multiple side electrodes which are arranged on the outer side surface of the package wiring board and soldered to multiple motherboard electrodes arranged on a motherboard; a semiconductor element fixed onto the bottom surface of the element housing recessed portion; and an element electrode arranged on the bottom of the element housing recessed portion and electrically connected to the semiconductor element and the side electrodes. The package wiring board has a multilayered structure in which woven fabric and a resin adhesive layer are alternately laminated, and the resin adhesive layer is formed of a resin adhesive that contains inorganic filler particles.
    Type: Application
    Filed: June 22, 2009
    Publication date: April 19, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tsuneo Hamaguchi, Ikio Sugiura, Hiroo Sakamoto, Masaki Iwata, Takashi Shirase, Takashi Okamuro
  • Publication number: 20120068322
    Abstract: A package substrate includes: a first conductive layer having plural first terminal pattern portions connected to a semiconductor part loaded on a first principal surface through plural first external connection conductors, which is formed on the first principal surface; a second conductive layer having plural second terminal patterns connected to a system substrate mounted on a second principal surface opposite to the first principal surface through a second external connection conductor, which is formed on the second principal surface; an intermediate conductive layer formed between the first conductive layer and the second conductive layer; interlayer insulating layers formed between the first conductive layer and the intermediate conductive layer as well as between the second conductive layer and the intermediate conductive layer; and plural interlayer connection conductors stacked for connecting between the first conductive layer and the second conductive layer so as to pierce through the interlayer insu
    Type: Application
    Filed: September 13, 2011
    Publication date: March 22, 2012
    Applicant: SONY CORPORATION
    Inventor: Mitsuhiro Hanabe
  • Patent number: 8115285
    Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: February 14, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Wen Chen, Yi-Shao Lai, Hsiao-Chuan Chang, Tsung-Yueh Tsai, Pao-Huei Chang Chien, Ping-Cheng Hu, Hsu-Yang Lee
  • Patent number: 8072052
    Abstract: Disclosed herein are a trench substrate and a method of manufacturing the same. The trench substrate includes a base substrate, an insulating layer formed on one side or both sides of the base substrate and including trenches formed in a circuit region and a dummy region positioned at a peripheral edge of the trench substrate, and a circuit layer formed in the trenches of the circuit region through a plating process and including a circuit pattern and vias. Thanks to formation of the trenches in the dummy region and the cutting region, deviation in thickness of a plating layer formed on the insulating layer in a plating process is improved upon.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: December 6, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Gwan Ko, Ryoichi Watanabe, Sang Soo Lee
  • Patent number: 8049314
    Abstract: An integrated circuit package system includes: providing a connection array; attaching a base integrated circuit adjacent the connection array; attaching a package integrated circuit over the base integrated circuit; attaching a package die connector to the package integrated circuit and the connection array; and applying a wire-in-film insulator over the package integrated circuit, the package die connector, the base integrated circuit, and the connection array, wherein the connection array is partially exposed.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: November 1, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Seng Guan Chow, Heap Hoe Kuan, Linda Pei Ee Chua, Rui Huang
  • Patent number: 8030743
    Abstract: A two tier power module has, in one form thereof, a PC board having upper and lower traces with an opening in the insulating material that contains a power device which has upward extending solder bump connections. An upper leadframe is mounted on the solder bumps and the upper tracks of the PC board. Vias in the PC board connect selected upper and lower traces. A control device is mounted atop the leadframe and wire bonded to the leadframe, and the assembly is encapsulated leaving exposed the bottom surfaces of the lower traces of the PC board as external connections. In another form the PC board is replaced by a planar leadframe and the upper leadframe has stepped sections which make connections with the planar leadframe, the bottom surfaces of the planar leadframe forming external connections of the module.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: October 4, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Margie T. Rios, Hua Yang, Yumin Liu, Tiburcio A. Maldo
  • Patent number: 8008759
    Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: August 30, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Erwin Victor Cruz, Maria Cristina B. Estacio
  • Publication number: 20110140105
    Abstract: A surface mount type semiconductor device is disclosed. The semiconductor device has testing lands on a lower surface of a wiring substrate with a semiconductor chip mounted thereon. Lower surface-side lands with solder balls coupled thereto respectively and testing lands with solder balls not coupled thereto are formed on a lower surface of a wiring substrate. To suppress the occurrence of contact imperfection between the testing lands and land contacting contact pins provided in a probe socket, the diameter of each testing land is set larger than the diameter of each lower surface-side land. Even when the wiring substrate is reduced in size, electrical characteristic tests using the testing lands can be done with high accuracy.
    Type: Application
    Filed: November 15, 2010
    Publication date: June 16, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuya MARUYAMA, Toshikazu ISHIKAWA, Jun MATSUHASHI, Takashi KIKUCHI
  • Patent number: 7936059
    Abstract: Broadly speaking, the present invention fills these needs by providing a lead frame package including a substrate stack having opposed sides, one of which includes a plurality of signal traces, with the remaining side including a ground plane. An integrated circuit is mounted to the substrate stack. The integrated circuit includes a plurality of bond pads. A plurality of leads is in electrical communication with a subset of the plurality of signal traces. A plurality of electrically conductive elements placing a sub-group of the plurality of bond pads in electrical communication with a sub-part of the plurality of electrically leads by being bonded signal traces of the subset, spaced-apart from the plurality of leads.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: May 3, 2011
    Assignee: Altera Corporation
    Inventor: Yuanlin Xie
  • Patent number: 7911038
    Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: March 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
  • Patent number: 7851896
    Abstract: A Quad Flat Non-leaded (QFN) chip package including a patterned conductive layer, a first solder resist layer, a chip, a plurality of bonding wires and a molding compound is provided. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface, wherein a part of the first surface is exposed by the first solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the first solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the chip and the bonding wires.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: December 14, 2010
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, Chun-Ying Lin, Shih-Wen Chou
  • Patent number: 7795071
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: September 14, 2010
    Assignee: Advanpack Solutions Pte Ltd.
    Inventors: Chew Hwee-Seng Jimmy, Ong Chee Kian, Abd. Razak Bin Chichik
  • Patent number: 7786563
    Abstract: An embodiment of the present invention is a technique to stack multiple devices using an interconnecting element. A board has a periphery and top and bottom surfaces. The top surface has top contact pads to attach to a first device. The bottom surface is milled down to form a cavity confined by vertical walls around the periphery. The cavity fits a second device. Bottom contact pads are formed on bottom side of the vertical walls. The bottom contact pads are raised with respect to the bottom side of the vertical walls. Traces internal to the board connect the bottom contact pads to the top contact pads.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: August 31, 2010
    Assignee: Virtium Technology, Inc.
    Inventors: Phan Hoang, Chinh Nguyen, Anthony Tran, Tung Dang
  • Patent number: 7768105
    Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: August 3, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Erwin Victor Cruz, Maria Cristina B. Estacio
  • Publication number: 20100123229
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an external interconnect; forming a first planar terminal adjacent to the external interconnect and non-planar to a portion the external interconnect; mounting a first integrated circuit over the first planar terminal; connecting the first integrated circuit with the external interconnect; and forming an encapsulation over the first planar terminal covering the first integrated circuit and with the external interconnect extending from a non-horizontal side of the encapsulation and with the first planar terminal coplanar with the adjacent portion of the encapsulation exposing the first planar terminal.
    Type: Application
    Filed: November 17, 2008
    Publication date: May 20, 2010
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Lionel Chien Hui Tay
  • Patent number: 7656032
    Abstract: A semiconductor chip mounting wiring board 2 includes an insulating resin substrate 5, a first conductive bump 12 formed on one side of the insulative resin substrate 5 to mount a semiconductor chip 3, a wiring pattern 15 extending from the first conductive bump 12 toward the periphery of the insulating resin substrate 5, a filled viahole 9 leading from the other side of the insulating resin substrate 5 to the wiring pattern 15, and a second conductive bump 13, or a conductive pad 19, positioned just above the filled viahole 9 and electrically connected to the viahole 9.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: February 2, 2010
    Assignee: Ibiden Co., Ltd.
    Inventors: Takashi Kariya, Masaya Nishikawa
  • Publication number: 20090293604
    Abstract: Subject matter disclosed herein may relate to packaging for multi-chip semiconductor devices as may be used, for example, in tire pressure monitoring systems.
    Type: Application
    Filed: May 29, 2008
    Publication date: December 3, 2009
    Applicant: Hong Kong Applied Science and Technology Research Institute Company Limited (ASTRI)
    Inventors: Man Lung Sham, Ziyang Gao, Chi Kuen Vincent Leung, Lap Wai Leung, Lourdito M. Olleres, Chang Hwa Chung
  • Patent number: 7626255
    Abstract: Provided is a device, an assembly comprising said device, a sub-assembly and an element suitable for use in the assembly. The device comprises a body of an electrically insulating material having a first side and an opposite second side, the body being provided with conductors according to a desired pattern, said conductors being anchored in the body. The body is provided with a through-hole extending from the first side to the second side of the body and having a surfacial area which is smaller on the first side than on the second side. Such a device can very suitably be used in an assembly comprising an element which is a sensor, preferably a chemical sensor, and particularly a biosensor.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: December 1, 2009
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Johannus Wilhelmus Weekamp, Menno Willem Jose Prins
  • Patent number: 7615853
    Abstract: The present invention provides a chip-stacked package structure with leadframe having multi-piece bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips stacked together and provided on the die pad, the plurality of chips and the plurality of inner leads arranged in rows facing each other being electrically connected with each other; and an encapsulant provided to cover the chip-stacked structure and the leadframe; wherein the leadframe comprises at least a bus bar provided between the plurality of inner leads arranged in rows facing each other and the die pad, the bus bar being formed by multiple pieces.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: November 10, 2009
    Assignees: CHIPMOS Technologies Inc., CHIPMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, Wu-Chang Tu
  • Publication number: 20090224383
    Abstract: A clip structure and semiconductor die package. The clip structure includes a first portion and a second portion, with a connecting structure located between the first and second portion. The clip structure is substantially planar. The semiconductor die package includes a semiconductor die located between a leadframe structure and a clip structure. Slots are formed within the molding material covering portions of the semiconductor die package. The slots are located between a first portion and the second portion of the clip structure, and the slot overlap with the semiconductor die.
    Type: Application
    Filed: March 7, 2008
    Publication date: September 10, 2009
    Inventors: Erwin Victor Cruz, Maria Cristina Estacio
  • Publication number: 20090127681
    Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first die-pad on which a semiconductor chip is mounted on a bottom surface of the first die-pad, a support plate disposed adjacent to a lateral surface of the first die-pad, a support prop protruding from the support plate, and supporting the first die-pad, and a package body that encapsulates the first die-pad, the semiconductor chip, and the support plate.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 21, 2009
    Applicant: Fairchild Korea Semiconductor Ltd.
    Inventors: Joon-seo Son, Seung-won Lim, O-seob Jeon
  • Publication number: 20090127683
    Abstract: An integrated circuit package system includes: providing a connection array; attaching a base integrated circuit adjacent the connection array; attaching a package integrated circuit over the base integrated circuit; attaching a package die connector to the package integrated circuit and the connection array; and applying a wire-in-film insulator over the package integrated circuit, the package die connector, the base integrated circuit, and the connection array, wherein the connection array is partially exposed.
    Type: Application
    Filed: May 23, 2008
    Publication date: May 21, 2009
    Inventors: Byung Tai Do, Seng Guan Chow, Heap Hoe Kuan, Linda Pei Ee Chua, Rui Huang
  • Publication number: 20090121344
    Abstract: A silicon interposer 30 being held between a wiring board 40 and a semiconductor element 60 to electrically connect the wiring board 40 to the semiconductor element 60, wherein through-hole electrodes 17 for electrically connecting the wiring board 40 to the semiconductor element 60 are each formed of a base section and a buffer section, and the buffer section is formed of a conductive material having an elastic coefficient lower than that of the conductive material of the base section, and a semiconductor device package 50 and a semiconductor device 70 incorporating the silicon interposer 30.
    Type: Application
    Filed: October 24, 2008
    Publication date: May 14, 2009
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Masahiro SUNOHARA
  • Publication number: 20090121345
    Abstract: A silicon interposer producing method comprising the steps of forming through holes 12 in a silicon wafer 11, forming an oxide coating 13 on the silicon wafer 11, providing a power feeding layer 14 for plating on one of the surfaces of the through holes 12, supplying a low thermal expansion filler 15 having a thermal expansion coefficient lower than the thermal expansion coefficient of the conductive material 16 of through-hole electrodes 17 to the through holes 12, filling the conductive material 16 into the through holes 12 by plating to form the through-hole electrodes 17, and removing the power feeding layer 14 for plating.
    Type: Application
    Filed: October 28, 2008
    Publication date: May 14, 2009
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Masahiro SUNOHARA
  • Patent number: 7514796
    Abstract: To prevent short-circuit due to contact of bonding wires each other and to make a semiconductor device compact. A semiconductor chip with a rectangular main surface may comprise: a first side composing the main surface; a second side opposed to the first side; a main electrode pad group composed of a plurality of main electrode pads, which plurality of main electrode pads is arranged on the main surface along the first side; a first electrode pad group composed of a plurality of first electrode pads, which plurality of first electrode pads is arranged between the first side and the main electrode pad group; a second electrode pad group composed of a plurality of second electrode pads, which plurality of second electrode pads is arranged on the main surface along the second side; a first interconnection connecting the main electrode pad with the first electrode pad; and a second interconnection connecting the main electrode pad with the second electrode pad.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: April 7, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yoshihiro Saeki
  • Patent number: 7511369
    Abstract: A three dimensional electronic module is disclosed. Conventional TSOP packages are modified to expose internal lead frame interconnects, thinned and stacked on a reroute substrate. The reroute substrate comprises conductive circuitry for the input and output of electrical signals from one or more TSOPs in the stack to a ball grid array pattern. The exposed internal lead frames are interconnected and routed on one or more side buses on the module to the reroute substrate for connection to external electronic circuitry. Alternatively, internal wire bonds or ball bonds may be exposed in the TSOP packages and routed to the side bus for interconnection to create a BGA scale module. One or more neolayers may also be bonded to a reroute substrate to create a BGA scale module.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: March 31, 2009
    Assignee: Irvine Sensors Corp.
    Inventors: Gann Keith, William E. Boyd
  • Patent number: 7479691
    Abstract: A power semiconductor module having surface-mountable flat external contact areas and a method for producing the same is disclosed. In one embodiment, the top sides of the external contacts form an inner housing plane, on which at least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the edge sides of the semiconductor chip as far as the inner housing plane whilst leaving free the source and gate contact areas on the top side of the semiconductor chip and also whilst partly leaving free the top sides of the corresponding external contacts. Arranged on the insulation layer is a connecting conductive layer between the source contact areas on the top side of the semiconductor chip and the top sides of the source external contacts, and also a gate connecting layer from the gate contact areas to the top side of the gate external contact.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: January 20, 2009
    Assignee: Infineon Technologies AG
    Inventors: Henrik Ewe, Stefan Landau, Klaus Schiess, Robert Bergmann
  • Patent number: 7473988
    Abstract: A wiring board includes a substrate core, ceramic capacitors and a built-up layer. The substrate core has a housing opening portion therein which opens at a core main surface. The ceramic capacitors are accommodated in the housing opening portion and oriented such that the core main surface and a capacitor main surface of each capacitor face the same way. The built-up layer includes semiconductor integrated circuit element mounting areas at various locations on a surface thereof. In the substrate core, each ceramic capacitor is respectively disposed in an area corresponding to each semiconductor integrated circuit element mounting area.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: January 6, 2009
    Assignee: NGK Spark Plug Co., Ltd
    Inventors: Kazuhiro Urashima, Shinji Yuri, Manabu Sato, Jun Otsuka
  • Publication number: 20080303127
    Abstract: A cap-less package comprises: a metallic die pad part; a submount mounted on the die pad part; an optical semiconductor element mounted on the submount; an insulating member fixed to the die pad part; a lead electrode inserted in the insulating member; and a wire connecting the lead electrode to the semiconductor optical element, wherein the submount, the optical semiconductor element, a portion of the lead electrode closer to the optical semiconductor element than to the insulating member, and the wire are located opposite the die pad part.
    Type: Application
    Filed: May 22, 2008
    Publication date: December 11, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Junji Fujino