Abstract: A cap-less package comprises: a metallic die pad part; a submount mounted on the die pad part; an optical semiconductor element mounted on the submount; an insulating member fixed to the die pad part; a lead electrode inserted in the insulating member; and a wire connecting the lead electrode to the semiconductor optical element, wherein the submount, the optical semiconductor element, a portion of the lead electrode closer to the optical semiconductor element than to the insulating member, and the wire are located opposite the die pad part.

Abstract: A stack of semiconductor dies is disclosed. A first stack level includes a first semiconductor die and at least one first support that are attached to a substrate surface. A second level includes a second semiconductor die and at least one second support that are attached to the active surface of the first semiconductor die and to a coplanar surface of the first support(s). A third level includes a third semiconductor die attached to the active surface of the second semiconductor die and to a coplanar surface of the second support(s). The second and third semiconductor dies do not overlap bond pads of the first and second semiconductor dies, respectively. An adhesive film overlies the entire inactive surface of the second and third semiconductor dies, and attaches the second and third semiconductor dies to the immediately underlying active surface and support(s).

Abstract: An integrated circuit package having a die pad with a first face and a second face, a plurality of inner leads, and a plurality of sides between the first face and the second face. The plurality of inner leads is disposed substantially co-planer with and substantially around the die pad. The package also comprises a plurality of outer leads disposed substantially co-planar with and substantially around the plurality of inner leads and the die pad, so that the sides of each of the plurality of outer leads are offset from the sides of each of the plurality of inner leads. A first adhesive layer disposed on the first face of the die pad and a second adhesive layer disposed on the first faces of each of the plurality of inner leads. An IC chip is coupled to the first face of the die pad through the first adhesive layer and to the plurality of inner leads through the second adhesive layer. The package further comprises wires linking the inner leads and outer leads to the IC chip.

Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.

Abstract: A wiring substrate (1) comprises an insulating base (10) with connection holes (11), buried conductors (12) provided in the connection holes (11) without reaching a rear surface of the insulating base (10), and wiring layers 14 connected to the buried conductors (12). The buried conductors (12) thicken the wiring layers (14), and can form aligning parts (110) on the rear surface of the connection holes (11) to be used for three-dimensional mounting structure. Each wiring layer (14) includes thin terminals (14A), wirings (14B) and thick electrodes (14C). Not only the terminals (14A) and wirings (14B) but also the buried conductors (12) are raised by the same manufacturing process. A semiconductor element (2) is attached to the electrodes (14C) of the wiring substrate (1).

Abstract: A relay board provided in a semiconductor device, including an entire main surface that is made of a conductive material. The relay board may further include a substrate made of the same material as at least one semiconductor element provided in the semiconductor device. The main surface of the relay board may be formed at an upper part of the substrate.

Abstract: In an electronic circuit device including a substrate including a front surface on which an electronic circuit element is mounted and a reverse surface opposite to the front surface in a thickness direction of the substrate, an electrically conductive terminal member electrically connected to the electronic circuit element, a lead frame extending perpendicular to the thickness direction to face the reverse surface in the thickness direction, and a sealing resin covering at least partially the electronic circuit element, substrate and lead frame while at least a part of the electrically conductive terminal member is prevented from being covered by the sealing resin, the substrate extends to project outward from an end of the lead frame in a transverse direction perpendicular to the thickness direction while the end of the lead frame is covered by the sealing resin.

Abstract: A semiconductor device is disclosed that includes a semiconductor element, a circuit board electrically connected to the semiconductor element, a heat dissipation member fixed to the first surface of the circuit board and thermally coupled to the semiconductor element, and an interposer provided to the second surface of the circuit board facing away from the heat dissipation member. The interposer is electrically connected to the circuit board. An opening is formed in the circuit board and the interposer so that the semiconductor element is thermally coupled directly to the heat dissipation member through the opening.

Abstract: In the stacked semiconductor package, on a first semiconductor chip, a second semiconductor chip is stacked offset such that a portion of the first semiconductor chip is exposed. At least one first conductor electrically connects the exposed portion of the first semiconductor chip to the second semiconductor chip. The first conductor may be formed such that the first conductor does not extend beyond a periphery of the first semiconductor chip. The first conductor electrically connects at least one bond pad on the first semiconductor chip with at least one bond pad on the second semiconductor chip, and a redistribution pattern electrically connects the bond pad on the second semiconductor chip to a differently positioned bond pad on the second semiconductor chip.

Abstract: To prevent short-circuit due to contact of bonding wires each other and to make a semiconductor device compact. A semiconductor chip with a rectangular main surface may comprise: a first side composing the main surface; a second side opposed to the first side; a main electrode pad group composed of a plurality of main electrode pads, which plurality of main electrode pads is arranged on the main surface along the first side; a first electrode pad group composed of a plurality of first electrode pads, which plurality of first electrode pads is arranged between the first side and the main electrode pad group; a second electrode pad group composed of a plurality of second electrode pads, which plurality of second electrode pads is arranged on the main surface along the second side; a first interconnection connecting the main electrode pad with the first electrode pad; and a second interconnection connecting the main electrode pad with the second electrode pad.

Abstract: A stack of semiconductor dies is disclosed. A first stack level includes a first semiconductor die and at least one first support that are attached to a substrate surface. A second level includes a second semiconductor die and at least one second support that are attached to the active surface of the first semiconductor die and to a coplanar surface of the first support(s). A third level includes a third semiconductor die attached to the active surface of the second semiconductor die and to a coplanar surface of the second support(s). The second and third semiconductor dies do not overlap bond pads of the first and second semiconductor dies, respectively. An adhesive film overlies the entire inactive surface of the second and third semiconductor dies, and attaches the second and third semiconductor dies to the immediately underlying active surface and support(s).

Abstract: Semiconductor leadframes are provided with selected coined and uncoined areas. The coined areas are arranged to coincide with connection sites for electrical couplings, and the uncoined areas are arranged to provide a secure mechanical bond between leadframe and die attach material or leadframe and encapsulant. Methods are disclosed for forming a leadframe including steps for providing a leadframe that has a die pad and leadfingers extending from the die pad, and coining a selected portion of the die pad using a high pressure coining tool configured to make contact with the selected portion of the die pad and to avoid contact with the remainder of the die pad. A leadframe coining tool is also disclosed for use in a high pressure press. The coining tool includes one or more contact area for coining a portion of the die pad, and at least one non-contact area, whereby a die pad of an aligned leadframe may be partially coined.

Abstract: A semiconductor device such as a COF or the like is provided on a semiconductor chip on a film-like shaped flexile wiring substrate on which a wiring pattern is formed. Between the semiconductor chip and the flexile wiring substrate, a sealing resin is filled for protecting the semiconductor chip. In the semiconductor device, a resin trace is 0.1 to 1.0 mm in width and 10 ?m in thickness, the resin trace being formed when applying the sealing resin along a longitudinal side of the semiconductor chip.

Abstract: A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, and an encapsulant at least partially covering the die, drain lead, gate lead and source lead.