For Devices Adapted For Rectifying, Amplifying, Oscillating, Or Switching, Capacitors, Or Resistors With At Least One Potential-jump Barrier Or Surface Barrier (epo) Patents (Class 257/E23.044)
Abstract: A new method to form RF devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A top metal level is defined overlying the substrate. The top metal level comprises pads and portions of planned RF devices. A first passivation layer is formed overlying the top metal level. The first passivation layer is patterned to selectively expose the pads and the parts of planned RF devices. A dielectric layer is formed overlying the top metal level and the first passivation layer. The dielectric layer is patterned to selectively expose the top metal level. An RF metal level is defined overlying the dielectric layer and the top metal level to thereby complete the RF devices. A second passivation layer is formed overlying the RF metal level, the dielectric layer, and the top metal level. The second passivation layer is patterned to expose the pads. The method is disclosed for damascene and non-damascene metal.
Type:
Grant
Filed:
August 26, 2004
Date of Patent:
February 27, 2007
Assignee:
Taiwan Semiconductor Manufacturing Company
Abstract: In a chip type solid electrolytic capacitor including a capacitor element and a packaging resin covering the capacitor element, the packaging resin has a mount surface and a side surface adjacent to the mount surface. A terminal is electrically connected to the capacitor element and coupled to the packaging resin. The terminal extends along the mount surface and the side surface to have an outer surface exposed from the packaging resin and to have an inner surface opposite to the outer terminal surface. The inner surface has a stepwise shape formed by forging.
Type:
Grant
Filed:
January 13, 2004
Date of Patent:
November 14, 2006
Assignees:
Nec Tokin Corporation, Nec Tokin Toyama, Ltd.
Abstract: Aspects of the invention provide a package for accommodating a piezoelectric resonator that can include more mounting electrodes than connecting electrodes of the piezoelectric resonator element. The mounting electrodes can be electrically connected with a wiring pattern. In the lower surface of a package body, there can be formed external terminals at the four corners thereof. The external terminals are bonded to a mounting board. The external terminals are electrically connected to the mounting electrodes, respectively. The external terminal is not connected electrically to either of the mounting electrodes. Therefore, positions of the external terminals for operating the piezoelectric resonator can be changed based on whether a pair of connecting electrodes of the piezoelectric vibration element is bonded to the mounting electrodes, or it is connected to the mounting electrodes. Accordingly, it can be possible to easily change positions of external terminals for connecting to a circuit on a board.
Abstract: An electrically isolated and thermally conductive double-sided pre-packaged IC component, stamped lead members, drain pads, source pads, gate runner, and a MOSFET, IGBT, etc. are positioned between a pair of ceramic substrate members. Layers of solderable copper material are directly bonded to the inner and outer surfaces of the substrate members.
Abstract: An electrically isolated and thermally conductive double-sided pre-packaged IC component, stamped lead members, drain pads, source pads, gate runner, and a MOSFET, IGBT, etc. are positioned between a pair of ceramic substrate members. Layers of solderable cooper material are directly bonded to the inner and outer surfaces of the substrate members.