Leads Being Also Applied On Sidewalls Or Bottom Of Substrate, E.g., Leadless Packages For Surface Mounting (epo) Patents (Class 257/E23.061)
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Patent number: 7982300Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.Type: GrantFiled: March 25, 2010Date of Patent: July 19, 2011Assignee: Aprolase Development Co., LLCInventors: Keith Gann, W. Eric Boyd
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Patent number: 7955893Abstract: Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.Type: GrantFiled: January 31, 2008Date of Patent: June 7, 2011Assignee: Alpha & Omega Semiconductor, LtdInventors: Tao Feng, François Hébert, Ming Sun, Yueh-Se Ho
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Patent number: 7952186Abstract: A semiconductor package includes a bare chip which has a plurality of external electrodes, a land grid array substrate having an edge, a first surface and a second surface. The first surface includes a first portion apart from the edge and a second portion adjacent to the edge. The first portion of the first surface mounts the bare chip and is covered with a resin to seal the bare chip with the resin. The first portion of the first surface and the second surface includes a non-sealed region which is not covered with the resin. A plurality of first electrodes are arranged on the non-sealed region and connected to the external electrodes and a plurality of second electrodes are arranged on the second surface and connected to the external electrodes.Type: GrantFiled: February 14, 2008Date of Patent: May 31, 2011Assignee: Renesas Electronics CorporationInventor: Kou Sasaki
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Patent number: 7911043Abstract: Provided are wafer level package with a sealing line that seals a device and includes electroconductive patterns as an electrical connection structure for the device, and a method of packaging the same. In the wafer level package, a device substrate includes a device region, where a device is mounted, on the top surface. A sealing line includes a plurality of non-electroconductive patterns and a plurality of electroconductive patterns, and seals the device region. A cap substrate includes a plurality of vias respectively connected to the electroconductive patterns and is attached to the device substrate by the sealing line. Therefore, a simplified wafer level package structure that accomplishes electric connection through electroconductive patterns of a sealing line can be formed without providing an electrode pad for electric connection with a device.Type: GrantFiled: May 22, 2008Date of Patent: March 22, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Ju Pyo Hong, Seog Moon Choi, Tae Hoon Kim, Job Ha, Seung Wook Park
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Patent number: 7911048Abstract: There is provided a wiring substrate. The wiring substrate includes: a semiconductor substrate having a through hole; an insulating film provided to cover an upper surface, a lower surface and a first surface of the semiconductor substrate, the first surface corresponding to a side surface of the through hole; a through electrode provided in the through hole; a first wiring pattern disposed on an upper surface side of the semiconductor substrate and coupled to the through electrode; and a second wiring pattern disposed on a lower surface side of the semiconductor substrate and coupled to the through electrode. A first air gap is provided between the first wiring pattern and the insulating film formed on the upper surface, and a second air gap is provided between the second wiring pattern and the insulating film formed on the lower surface.Type: GrantFiled: June 19, 2008Date of Patent: March 22, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventor: Kei Murayama
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Patent number: 7880313Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.Type: GrantFiled: November 17, 2005Date of Patent: February 1, 2011Assignee: Chippac, Inc.Inventors: Jae Soo Lee, Geun Sik Kim, Sheila Alvarez, Robinson Quiazon, Hin Hwa Goh, Frederick Dahilig
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Patent number: 7879653Abstract: A leadless semiconductor package with an electroplated layer embedded in an encapsulant and its manufacturing processes are disclosed. The package primarily includes a half-etched leadframe, a chip, an encapsulant, and an electroplated layer. The half-etched leadframe has a plurality of leads and a plurality of outer pads integrally connected to the leads. The encapsulant encapsulates the chip and the leads and has a plurality of cavities reaching to the outer pads to form an electroplated layer on the outer pads and embedded in the cavities. Accordingly, under the advantages of lower cost and higher thermal dissipation, the conventional substrates and their solder masks for BGA (Ball Grid Array) or LGA (Land Grid Array) packages can be replaced. The leads encapsulated in the encapsulant have a better bonding strength and the electroplated layer embedded in the encapsulant will not be damaged during shipping, handling, or storing the semiconductor packages.Type: GrantFiled: August 10, 2008Date of Patent: February 1, 2011Assignees: Chipmos Technologies (Bermuda) Ltd., Chipmos Technologies Inc.Inventor: Hung-Tsun Lin
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Patent number: 7863737Abstract: An integrated circuit package system including providing a plurality of substantially identical package leads formed in a single row, and attaching bond wires having an offset on adjacent locations of the package leads.Type: GrantFiled: April 1, 2006Date of Patent: January 4, 2011Assignee: Stats Chippac Ltd.Inventors: Byoung Wook Jang, Hun Teak Lee, Kwang Soon Hwang
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Patent number: 7843049Abstract: There are constituted by a tab (1b) on which a semiconductor chip (2) is mounted, a sealing portion (3) formed by resin-sealing the semiconductor chip (2), a plurality of leads (1a) each having a mounted surface (1d) exposed to a peripheral portion of a rear surface (3a) of the sealing portion (3) and a sealing-portion forming surface (1g) disposed on an opposite side thereto, and a wire (4) for connecting a pad (2a) of the semiconductor chip (2) and a lead (1a), wherein the length (M) between inner ends (1h) of the sealing-portion forming surfaces (1g) of the leads (1a) disposed so as to oppose to each other is formed to be larger than the length (L) between inner ends (1h) of the mounted surfaces (1d). Thereby, a chip mounting region surrounded by the inner end (1h) of the sealing-portion forming surface (1g) of each lead (1a) can be expanded and the size of the mountable chip is increased.Type: GrantFiled: March 23, 2009Date of Patent: November 30, 2010Assignee: Renesas Electronics CorporationInventors: Yoshihiko Shimanuki, Yoshihiro Suzuki, Koji Tsuchiya
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Publication number: 20100276766Abstract: A device comprises a conductive substrate, a micro electromechanical systems (MEMS) structure, and a plurality of bond pads. The conductive substrate has a first side and a second side, the second side opposite the first side. The MEMS structure is formed over the first side of the conductive substrate. The plurality of bond pads are formed over the first side of the conductive substrate and electrically coupled to the first side of the conductive substrate. The conductive substrate and plurality of bond pads function to provide electrostatic shielding to the MEMS structure.Type: ApplicationFiled: April 29, 2009Publication date: November 4, 2010Inventors: Jinbang Tang, Lianjun Liu
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Patent number: 7825505Abstract: In one embodiment, a semiconductor package is formed to include a tamper barrier that is positioned between at least a portion of the connection terminals of the semiconductor package and an edge of the semiconductor package.Type: GrantFiled: November 11, 2009Date of Patent: November 2, 2010Assignee: Semiconductor Components Industries, LLCInventors: Phillip Celaya, James P. Letterman, Jr.
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Patent number: 7825524Abstract: A semiconductor system or sensor system in a housing which is butt-joined to a printed circuit board by soldering, at least some of the connecting surfaces not being soldered over their entire area, the connecting surfaces which are not soldered over their entire area being fixedly soldered in a first surface region to a section of a printed conductor, and in a second surface region the connecting surfaces not being fixedly connected to the printed circuit board, the securely soldered surface regions being situated closer to the semiconductor or sensor structure to be contacted than are the surface regions which are not fixedly connected to the printed circuit board.Type: GrantFiled: March 30, 2007Date of Patent: November 2, 2010Assignee: Robert Bosch GmbHInventors: Anton Doering, Stefan Mueller, Frieder Haag, Christoph Gahn
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Patent number: 7808103Abstract: Provided is a semiconductor package, and in particular a semiconductor package which is capable of electrically connecting to the outside without a lead.Type: GrantFiled: January 7, 2009Date of Patent: October 5, 2010Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Sung-min Park, Keun-hyuk Lee, Seung-Won Lim
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Patent number: 7795710Abstract: A redistributed lead frame for use in molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound (18) within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites (24) and routing circuits (26) electrically interconnecting the array of lands and the array of chip attached sites (24), (d) directly electrically interconnecting input/output pads on the at least one semiconductor device (28) to chip attach site members (24) of the array of chip attach sites (24), and (e) encapsulating the at least one semiconductor device (28), the array of chip attach sites (24) and the routing circuits (26) with a second molding compound (36).Type: GrantFiled: June 18, 2004Date of Patent: September 14, 2010Assignee: Unisem (Mauritius) Holdings LimitedInventors: Shafidul Islam, Romarico Santos San Antonio, Anang Subagio
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Patent number: 7790594Abstract: It is an object of the invention to provide an electronic part capable of forming an accurate gap between opposing substrates while also capable of decreasing the area of the electronic part, and a method of producing the same. A second electrode portion (6), having a core pattern (7) and a bump pattern (8) covering the surface thereof, is provided on a device substrate (1), the core pattern (7) is made of a material having hardness greater than that of the bump pattern (8), a first electrode portion (5) of the same material as the bump pattern (8) is provided on a bonding substrate (2), and a functional portion of the device substrate (1) and the first electrode portion (5) are electrically connected by direct bonding of the first electrode portion (5) and the bump pattern (8).Type: GrantFiled: November 20, 2008Date of Patent: September 7, 2010Assignee: Panasonic CorporationInventor: Kazushi Higashi
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Patent number: 7781888Abstract: The electric component includes at least a set of electrode terminals 2, 3, a semiconductor element 4 electrically connected with the set of electrode terminals, and a package 6 made of synthetic resin and sealing the electrode terminals and the semiconductor element with part of a lower surface of each of the electrode terminals exposed at a lower surface of the package. A cover layer 11 made of synthetic resin is formed to cover a cut surface of a tip of a connector lead remainder extending integrally outward from the each of the electrode terminals. Thus, disadvantages resulting from exposure of the cut surface of the tip of the connector lead remainder are eliminated.Type: GrantFiled: May 12, 2005Date of Patent: August 24, 2010Assignee: Rohm Co., Ltd.Inventors: Masahiko Kobayakawa, Masahide Maeda
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Patent number: 7777321Abstract: A method for interconnecting stacked layers containing integrated circuit die and a device built from the method is disclosed. The stacked layers are bonded together to form a module whereby individual I/O pads of the integrated circuit die are rerouted to at least one edge of the module. The rerouted leads terminate at the edge. Channels are formed in a surface of the module or on the surface of a layer whereby the rerouted leads are disposed within the channel. The entire surface of the edge or layer is metalized and a predetermined portion of the metalization removed such that the rerouted leads within each channel are electrically connected to each other.Type: GrantFiled: October 25, 2005Date of Patent: August 17, 2010Inventors: Keith D. Gann, W. Eric Boyd
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Patent number: 7777312Abstract: A semiconductor device is disclosed which includes a tab (5) for use in supporting a semiconductor chip (8), a seal section (12) as formed by sealing the semiconductor chip (8) with a resin material, more than one tab suspension lead (4) for support of the tab (5), a plurality of electrical leads (2) which have a to-be-connected portion as exposed to outer periphery on the back surface of the seal section (12) and a thickness reduced portion as formed to be thinner than said to-be-connected portion and which are provided with an inner groove (2e) and outer groove (2f) in a wire bonding surface (2d) as disposed within the seal section (12) of said to-be-connected portion, and wires (10) for electrical connection between the leads (2) and pads (7) of the semiconductor chip (8), wherein said thickness reduced portion of the leads (2) is covered by or coated with a sealing resin material while causing the wires (10) to be contacted with said to-be-connected portion at specified part lying midway between the outerType: GrantFiled: August 1, 2008Date of Patent: August 17, 2010Assignees: Renesas Technology Corp., Hitachi Yonezawa Electronics Co., Ltd.Inventor: Yoshihiko Shimanuki
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Patent number: 7776658Abstract: A semiconductor package is disclosed for packaging two adjacent semiconductor dies atop a circuit substrate. The dies are separated from each other along their longitudinal edges with an inter-die distance. An elevation-adaptive electrical connection connects a top metalized contact of die two to the bottom surface of die one while accommodating for elevation difference between the surfaces. The elevation-adaptive electrical connection includes: a) An L-shaped circuit route that is part of the circuit substrate, extending transversely from a die one longitudinal edge and placing an intermediate contact area next to a die two transverse edge. b) An interconnection plate connecting the top metalized contact area of die two with the intermediate contact area while being formed to accommodate for elevation difference between the contact areas.Type: GrantFiled: August 7, 2008Date of Patent: August 17, 2010Assignee: Alpha and Omega Semiconductor, Inc.Inventors: Kai Liu, Ming Sun
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Publication number: 20100148372Abstract: A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.Type: ApplicationFiled: February 22, 2010Publication date: June 17, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Warren M. Farnworth, Jerry M. Brooks
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Patent number: 7737545Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.Type: GrantFiled: February 13, 2006Date of Patent: June 15, 2010Assignee: Interconnect Portfolio LLCInventors: Joseph C. Fjelstad, Para K. Segaram, Thomas J. Obenhuber, Inessa Obenhuber, legal representative, Kevin P. Grundy
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Publication number: 20100140794Abstract: An apparatus comprises an integrated circuit die including a main body having a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer. The integrated circuit die also includes a bond pad on the main body, an edge contact at the peripheral edge surface and a line connecting the bond pad to the edge contact. The edge contact includes a bottom surface that substantially in the same plane as a surface of an encapsulant encasing the die. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: February 12, 2010Publication date: June 10, 2010Inventors: Chia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Lou, Eng Meow Koon, Ser Bok Leng, Chun Swee Kwang, So Chee Chung, Ho Kwok Song
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Patent number: 7700965Abstract: An LED (20) includes a base (24), a chip (21) and an encapsulation (22) made of a transparent material. The base has a concave depression (240). The chip is mounted on a bottom of the concave depression. The first encapsulation is received in the depression for sealing the chip. The chip includes a light emitting surface (210). The encapsulation includes a light output surface (25) over the light emitting surface. The light output surface defines a plurality of recesses (26). A mixture (29) formed by mixing another transparent material (27) and fluorescent powder (28) is filled in each of the recesses.Type: GrantFiled: July 10, 2008Date of Patent: April 20, 2010Assignee: Foxconn Technology Co., Ltd.Inventor: Chia-Shou Chang
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Patent number: 7695990Abstract: The invention relates to a method for producing an electrical leadframe (10), in particular for a light-emitting diode component, having at least one first electrical connection conductor (2) and at least one second electrical connection conductor (3).Type: GrantFiled: December 23, 2005Date of Patent: April 13, 2010Assignee: Osram Opto Semiconductors GmbHInventors: Joerg-Erich Sorg, Gertrud Kraeuter
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Patent number: 7692278Abstract: In some embodiments, an apparatus and a system are provided. The apparatus and the system may comprise a first integrated circuit die comprising a plurality of silicon vias and a first surface activated bonding site coupled to the plurality of silicon vias, and a second integrated circuit die comprising a second surface activated bonding site coupled to the first surface activated bonding site. The first surface activated bonding site may comprise a first clean metal and the second surface activated bonding site may comprise a second clean metal. If the first surface activated bonding site is coupled to the second surface activated bonding site respective metal atoms of the first activated surface activated bonding site are diffused into the second surface activated bonding site and respective metal atoms of the second activated surface activated bonding site are diffused into the first surface activated bonding site.Type: GrantFiled: December 20, 2006Date of Patent: April 6, 2010Assignee: Intel CorporationInventors: Shanggar Periaman, Kooi Chi Ooi, Bok Eng Cheah
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Patent number: 7666716Abstract: The present invention provides a semiconductor package and a fabrication method thereof. The method includes the steps of: providing a chip carrier module having a plurality of chip carriers, disposing a plurality of electrical connecting points on the chip carriers, performing chip mounting and molding on the chip carrier module to form an encapsulant encapsulating the semiconductor chip, exposing the electrical connecting points from the encapsulant; forming a patterned circuit layer on the encapsulant, electrically connecting the patterned circuit layer to the electrical connecting points, cutting and separating the chip carriers to form a plurality of semiconductor packages each having a circuit layer formed on the encapsulant such that the circuit layer provides extra electrical connecting points and thereby enhances electrical performance of electrical products. During a package stacking process, no package is limited by the design of another package below.Type: GrantFiled: February 9, 2009Date of Patent: February 23, 2010Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Han-Ping Pu, Cheng-Hsu Hsiao
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Patent number: 7663221Abstract: A package circuit board having a reduced package size. The package circuit board may include a semiconductor substrate in place of a printed circuit board. The package circuit board may further include a microelectronic chip mounted on the semiconductor substrate, the microelectronic chip having at least one of active and passive elements formed on the semiconductor substrate semiconductor substrate.Type: GrantFiled: January 5, 2005Date of Patent: February 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Lae Jang, Hee-Seok Lee
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Patent number: 7663218Abstract: A semiconductor component including a surface-mount housing and a method for producing the same are described herein. The semiconductor component includes lead pieces embedded into a plastic housing composition and arranged on an underside of the housing. External contact areas of the lead pieces are free of the plastic housing composition. A structured solderable coating is arranged on the external contact areas that have been kept free of the plastic housing composition, the coating includes a plurality of electrically conductive and mechanically elastic contact elements.Type: GrantFiled: August 16, 2007Date of Patent: February 16, 2010Assignee: Infineon Technologies AGInventors: Michael Bauer, Edward Fuergut, Simon Jerebic, Hermann Vilsmeier
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Patent number: 7649250Abstract: Provided are a semiconductor package and a method for manufacturing the same. The semiconductor package includes: a substrate having a top surface on which a lead is formed and a bottom surface opposite to the top surface; a semiconductor chip attached to the top surface of the substrate and having an active surface on which a chip pad is formed and a back surface opposite to the active surface; a redistribution pattern electrically connected to the chip pad and extending from the active surface to a lateral surface of the semiconductor chip; and an interconnector electrically connecting the redistribution to the lead on the lateral surface of the semiconductor chip.Type: GrantFiled: November 14, 2007Date of Patent: January 19, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Tae-Sung Park
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Patent number: 7633159Abstract: A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. A semiconductor device assembly or package includes a semiconductor device, a redistribution layer over an active surface of the semiconductor device, and dielectric material coating at least portions of an outer periphery of the semiconductor device. Peripheral sections of contacts are located on the peripheral edge and electrically isolated therefrom by the dielectric coating. The contacts may also include upper sections that extend partially over the active surface of the semiconductor device. The assembly or package may include any type of semiconductor device, including a processor, a memory device, and emitter, or an optically sensitive device.Type: GrantFiled: August 29, 2005Date of Patent: December 15, 2009Assignee: Micron Technology, Inc.Inventors: Suan Jeung Boon, Yong Poo Chia, Meow Koon Eng, Siu Waf Low
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Patent number: 7629620Abstract: A chip-type light-emitting semiconductor device includes: a substrate 4; a blue LED 1 mounted on the substrate 4; and a luminescent layer 3 made of a mixture of yellow/yellowish phosphor particles 2 and a base material 13 (translucent resin). The yellow/yellowish phosphor particles 2 is a silicate phosphor which absorbs blue light emitted by the blue LED 1 to emit a fluorescence having a main emission peak in the wavelength range from 550 nm to 600 nm, inclusive, and which contains, as a main component, a compound expressed by the chemical formula: (Sr1-a1-b1-xBaa1Cab1Eux)2SiO4 (0?a1?0.3, 0?b1?0.8 and 0<x<1). The silicate phosphor particles disperse substantially evenly in the resin easily. As a result, excellent white light is obtained.Type: GrantFiled: February 9, 2006Date of Patent: December 8, 2009Assignee: Panasonic CorporationInventors: Toshihide Maeda, Shozo Oshio, Katsuaki Iwama, Hiromi Kitahara, Tadaaki Ikeda, Hidenori Kamei, Yasuyuki Hanada, Kei Sakanoue
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Patent number: 7615851Abstract: An integrated circuit package system comprised by providing a leadframe including leads configured to provide electrical contact between an integrated circuit chip and an external electrical source. Configuring the leads to include outer leads, down set transitional leads, and down set inner leads. Connecting the integrated circuit chip electrically to the down set inner leads. Depositing an encapsulating material to prevent exposure of the down set inner leads.Type: GrantFiled: January 31, 2006Date of Patent: November 10, 2009Assignee: Stats Chippac Ltd.Inventors: Taesung Lee, Jae Soo Lee, Geun Sik Kim
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Patent number: 7592639Abstract: A chip-type light-emitting semiconductor device includes: a substrate 4; a blue LED 1 mounted on the substrate 4; and a luminescent layer 3 made of a mixture of yellow/yellowish phosphor particles 2 and a base material 13 (translucent resin). The yellow/yellowish phosphor particles 2 is a silicate phosphor which absorbs blue light emitted by the blue LED 1 to emit a fluorescence having a main emission peak in the wavelength range from 550 nm to 600 nm, inclusive, and which contains, as a main component, a compound expressed by the chemical formula: (Sr1-a1-b1-xBaa1Cab1Eux)2SiO4 (0?a1?0.3, 0?b1?0.8 and 0<x<1). The silicate phosphor particles disperse substantially evenly in the resin easily. As a result, excellent white light is obtained.Type: GrantFiled: October 25, 2006Date of Patent: September 22, 2009Assignee: Panasonic CorporationInventors: Toshihide Maeda, Shozo Oshio, Katsuaki Iwama, Hiromi Kitahara, Tadaaki Ikeda, Hidenori Kamei, Yasuyuki Hanada, Kei Sakanoue
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Patent number: 7582512Abstract: A semiconductor device includes a base plate, at least one first conductive layer carried by the base plate, and a semiconductor constructing body formed on or above the base plate, and having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constructing body. A plurality of second conductive layers are formed on the insulating layer and electrically connected to the external connecting electrodes of the semiconductor constructing body. A vertical conducting portion is formed on side surfaces of the insulating film and base plate, and electrically connects the first conductive layer and at least one of the second conductive layers.Type: GrantFiled: September 25, 2007Date of Patent: September 1, 2009Assignee: Casio Computer Co., Ltd.Inventor: Hiroyasu Jobetto
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Publication number: 20090140410Abstract: It is an object of the invention to provide an electronic part capable of forming an accurate gap between opposing substrates while also capable of decreasing the area of the electronic part, and a method of producing the same. A second electrode portion (6), having a core pattern (7) and a bump pattern (8) covering the surface thereof, is provided on a device substrate (1), the core pattern (7) is made of a material having hardness greater than that of the bump pattern (8), a first electrode portion (5) of the same material as the bump pattern (8) is provided on a bonding substrate (2), and a functional portion of the device substrate (1) and the first electrode portion (5) are electrically connected by direct bonding of the first electrode portion (5) and the bump pattern (8).Type: ApplicationFiled: November 20, 2008Publication date: June 4, 2009Applicant: Panasonic CorporationInventor: Kazushi Higashi
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Patent number: 7541668Abstract: Provided are a lead frame and a semiconductor package which allows reliable attachment of a small-sized semiconductor chip requiring a large number of leads to a board while providing high heat dissipation capability. The semiconductor package includes leads, each having a top plate extending inward from the outside edge of a frame and a plurality of pillar-shaped portions supporting the top plates, a semiconductor chip attached onto edge portions of the leads, wires connecting the leads with corresponding bonding pad on the semiconductor chip, and a molding material encapsulating the semiconductor chip and the wires and parts of the leads so as to the bottom surfaces of the leads are exposed. Further, some embodiments have a conductive pad exhibiting higher heat dissipation.Type: GrantFiled: June 27, 2006Date of Patent: June 2, 2009Assignee: Fairchild Korea Semiconductor, Ltd.Inventor: Yoon-hwa Choi
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Patent number: 7531381Abstract: The present invention provides a method for fabricating a quad flat no-lead package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.Type: GrantFiled: February 26, 2006Date of Patent: May 12, 2009Assignee: United Microelectronics Corp.Inventors: Jui-Hsiang Pan, Kuang-Shin Lee, Cheng-Kuang Sun
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Patent number: 7511369Abstract: A three dimensional electronic module is disclosed. Conventional TSOP packages are modified to expose internal lead frame interconnects, thinned and stacked on a reroute substrate. The reroute substrate comprises conductive circuitry for the input and output of electrical signals from one or more TSOPs in the stack to a ball grid array pattern. The exposed internal lead frames are interconnected and routed on one or more side buses on the module to the reroute substrate for connection to external electronic circuitry. Alternatively, internal wire bonds or ball bonds may be exposed in the TSOP packages and routed to the side bus for interconnection to create a BGA scale module. One or more neolayers may also be bonded to a reroute substrate to create a BGA scale module.Type: GrantFiled: February 22, 2005Date of Patent: March 31, 2009Assignee: Irvine Sensors Corp.Inventors: Gann Keith, William E. Boyd
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Patent number: 7501693Abstract: A low dropout (LDO) regulator device includes an LDO regulator integrated circuit housed in a 4-pin quad flat no-lead (QFN) package where the exposed die paddle is used as the ground terminal. The LDO regulator integrated circuit is formed on a semiconductor substrate. The 4-pin QFN package includes four perimeter lands connected to the input terminal, the output terminal, the enable terminal and the bypass terminal of the LDO regulator integrated circuit. The die paddle is to be electrically connected to a ground potential to allow the ground current of the LDO regulator integrated circuit to flow through the substrate and the die paddle of the 4-pin QFN package.Type: GrantFiled: November 17, 2006Date of Patent: March 10, 2009Assignee: Micrel, Inc.Inventors: George Chu, Martin Alter
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Patent number: 7495341Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.Type: GrantFiled: January 30, 2007Date of Patent: February 24, 2009Assignee: Tessera Technologies Hungary Kft.Inventors: Gil Zilber, Julia Aksenton, Vage Oganesian
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Patent number: 7494844Abstract: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit pattern on one side of a seed layer by use of a first dry film; (b) laminating a second dry film on the first dry film, the thickness of the second dry film corresponding to the depth of the cavity to be formed; (c) laminating a dielectric layer on an area outside of where the cavity is to be formed, the thickness of the dielectric layer corresponding to the depth of the cavity to be formed; (d) laminating on the seed layer a copper foil laminated master having a second circuit pattern; and (e) forming the cavity by peeling off the first dry film and the second dry film after removing the seed layer. The method in accordance with the present invention can mount a plurality of integrated circuits by reducing the thickness of a substrate on a package on package.Type: GrantFiled: September 21, 2006Date of Patent: February 24, 2009Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Hoe-Ku Jung, Myung-Sam Kang, Jung-Hyun Park
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Patent number: 7489027Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.Type: GrantFiled: January 4, 2008Date of Patent: February 10, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Hiroshi Iwasaki
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Patent number: 7489044Abstract: The present invention provides a semiconductor package and a fabrication method thereof. The method includes the steps of: providing a chip carrier module having a plurality of chip carriers, disposing a plurality of electrical connecting points on the chip carriers, performing chip mounting and molding on the chip carrier module to form an encapsulant encapsulating the semiconductor chip, exposing the electrical connecting points from the encapsulant; forming a patterned circuit layer on the encapsulant, electrically connecting the patterned circuit layer to the electrical connecting points, cutting and separating the chip carriers to form a plurality of semiconductor packages each having a circuit layer formed on the encapsulant such that the circuit layer provides extra electrical connecting points and thereby enhances electrical performance of electrical products. During a package stacking process, no package is limited by the design of another package below.Type: GrantFiled: November 1, 2006Date of Patent: February 10, 2009Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Han-Ping Pu, Cheng-Hsu Hsiao
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Publication number: 20080296750Abstract: A semiconductor device comprises a semiconductor chip having a photoelectric conversion function and conductor connecting with the semiconductor chip electrically. The semiconductor chip is sealed by resin. The resin comprises a first sealing resin, second sealing resin and third sealing resin. The second sealing resin has transparency for optical signal to the semiconductor chip and seals one side of the conductor. The third sealing resin seals the other side of the conductor and has a linear thermal expansion coefficient and thickness which may restrain at least a part of flexion of the conductor caused by the linear thermal expansion of the second sealing resin. The first sealing resin seals at least a part of the conductor, is sandwiched between the second sealing resin and the third sealing resin, and has a linear thermal expansion coefficient which may restrain at least a part of the linear thermal expansion of the second sealing resin.Type: ApplicationFiled: May 30, 2008Publication date: December 4, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Taibo NAKAZAWA
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Patent number: 7456496Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.Type: GrantFiled: May 12, 2005Date of Patent: November 25, 2008Assignee: Advanpack Solutions Pte LtdInventors: Tan Kim Hwee, Roman Perez, Kee Kwang Lau, Alex Chew, Antonio Dimaano
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Publication number: 20080272472Abstract: A thin semiconductor device difficult to cause breakage of a semiconductor chip is disclosed.Type: ApplicationFiled: July 2, 2008Publication date: November 6, 2008Inventors: Toshiyuki Hata, Hiroshi Sato
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Patent number: 7443021Abstract: An electronic component packaging structure, includes: circuit boards each having a wiring at least on a surface thereof; and an electronic component package secured between the circuit boards. The electronic component package includes at least one electronic component embedded within an electrical insulating encapsulation resin molded member made of an inorganic filler and a resin, the at least one electronic component being selected from an active component and a passive component, protruding electrodes are arranged on both faces of the electrical insulating encapsulation resin molded member, and the electronic component is connected electrically with at least a part of the protruding electrodes. This configuration allows circuit boards to be connected with each other and a high-density and high-performance structure.Type: GrantFiled: October 18, 2006Date of Patent: October 28, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Seiichi Nakatani
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Publication number: 20080251944Abstract: A semiconductor device has a semiconductor chip bonded to external connection pads or external connection terminals by flip-chip bonding and an underfill resin, and provides a semiconductor device which enables to lessen the warpage attributable to the underfill without involvement of an increase in the size of the semiconductor device. A low elastic resin member is disposed opposite to a surface of a semiconductor chip on which a plurality of electrode pads are formed, and an underfill resin is filled between the semiconductor chip and the low elastic resin member and between electrode pads and external connection pads.Type: ApplicationFiled: September 25, 2007Publication date: October 16, 2008Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Kiyoshi Oi
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Publication number: 20080237889Abstract: Provided is a semiconductor package, which may include a plurality of semiconductor chips to form a multi-stack semiconductor package (MSP), a method of fabricating the semiconductor package and the MSP, and a semiconductor package mold for fabricating the semiconductor package. The semiconductor package may include a first semiconductor chip package having a first substrate including a first surface having a center portion on which a first semiconductor chip is mounted, and at least one first boundary portion on which a plurality of conductive connection pad groups are formed, and a molding member including a body that covers the first semiconductor chip, and at least one extension that extends from the body towards a corner portion of the first surface of the first substrate, wherein the extension extends while avoiding the conductive connection pad group.Type: ApplicationFiled: April 2, 2008Publication date: October 2, 2008Inventors: Seung-yeol Yang, Sang-wook Park, Seung-jae Lee, Min-young Son
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Publication number: 20080231288Abstract: A semiconductor package includes a bare chip which has a plurality of external electrodes, a land grid array substrate having an edge, a first surface and a second surface. The first surface includes a first portion apart from the edge and a second portion adjacent to the edge. The first portion of the first surface mounts the bare chip and is covered with a resin to seal the bare chip with the resin. The first portion of the first surface and the second surface includes a non-sealed region which is not covered with the resin. A plurality of first electrodes are arranged on the non-sealed region and connected to the external electrodes and a plurality of second electrodes are arranged on the second surface and connected to the external electrodes.Type: ApplicationFiled: February 14, 2008Publication date: September 25, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Kou Sasaki