Abstract: A process for fabricating an integrated circuit package includes: selectively etching a leadframe strip to define a die attach pad and at least one row of contact pads; mounting a semiconductor die to one side of the leadframe strip, on the die attach pad; wire bonding the semiconductor die to ones of the contact pads; releasably clamping the leadframe strip in a mold by releasably clamping the contact pads; molding in a molding compound to cover the semiconductor die, the wire bonds and a portion of the contact pads not covered by the clamping; releasing the leadframe strip from the mold; depositing a plurality of external contacts on the one side of the leadframe strip, on the contact pads, such that the external contacts protrude from the molding compound; mounting at least one of an active and a passive component to a second side of said leadframe strip; and singulating to provide the integrated circuit package.

Abstract: A semiconductor package includes a semiconductor chip electrically connected to a plurality of leads arranged at the periphery of the semiconductor chip wherein each of the leads is bent to have a first portion exposed from the upper surface of the semiconductor package and a second portion exposed from the lower surface of the semiconductor package. Both of the first portion and the second portion of each lead can be utilized for making external electrical connection.

Abstract: A thin semiconductor device difficult to cause breakage of a semiconductor chip is disclosed.

Abstract: The present invention provides a semiconductor device that is inexpensive and can suppress signal transmission delay, and a manufacturing method thereof. The semiconductor device includes: a plurality of semiconductor chips; a semiconductor substrate that has, on the same surface thereof, a chip-to-chip interconnection for electrically connecting the plurality of semiconductor chips to each other, and a plurality of chip-connection pads connected to the chip-to-chip interconnection; and a wiring board that has a plurality of lands of which pitch is larger than a pitch of the chip-connection pads, wherein a major surface of each of the plurality of semiconductor chips is connected to the chip-connection pads via a first connector so that the plurality of semiconductor chips are mounted on the semiconductor substrate, and an external-connection pad is formed on the major surface other than a region facing the semiconductor substrate, and is connected to the land on the wiring board via a second connector.

Abstract: The present invention provide a wafer level chip size packaged chip device with a N-shape junction at which external leads electrically connect to peripheral arrayed compatible pads and a method of fabricating the same. In the wafer level chip size package, with such an n-shape junction instead of a conventional T-shape junction observed in Shellcase type wafer level chip size package technology, electrical connections between compatible pads and external leads are more reliable due to larger connection area than the counterpart in the T-shape junction.

Abstract: A semiconductor chip package may include a substrate, which may have bonding pads formed thereon. A semiconductor chip mounted on the substrate may have chip pads, and electrical connections for connecting the chip pads of the semiconductor chip to the substrate bonding pads. The semiconductor chip and the electrical connections on the substrate may be encapsulated, and a board attached to a portion of a surface of the substrate may not be encapsulated.

Abstract: A method of forming a leadframe package, a leadframe package formed according to the method, and a system incorporating the leadframe package. The leadframe package includes: a metallization layer comprising a paddle portion and a contact portion including contact leads; a die mounted onto the paddle portion; wirebonds connected between the die and respective ones of the contact leads; an overmold encapsulating the die, the paddle portion, the contact leads and the wirebonds; and a stiffening element encapsulated in the overmold and unconnected to electrical pathways within the leadframe package.

Abstract: A method for fabricating a leadframe with encapsulant guide is provided, including forming a die attach paddle. Leads are formed around at least portions of the die attach paddle, and encapsulant guides are formed angled on a plurality of the leads to push the leads outwardly when an encapsulant flows therepast.

Abstract: A manufacture method for semiconductor device (1, 21) including: a sealing-resin-layer forming step of forming a sealing resin layer (7) on a conductive member (13) formed at lest on one surface of a base substrate (11) formed with a plurality of wiring boards (2) therein, the conductive member spanning a boundary between a respective pair of adjoining wiring boards; and a step of moving the base substrate and a cutting tool (B) relative to each other in a manner to allow the cutting tool to pass through the base substrate from the other surface (2b) opposite from the one surface thereof toward the one surface thereof, thereby cutting the base substrate along the boundary between the respective pair of adjoining wiring boards.

Abstract: A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major surface, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/O contacts.

Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.

Abstract: A carrier-free semiconductor package and a fabrication method thereof are provided. The fabrication method includes the steps of: providing a carrier having a plurality of electrical contacts formed thereon; mounting at least one chip on the carrier; electrically connecting the chip to the electrical contacts via a plurality of bonding wires; forming a coating layer on each of the electrical contacts to encapsulate a bonded end of each of the bonding wires on the electrical contacts; performing a molding process to form an encapsulant for encapsulating the chip, the bonding wires and the electrical contacts; and removing the carrier, such that bottom surfaces of the electrical contacts are exposed from the encapsulant. This obtains a semiconductor package not having a carrier, and the coating layers can enhance adhesion between the electrical contacts and the encapsulant.

Abstract: A package for an integrated circuit (IC) die comprises a substrate and a lid. The substrate has an upper surface facing an interior of the package and a lower surface facing an exterior of the package. The upper surface of the substrate carries an IC die and provides electrical connections from the IC die to the lower surface of the substrate. The lid includes an outer lid and an inner lid. The inner lid is positioned over the IC die and is in thermal communication with the IC die. The inner lid is formed of a material suitable for conducting heat away from the IC die. The outer lid is attached to the upper surface of the substrate. A gap extends between the outer lid and inner lid.

Abstract: A package substrate includes signal pads provided on a main surface of the package substrate, footpads provided on a backside of the package substrate, and a sealing electrode provided on the main surface to surround the signal pads, the signal pads being electrically coupled to the footpads, the sealing electrode being insulated from the footpads.

Abstract: A support structure for a semiconductor device with peripherally disposed contacts includes a support substrate and at least one conductive column protruding from the support substrate. The at least one conductive column is configured to contact an outer connector on a peripheral edge of a semiconductor device that may be carried by the support structure. Optionally, the at least one conductive column may engage a feature of (e.g., a recess in) the peripherally disposed outer connector. The at least one conductive column may facilitate alignment of one or more semiconductor devices with the support substrate alignment of semiconductor devices relative to one another, or electrical connection between multiple semiconductor devices of other components.

Abstract: A process for fabricating a leadless plastic chip carrier includes selectively depositing a plurality of base layers on a first surface of a base of a leadframe strip to at least partially define a die attach pad and at least one row of contact pads. At least one further layer is selectively deposited on portions of the plurality of layers to further define at least the contact pads. The leadframe strip is then treated with a surface preparation. A semiconductor die is mounted to the die attach pad, followed by wire bonding the semiconductor die to at least the contact pads. Molding the semiconductor die, the wire bonds, the die attach pad and the contact pads on the surface of the leadframe strip, in a molding compound follows. The leadframe strip is etched to expose the contact pads and the die attach pad and the leadless plastic chip carrier is singulated from a remainder of the leadframe strip.

Abstract: A chip package having a lead frame, a chip, a plurality of bonding wires, and an insulation material is provided. The lead frame comprises a die pad, a plurality of leads, a plurality of signal pads and a plurality of non-signal pads. The signal pads and non-signal pads are underneath the signal leads and non-signal leads respectively. The non-signal pad is directly connected to a non-signal plane in the circuit board through its own vias. The signal pad has a structure which extends toward its adjacent non-signal pads. With the signal pad size enlarged, the capacitance between the non-signal plane in the circuit board and the signal pad is increased. The increased capacitance compensates the inductance induced from the bonding wires and improves the response of the signal propagation path for RF applications.

Abstract: A memory card comprising a leadframe having a die pad, and an insert having a plurality of contacts. Attached to the die pad is a semiconductor die which is electrically connected to the contacts of the insert. A body covers the die pad and the semiconductor die and partially covers the insert such that the contacts are exposed in an exterior surface of the body.

Abstract: A semiconductor chip package has a pillar body including at least three conductors insulated from each other by an insulating layer. The pillar body has a periphery that includes a plurality of mounting faces, with each mounting face defined by two adjacent conductors separated by a portion of the insulating layer. A plurality of semiconductor chips are attached on the mounting faces and selectively and electrically connected to the conductors. The semiconductor package of the present invention can be used in a semiconductor illuminator which has a housing having a reflecting cup, with the pillar body positioned inside the reflecting cup.

Abstract: A SAW apparatus is provided capable of realizing a small size without adverse affect while mounting the active surfaces of the semiconductor integrated circuit and the surface acoustic wave element. The SAW apparatus comprises a semiconductor IC and a SAW element. The semiconductor IC is flip-chip mounted on a bottom of the package, a non-active surface of the SAW element is bonded to a non-active surface of the semiconductor IC by using an adhesive, and an electrode portion arranged in the active surface is wire-bonded to an electrode pattern formed on the side walls of the package by using wires.

Abstract: Disclosed are a wafer level stacked package and its manufacturing method. As one example, in such a wafer level stacked package, a first semiconductor die is electrically connected to an upper surface of a substrate and a second semiconductor die is electrically connected to a lower surface of the substrate. That is, with respect to one substrate, semiconductor dies can be stacked on upper and lower surfaces of the substrate. Also, underfill is formed between the respective semiconductor dies and the substrate, thereby enhancing bonding forces between the respective semiconductor dies and the substrate. In addition to stacking the semiconductor dies, packages can be stacked with each other. That is, it is possible to stack a plurality of completed wafer level packages with each other in an up-and-down direction.

Abstract: A series of grooves are etched in a leadframe to be used in fabricating a group of semiconductor packages at locations where the leadframe will later be sawed to separate the semiconductor packages. In variations of the process, the grooves may be wider or narrower than the kerf of the saw cuts and may be formed on the side of the leadframe facing towards or away from the entry of the saw blade.

Abstract: The present invention discloses a chip-package structure and a fabrication process thereof, wherein a mount board is used as a support part, which is removed after completing the chip-package process, in order to promote the planarity, firmness and reliability of the entire package structure, to reduce the height of the entire package structure, to apply to the packaging of many kinds of semiconductors and to be used for various purposes.

Abstract: An electronic device comprises a semiconductor device having a package substrate with bumps. The semiconductor device is bonded to a mounting substrate by flip-chip bonding. A standoff member supports the package substrate on the mounting substrate with a predetermined standoff between the package substrate and the mounting substrate. The standoff member comprises a hole provided in the mounting substrate, an insertion portion provided to be contained in the hole, and a standoff portion provided to contact and support the package substrate such that the standoff portion has a height, equivalent to the predetermined standoff, on the mounting substrate and enables relative displacement of the package substrate to the mounting substrate.

Abstract: An embedded redistribution interposer is disclosed for providing footprint compatible chip package migration in which a die designed to be mounted into chip package is originally implemented using a first type of silicon platform and is subsequently redesigned for a second type of silicon platform, resulting in a redesigned die being a different size than the original die and no longer compatible for mounting in the chip package. According to the present invention, the embedded redistribution interposer includes a substrate having a plurality of bond pads on a top side thereof, wherein the redesigned die is mounted to the top of the interposer substrate, and the bottom of the interposer substrate is mounted to the substrate of the chip package. The redesigned die is connected to the redistribution interposer via a first set of electrical connections coupled between the die and the interposer bond pads.

Abstract: A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. Each lead of the lead frame has a first portion, a second portion and a third portion connecting the first portion and the second portion, wherein the first metal layer is not provided on the third portion. After a wire bonding step and an encapsulating step are conducted, a second metal layer is selectively plated on the first portions and the second portions of the leads and the die pads exposed from the bottom of the molded product. Then, the third portion of each lead is selectively etched away such that the first portion and the second portion are electrically isolated from each other. Finally, a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.

Abstract: A semiconductor package having improved adhesiveness between the chip paddle and the package body and having improved ground-bonding of the chip paddle. A plurality of through-holes are formed in the chip paddle for increasing the bonding strength of encapsulation material in the package body. A plurality of tabs are formed in the chip paddle may also be used alone or in conjunction with the through-holes to further increase the bonding strength of the encapsulation material in the package body. The tabs provide additional area for the bonding site to ground wires from the semiconductor chip by increasing the length of the chip paddle.

Abstract: The present invention relates to leads of a No-Lead type package which includes a chip having an active surface and a rear surface opposite the active surface. The active surface has a plurality of connection points with a plurality of leads arranged around the perimeter of the chip and a first and a second surface orthogonal to said first surface. A plurality of connection wires connect electrically the bonding pads of the chip to the first surface of the leads respectively. The package also includes a welding compound suitable for encapsulating the chip, the first surface of the leads and the bonding pads. The leads possess at least one hole in the second surface of the leads.