Abstract: A semiconductor structure includes a plurality of thermal vias and a heat dissipation layer disposed at a periphery of a back surface of a lower chip in a stacked-chip package. This arrangement improves solderability of a subsequently-bonded heat sink. Additionally, the thermal vias and the heat dissipation layer provide an improved thermal conduction path for enhancing heat dissipation efficiency of the semiconductor structure. A method for manufacturing the semiconductor structure is also provided.

Abstract: A package substrate includes an insulating substrate, a functional pattern and a main dummy pattern. A semiconductor chip is arranged on the insulating substrate. The functional pattern is formed on the insulating substrate. The functional pattern is electrically connected to the semiconductor chip. The main dummy pattern is formed on a portion of the insulating substrate at least of to the outside of and/or adjacent the functional pattern in a path of stress generated by a difference between thermal expansion coefficient of the insulating substrate and the semiconductor chip, so as to divert the stress away from the functional pattern. Thus, the stress is not concentrated on the functional pattern. As a result, damage to the functional bump caused by the stress is prevented.

Abstract: A semiconductor package structure including a substrate, a first chip, a second chip, and an interposer is provided. The substrate has a carrying surface and an opposite bottom surface. The first chip disposed on the carrying surface has a first surface and an opposite second surface. The second surface faces the substrate. The first chip has a plurality of through silicon vias (TSVs) and a plurality of first pads and second pads on the first surface. The first pads are electrically connected to the corresponding TSVs. The TSVs are electrically connected to the substrate. The second chip disposed above the first chip exposes a portion of the first surface. The second chip is electrically connected to the corresponding TSVs. The interposer is disposed on the first surface. Top surfaces of the interposer and the second chip are substantially aligned with each other. The interposer is bonded to the second pads.

Abstract: A semiconductor device includes a semiconductor die mounted over a package substrate. The die has a bond pad located thereover. A stud bump consisting substantially of a first metal is located on the bond pad. A wire consisting substantially of a different second metal is bonded to the stud bump.

Abstract: The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

Abstract: A lead-free solder alloy, a solder ball and an electronic member comprising a solder bump which enable the prevention of the occurrence of yellow discoloration on the surface of a solder after soldering, the surface of a solder bump after the formation of the bump in a BGA, and the surface of a solder bump after a burn-in test of a BGA. Specifically disclosed are: a lead-free solder alloy; a solder ball; and an electronic member comprising a solder bump, containing at least one additive element selected from Li, Na, K, Ca, Be, Mg, Sc, Y, lanthanoid series elements, Ti, Zr, Hf, Nb, Ta, Mo, Zn, Al, Ga, In, Si and Mn in the total amount of 1 ppm by mass to 0.1% by mass inclusive, with the remainder being 40% by mass or more of Sn.

Abstract: A stacked semiconductor device may have a plurality of chips stacked in three-dimension. The stacked semiconductor device may include a first semiconductor chip and at least one second semiconductor chip. The first semiconductor chip may include a plurality of first through silicon vias (TSVs). The at least one second semiconductor chip may include a plurality of second TSVs. The at least one second semiconductor chip may be stacked above the first semiconductor chip and may be thinner than the first semiconductor chip. Therefore, the stacked semiconductor device may have an improved reliability.

Abstract: A technology is provided for a packaging board adapted to mount a device capable of improving handleability and securing connection reliability. The packaging board includes: a pad electrode formed on a substrate; an insulating layer covering the substrate, having an opening at least in part in an area over the pad electrode; and a joint layer formed on the pad electrode inside the opening. The surface of the joint layer is lower than the top lip of the opening.

Abstract: Disclosed is a flip chip package maintaining alignment during soldering, primarily comprising a chip and a substrate. A plurality of bumps and at least an extruded alignment key are disposed on the active surface of the chip. The substrate has a plurality of bonding pads and at least an alignment base where the alignment base has a concaved alignment pattern corresponding to the extruded alignment key. When the chip is disposed on the substrate, the extruded alignment key is embedded into the concaved alignment pattern to achieve accurately align the bumps to the corresponding bonding pads. Therefore, even with the mechanical misalignment due to the accuracy of flip-chip die bonders and the transportation during reflow processes, the bumps of a chip still can accurately align to the bonding pads of the substrate to achieve accurate soldering which is especially beneficial to the mass production of MPS-C2 products.

Abstract: There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

Abstract: A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.

Abstract: A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; and an electrode pad formed above the interlayer dielectric. A connection section at which the first conductive layer and the second conductive layer are connected is disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and a reinforcing section is provided at the connection section.

Abstract: A package-on-package includes a package carrier; a semiconductor die assembled face-down to a chip side of the package carrier; a rewiring laminate structure between the semiconductor die and the package carrier; a plurality of bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier; and an IC package mounted on the package carrier. The IC package and the semiconductor die are at least partially overlapped.

Abstract: In a DC-DC converter, a multilayer wiring layer is provided on a silicon substrate, and a control circuit configured to control an input circuit and an output circuit is formed in the silicon substrate and the multilayer wiring layer. Moreover, a sealing resin layer covering the multilayer wiring layer and a connecting member connected to an uppermost wiring of the multilayer wiring layer, penetrating the sealing resin layer and having an upper end portion protruding from an upper surface of the sealing resin layer are provided. The upper end portion of the connecting member is formed from a protruding electrode. Horizontal cross-sectional area of the connecting member connected to terminals of the output circuit is larger than horizontal cross-sectional area of the connecting member connected to terminals of the control circuit.

Abstract: A semiconductor package is provided. The semiconductor package includes a substrate, a semiconductor element, a plurality of element contacts and a molding compound. The substrate includes a passivation layer and a plurality of substrate pads. Each substrate pad includes a protrusion and an embedded portion. The embedded portion is embedded in the passivation layer, and the protrusion projects from the passivation layer. The semiconductor element includes a plurality of under bump metallurgies (UBM) with recesses. The ratio of the width of each recess to the first width of the protrusion is larger than 1. The element contacts connect the UBM and the substrate pads. The molding compound covers the semiconductor element.

Abstract: A semiconductor structure includes multiple semiconductor devices on a substrate and a metal layer disposed over the semiconductor devices, the metal layer comprising at least a first trace and a second trace. A conductive pillar is disposed directly on and in electrical contact with the first trace of the metal layer, and a dielectric layer is selectively disposed between the metal layer and the conductive pillar, where the dielectric layer electrically isolates the second trace from the pillar. A moisture barrier surrounds the semiconductor devices around a periphery of the semiconductor structure, and extends from the substrate through the dielectric layer to the conductive pillar.

Abstract: A method of making a semiconductor device includes providing a substrate, and forming a first conductive layer over the substrate. A patterned layer is formed over the first conductive layer. A second conductive layer is formed in the patterned layer. A height of the second conductive layer is greater than a height of the first conductive layer. The patterned layer is removed. A first bump and a second bump are formed over the first and second conductive layers, respectively, wherein the second bump overlaps the first bump, and wherein an uppermost surface of the second bump is vertically offset from an uppermost surface of the first bump. Bond wires are formed on the first and second bumps. The bond wires are arranged in a straight configuration. Lowermost surfaces of the first conductive layer and second conductive layer are substantially coplanar.

Abstract: A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate.

Abstract: A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a surface of the chip and near two opposite long sides of the chip respectively. The ratio of the total contacting area of the first bumps to that of the second bumps is between 0.8 and 1.2. Thus, a pressure applied on the chip and the glass substrate of the displayer for connection can be uniformly exerted all over the chip, and the stability of the connection is therefore improved.

Abstract: Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.

Abstract: A conductive structure for a semiconductor integrated circuit is provided. The semiconductor integrated circuit has a substrate, a plurality of pads and a passivation layer. The pads are disposed on the substrate. The passivation layer extends over and covers a part of the substrate and a part of around each of the pads to define a plurality of openings, in which the conductive structure electrically connects to a corresponding pad of the pads through a corresponding opening of the openings. The conductive structure includes a buffering layer, an under bump metallurgy (UBM) layer and a bump. The buffering layer is formed on the passivation layer without fully blocking the corresponding opening. The UBM layer is substantially formed in the corresponding opening and electrically connects to the corresponding pad. Additionally, the UBM layer, formed under the bump, continuously extends over and covers a peripheral portion of the buffering layer.

Abstract: A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.

Abstract: A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.

Abstract: A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM.

Abstract: A semiconductor structure and a manufacture method thereof are disclosed. The semiconductor structure includes a semiconductor wafer having a plurality of semiconductor device dies, wherein each of the semiconductor device dies includes a die body, a metal wiring layer, a bump, and a metal layer. The metal wiring layer is formed on the die body while the bump is formed on the metal wiring layer during the semiconductor front-end-of-line (FEOL) process and protrudes from the die body. The metal layer is disposed on one side of the bump opposite to the metal wiring layer, wherein the activity of the metal layer is smaller than the activity of the bump. In this way, the semiconductor structure of the present invention is easy to be manufactured and the manufacture cost is also reduced.

Abstract: Semiconductor devices comprising a flip-chip having vias to connect front and back surfaces and a bondwire connected to the via or the back surface. Provision is made for packaging the flip-chip with a package substrate. Further aspects of the invention provide for inductance within the semiconductor device.

Abstract: An embodiment of an integrated circuit (IC) is described. This embodiment of the IC includes an interposer; a first die on an interposer, where the first die generates a global signal propagated through the interposer; and a second die on the surface of the interposer and coupled to the global signal. The first die and the second die each is configured to implement a same operating state concurrently in response to the global signal.

Abstract: Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Abstract: Disclosed is a package structure including a semiconductor chip disposed in a core board having a first surface and an opposite second surface. The package structure further includes a plurality of first and second electrode pads disposed on an active surface and an opposite inactive surface of the semiconductor chip respectively, the semiconductor chip having a plurality of through-silicon vias for electrically connecting the first and second electrode pads. As a result, the semiconductor chip is electrically connected to the two sides of the package structure via the through-silicon vias instead of conductive through holes, so as to enhance electrical quality and prevent the inactive surface of the semiconductor chip from occupying wiring layout space of the second surface of the core board to thereby increase wiring layout density and enhance electrical performance.

Abstract: A connection structure (package 10) has a first plate body 101 and a second plate body; in the first plate body 101, a wiring pattern having a plurality of connection terminals 102 is formed, and the second plate body has at least two connection terminals (electrode terminals 104) arranged facing the connection terminals of the first plate body 101. The connection terminals of the first and second plate bodies are connection terminals formed as projections on the surfaces of the first and second plate bodies. A conductive substance 108 is accumulated to cover at least a part of each side face of the connection terminals opposed to each other of the first and second plate bodies, and the connection terminals thus opposed are connected to each other via the conductive substance. The package thus formed is ready for a high-pin-count, narrow-pitch configuration of a next-generation semiconductor chip, and exhibits excellent productivity and reliability.

Abstract: A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Abstract: A semiconductor element and a fabrication method thereof. The method includes forming an encapsulating layer on a semiconductor silicon substrate having electrode pads and a passivation layer formed thereon, the encapsulating layer covering the electrode pads and a part of the passivation layer that surrounds the electrode pads; forming a covering layer on the passivation layer and the encapsulating layer with a plurality of openings that expose a part of the encapsulating layer; forming a bonding metallic layer on the part of the encapsulating layer that are exposed from the openings and electrically connecting the bonding metallic layer to the encapsulating layer, wherein the bonding metallic layer is not greater in diameter than the encapsulating layer; and forming a conductive element on the bonding metallic layer. The encapsulating layer provides a good buffering effect to prevent electrode pads from delamination or being broken caused by the direct stress from the conductive element.

Abstract: Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and an insulating film formed over the main surface, and a plurality of solder bumps each connected to the rearrangement wiring and arranged differently from the plurality of pads. The presence of a bevel cut surface obliquely continuous to the main surface and formed on a periphery of the main surface of the semiconductor chip prevents chipping.

Abstract: A chip fanning out method is disclosed. The chip fanning out method includes mounting a chip on a film, forming a plurality of outer lead bonds spatially arranged in a bump correspondence order on the film, forming a plurality of bumps spatially arranged in a bump arrangement order on the chip, and forming a plurality of wires to connect the plurality of outer lead bonds to the plurality of bumps according to the bump correspondence order, wherein the bump correspondence order is different from the bump arrangement order.

Abstract: A chip package includes a bump connecting said semiconductor chip and said circuitry component, wherein the semiconductor chip has a photosensitive area used to sense light. The chip package may include a ring-shaped protrusion connecting a transparent substrate and the semiconductor chip.

Abstract: A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.

Abstract: Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure.

Abstract: A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer.

Abstract: In one embodiment, a semiconductor device includes a circuit substrate, and first and second semiconductor chips mounted on it. The first semiconductor chip and the second semiconductor chip are flip-chip connected, and an underfill resin is filled between them. The underfill resin has a fillet portion. A thickness T1 of the first semiconductor chip and a thickness T2 of the second semiconductor chip satisfy a relationship of T1/(T1+T2)?0.6.

Abstract: A circuit board has an insulative layer including a first surface and a second surface opposite to the first surface. A plurality of electrically conductive patterns is formed on the first surface of the insulative layer. Conductive lands are formed in a die mounting region of the first surface of the insulative layer and electrically connected to one of the plurality of conductive patterns on the first surface. An extending pattern extends from the conductive lands to outside of the mounting region. A protective layer covers the first surface of the insulative layer and the electrically conductive patterns. A trench is formed in the protective layer to expose the conductive lands and the extending patterns.

Abstract: A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump.

Abstract: A semiconductor package includes a first board, a semiconductor chip having a first face and a second face at an opposite side to the first face, the semiconductor chip being mounted on the first board with the first face facing the first board, an insulating film provided on the second face of the semiconductor chip, and a second board stacked on the first board. A bump provided on a face of the second board facing the first board is connected to a pad provided on a face of the first board facing the second board and a gap is formed between the first board and the second board. The semiconductor chip and the insulating film are provided in the gap.

Abstract: In flip chip attach of electronic components, underfill is filled between the component and the substrate to alleviate, for example, thermal stress. In electronic component mounting using copper pillars conducted so far, filler contained in the underfill may cause separation in the process of heating and curing the resin. Disclosed is plating the surfaces of the copper pillars with solder. Mobilization of the filler charged in the underfill due to electric fields produced by local cells that are developed upon contact between dissimilar metals, is suppressed, and occurrence of crack at connection portions is obviated. Thus, connection reliability is increased.

Abstract: A semiconductor package includes a board, an under fill resin layer provided on the board, and a semiconductor chip having a first face and a second face at an opposite side to the first face, the semiconductor chip being flip-chip mounted on the board via the under fill resin layer with the first face facing the board. The semiconductor chip is covered with the under fill resin layer over the first face and from the first face to an edge part of the second face.

Abstract: A semiconductor device includes a semiconductor substrate having a plurality of electrode pads, a protective film covering the upper surface of the semiconductor substrate and having an opening so that the electrode pad is exposed therethrough, a metal film formed on the electrode pad exposed through the opening, and a bump formed on the metal film. The metal film includes a plurality of grooves radially formed from the center thereof toward the periphery thereof.

Abstract: A die package and a method for manufacturing the die package are provided.

Abstract: A semiconductor device includes a semiconductor integrated circuit device (1). In the semiconductor integrated circuit device (1), a semiconductor integrated circuit (5) is formed on a center of the surface of a semiconductor substrate (3), and a plurality of electrode terminals (71, 73, . . . ) are provided on the surface of the semiconductor substrate (3). A protection film (9) is provided on the surface of the semiconductor substrate (3) such that the surfaces of the electrode terminals (71, 73) are exposed. The electrode terminals (71, 73, . . . ) include an electrode terminal (73) having a thin portion (74). The surface of the thin portion (74) is located below the surfaces of the electrode terminals except for the electrode terminal (73) having the thin portion (74) among the electrode terminals (71, 73, . . . ).

Abstract: A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.

Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate with a face surface having a via therein and a back surface having a trench therein; filling the via with a conductive pillar; forming a recessed contact pad in the trench; filling the recessed contact pad partially with solder; and forming an under-bump metal having a base surface in electrical contact with the conductive pillar, and having sides that extend away from the face surface of the substrate and further extend beyond the base surface.

Abstract: A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.