Abstract: A wiring substrate and a semiconductor chip mounted on the wiring substrate are connected together via a bonding wire. The distance from each end of the semiconductor chip to a wire bond pad provided on the wiring substrate is smaller than the height of the semiconductor chip.

Abstract: In regard to a semiconductor device having a multilayered wiring board where a semiconductor chip is embedded inside, a technology which allows the multilayered wiring board to be made thinner is provided. A feature of the present invention is that, in a semiconductor device where bump electrodes are formed over a main surface (element forming surface) of a semiconductor chip embedded in a chip-embedded wiring board, an insulating film is formed over a back surface (a surface on the side opposite to the main surface) of the semiconductor chip. As a result, it becomes unnecessary to form a prepreg over the back surface of the semiconductor chip. Therefore, an effect of thinning the chip-embedded wiring board in which the semiconductor chip is embedded is obtained.

Abstract: A chip stack package includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The first semiconductor chip includes a first through silicon via that extends through the first semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and includes a second through silicon via that extends through the second semiconductor chip. The second through silicon via is disposed on the first through silicon via, and has a cross-sectional area smaller than that of the first through silicon via. The third semiconductor chip is stacked on the first semiconductor chip, and includes a third through silicon via that extends through the third semiconductor chip. The third through silicon via is disposed on the second through silicon via, and has a cross-sectional area smaller than that of the second through silicon via.

Abstract: A semiconductor package includes a semiconductor chip having a first surface, a second surface which faces away from the first surface, and through holes which pass through the first surface and the second surface; a dielectric layer formed on one or more of the first surface and the second surface and formed with grooves around the through holes on a fourth surface of the dielectric layer facing away from a third surface of the dielectric layer which is attached to the semiconductor chip; through-silicon vias filling the through holes; and bumps formed on the through-silicon vias and on portions of the dielectric layer around the through-silicon vias and filling the grooves.

Abstract: A semiconductor device has a substrate and first semiconductor die to the substrate. A plurality of vertically-oriented discrete electrical devices, such as a capacitor, inductor, resistor, diode, or transistor, is mounted over the substrate in proximity to the first semiconductor die. A first terminal of the discrete electrical devices is connected to the substrate. A plurality of bumps is formed over the substrate adjacent to the discrete electrical devices. An encapsulant is deposited over and between the first semiconductor die and substrate. A portion of the bumps and a second terminal of the discrete electrical devices is exposed from the encapsulant. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. The semiconductor devices are stackable and electrically connected through the substrate, discrete electrical devices, and bumps. A heat spreader or second semiconductor die can be disposed between the stacked semiconductor devices.

Abstract: An embedded package includes a semiconductor chip divided into a cell region and a peripheral region, having a first surface and a second surface which faces away from the first surface, and including an integrated circuit which is formed in the cell region on the first surface, a bonding pad which is formed in the peripheral region on the first surface and a bump which is formed over the bonding pad; a core layer attached to the second surface of the semiconductor chip; an insulation component formed over the core layer including the semiconductor chip and having an opening which exposes the bump; and a circuit wiring line formed over the insulation component and the bump and electrically connected to is the bump, wherein the insulation component formed in the cell region has a thickness larger than a height of the bump.

Abstract: Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.

Abstract: Dual-layered structural semiconductor chips are provided. The semiconductor chip includes a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip. The first semiconductor chip includes a first substrate having a first bottom surface. The second semiconductor chip includes a second substrate having a second bottom surface. The first bottom surface directly contacts the second bottom surface. The related packages and the related methods are also provided.

Abstract: The present invention relates to a method for inhibiting growth of intermetallic compounds, comprising the steps of: (i) preparing a substrate element including a substrate on which at least one layer of metal pad is deposited, wherein at least one thin layer of solder is deposited onto the layer of metal pad, and then carry out reflowing process; and (ii) further depositing a bump of solder with an appropriate thickness on the substrate element, characterized in that a thin intermetallic compound is formed by the reaction of the thin solder layer and the metal in the metal pad after appropriate heat treatment of the thin solder layer. In the present invention, the formation of a thin intermetallic compound is able to slow the growth of the intermetallic compound and to prevent the transformation of the intermetallic compounds.

Abstract: A semiconductor device includes a wiring substrate having first and second connection pads on a main surface thereof, a first semiconductor chip having first electrode pads, a second semiconductor chip having second electrode pads each of which has a size smaller than that of each of the first electrode pads, first wires connecting the first electrode pads with the first connection pads, and second wires connecting the second electrode pads with the second connection pads. The second wires have wide width parts at first ends. The first electrode pads are larger than the wide width parts while the second electrode pads are smaller than the wide width parts. The wide width parts are connected the second connection pads and the second wires have second ends connected to the second electrode pads via bump electrodes which are smaller than the second electrode pads.

Abstract: A semiconductor device includes a semiconductor substrate, which includes a through hole that extends through the semiconductor substrate. An insulative layer includes a first surface, an opposite second surface covering the semiconductor substrate, and an opening aligned with the through hole. An insulative film covers an inner wall surface of the semiconductor substrate and the opening. A through electrode is formed in the through hole and the opening inward from the insulative film. The through electrode includes a first end surface that forms a pad exposed from the first surface of the insulative layer. The first end surface of the through electrode is flush with the first surface of the insulative layer.

Abstract: The present invention relates to a package for semiconductor device and the fabrication method for integrally encapsulating a whole semiconductor chip within a molding compound. In the semicondcutor device package, bonding pads distributed on the top of the chip are redistributed into an array of redistributed bonding pads located in an dielectric layer by utilizing the redistribution technique. The electrodes or signal terminals on the top of the semiconductor chip are connected to an electrode metal segment on the bottom of the chip by conductive materials filled in through holes formed in a silicon substrate of a semiconductor wafer. Furthermore, the top molding portion and the bottom molding portion seal the semiconductor chip completely, thus providing optimum mechanical and electrical protections.

Abstract: A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

Abstract: A chip package structure includes a flexible substrate having a chip mounting region, a plurality of leads disposed on the flexible substrate, an insulating layer and a chip. Each lead includes a body portion and an inner lead portion connected to each other. The body portion is located outside the chip mounting region and has a thickness greater than that of the inner lead portion. The insulating layer is disposed on the inner lead portions. The chip has an active surface on which a plurality of bumps and a seal ring adjacent to the chip edges are disposed. The chip is mounted within the chip mounting region and electrically connects the flexible substrate by connecting the inner lead portions of the leads with the bumps. The insulating layer is corresponding to the seal ring in position when the chip is electrically connected to the flexible substrate.

Abstract: A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

Abstract: The disclosure relates to a conductive bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface and conductive bumps distributed over the major surface of the substrate. Each of a first subset of the conductive bumps comprise a regular body, and each of a second subset of the conductive bumps comprise a ring-shaped body.

Abstract: The embodiments of bump and bump-on-trace (BOT) structures provide bumps with recess regions for reflowed solder to fill. The recess regions are placed in areas of the bumps where reflow solder is most likely to protrude. The recess regions reduce the risk of bump to trace shorting. As a result, yield can be improved.

Abstract: A solder bump support structure and method of manufacturing thereof is provided. The solder bump support structure includes an inter-level dielectric (ILD) layer formed over a silicon substrate. The ILD layer has a plurality of conductive vias. The structure further includes a first insulation layer formed on the ILD layer. The solder bump support structure further includes a pedestal member formed on the ILD layer which includes a conductive material formed above the plurality of conductive vias in the ILD layer coaxially surrounded by a second insulation layer. The second insulation layer is thicker than the first insulation layer. The structure further includes a capping under bump metal (UBM) layer formed over, and in electrical contact with, the conductive material and formed over at least a portion of the second insulation layer of the pedestal member.

Abstract: Disclosed is a flip-chip semiconductor device having isotropic electrical interconnection, primarily comprising a chip and a substrate. The chip has at least a first bump and a plurality of second bumps. The substrate has a plurality of bump pads disposed on the top surface and an isotropic connecting mechanism disposed inside the substrate consisting of a plurality of terminals electrically isolated from each other and a flexible vertical pad protruded from the top surface, wherein the disposition locations of the terminals circle around the flexible vertical pad as a disposition center. When the second bumps of the chip are bonded onto the corresponding bump pads, the first bump presses and bends the flexible vertical pad in a specific horizontal direction so that the flexible vertical pad selectively and electrically connect to a selected one of the terminals.

Abstract: A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.

Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate that contains a plurality of electronic components. The semiconductor device includes an interconnect structure disposed over the substrate, the interconnect structure containing a plurality of interconnect layers. The semiconductor device includes a passivation layer disposed over the interconnect structure. The semiconductor device includes an Under-Bump Metallization (UBM) layer disposed over the passivation layer, the UBM layer containing a UBM pad and a plurality of UBM devices, the UBM devices including at least one of: a UBM trace that is electrically coupled to one of the electronic components through the interconnect structure, and a dummy UBM device. The semiconductor device includes a solder bump disposed on, and electrically coupled to, the UBM pad.

Abstract: The invention provides a package structure, including: a substrate, wherein the substrate has a first surface and a second surface, and a first pattern metal layer is formed on the first surface, and a second patterned metal layer is formed on the second surface, and the substrate has a plurality of vias formed therein, wherein the first patterned metal layer is electrically connected to the second patterned metal layer through the plurality of vias, and the widths of the plurality of vias are gradually increased from the first surface to the second surface; a chip formed on the first surface of the substrate; and a molding material is formed on the substrate and the chip, wherein the chip is covered by the molding material.

Abstract: A method for rejoining an IC die, removed from an existing substrate, to a new substrate, is disclosed herein. In one embodiment, such a method includes grinding an existing substrate from an IC die to create a substantially planar surface exposing interconnects and surrounding underfill material. A new substrate is provided having electrically conductive pedestals protruding therefrom. The electrically conductive pedestals are positioned to align with the exposed interconnects and have a melting point substantially higher than the melting point of the interconnects. The method places the exposed interconnects in contact with the electrically conductive pedestals. The method then applies a reflow process to melt and electrically join the exposed interconnects with the electrically conductive pedestals. A structure produced by the method is also disclosed.

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a semiconductor substrate containing a chip area and a peripheral pad area surrounding the chip area, wherein a conductive pad and a through hole exposing the conductive pad are formed in the peripheral pad area; a protection layer covering a bottom surface of the semiconductor substrate and the through hole; a packaging layer formed on an upper surface of the semiconductor substrate; and a spacing layer formed between the packaging layer and the semiconductor substrate, wherein the chip packaging has a main side surface constituted of side surfaces of the semiconductor substrate, the protecting layer, the packaging layer and the spacing layer, and wherein the main side surface has at least one recess portion.

Abstract: A semiconductor device is provided and includes a semiconductor die, and a plurality of bond pads having exposed surfaces arranged in an alternating interleaved pattern on the semiconductor die. Each of the surfaces of the bond pads have a first bond placement area that overlaps with a second bond placement area, with the first bond placement area having a major axis that is orthogonal to a major axis of the second bond placement area. A connecting bond is located at an intersection of the major axes of the first bond placement area and the second bond placement area on one or more of the bond pads.

Abstract: In an embodiment, a stacked semiconductor package includes a wiring board having external connection terminals and internal connection terminals, and first and second modules stacked on the wiring board. Each of the first and second modules includes a plurality of semiconductor chips mounted on an interposer and a sealing resin layer. The interposers and the internal connection terminals of the wiring board are electrically connected by connecting members such as metal wires, printed wiring layers or metal bumps. The first and second modules are collectively sealed by a sealing resin layer formed on the wiring board.

Abstract: An electronic unit is produced including at least one electronic component at least partially embedded in an insulating material. A film assembly is provided with at least one conductive layer and a carrier layer. The conductive layer includes openings in the form of holes for receiving bumps, which are connected to contact surfaces of the at least one electronic component. The at least one component is placed on the film assembly such that the bumps engage with the openings of the conductive layer. The at least one component is partially embedded from the side opposite of the bumps into a dielectric layer. The carrier layer of the film assembly is removed such that the surface of the bumps is exposed. A metallization layer is then deposited on the side of the remaining conductive layer having the exposed bumps and so as to produce conductor tracks that overlap with the bumps.

Abstract: A mounting structure for a semiconductor device includes a stepwise stress buffer layer under a likewise stepwise UBM structure.

Abstract: A test circuit includes a substrate, a wiring section having a plurality of pieces of wiring, and a device-under-test section formed on the substrate, and having a device-under-test main body and a plurality of connecting electrodes for establishing connection between the main body and the plurality of pieces of wiring, an extending direction of a straight line connecting a position of a center of rotation in a plane of pattern formation of the main body and each electrodes being inclined at a predetermined angle to an extending direction of the pieces of wiring, and the connecting electrodes being arranged at positions such that connection relation between the electrodes and the plurality of pieces of wiring is maintained even when the main body and the electrodes are rotated about the position of the center of rotation by 90 degrees relative to the wiring section in the plane of the pattern formation.

Abstract: A package-on-package (PoP) comprises a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of bond-on-trace connections, and a second function chip on top of the first function chip, directly connected to the substrate. Another package-on-package (PoP) comprises: a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of solder mask defined (SMD) connections formed on SMD bonding pads connected to solder bumps, and a second function chip on top of the first function chip, directly connected to the substrate by a plurality of bond-on-trace connections.

Abstract: A semiconductor stack package apparatus includes an upper semiconductor package and a lower semiconductor package. The upper semiconductor chip includes a chip pad, an upper substrate including a substrate pad formed on a top surface of the upper substrate and an upper ball land formed on a bottom surface of the upper substrate and attached to an intermediate solder ball, and a wire connecting the chip pad and the substrate pad. The lower semiconductor package includes a lower semiconductor chip including a bump, and a lower substrate including a bump land formed on a top surface of the lower substrate in an area corresponding to the bump, an intermediate ball land formed on the top surface of the lower substrate in an area corresponding to the intermediate solder ball, and a lower ball land formed on a bottom surface of the lower substrate and attached to a lower solder ball.

Abstract: A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.

Abstract: A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

Abstract: In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls.

Abstract: A device includes a package component, and a metal trace on a surface of the package component. A first and a second dielectric mask cover a top surface and sidewalls of the metal trace, wherein a landing portion of the metal trace is located between the first and the second dielectric masks. The landing portion includes a first portion having a first width, and a second portion connected to an end of the first portion. The second portion has a second width greater than the first width, wherein the first and the second widths are measured in a direction perpendicular to a lengthwise direction of the metal trace.

Abstract: A conductive connecting member formed on a bonded face of an electrode terminal of a semiconductor or an electrode terminal of a circuit board, the conductive connecting member comprising a porous body formed in such manner that a conductive paste containing metal fine particles (P) having mean primary particle diameter from 10 to 500 nm and an organic solvent (S), or a conductive paste containing the metal fine particles (P) and an organic dispersion medium (D) comprising the organic solvent (S) and an organic binder (R) is heating-treated so as for the metal fine particles (P) to be bonded, the porous body being formed by bonded metal fine particles (P) having mean primary particle diameter from 10 to 500 nm, a porosity thereof being from 5 to 35 volume %, and mean pore diameter being from 1 to 200 nm.

Abstract: A semiconductor structure includes multiple semiconductor devices on a substrate and a metal layer disposed over the semiconductor devices, the metal layer comprising at least a first trace and a second trace. A conductive pillar is disposed directly on and in electrical contact with the first trace of the metal layer, and a dielectric layer is selectively disposed between the metal layer and the conductive pillar, where the dielectric layer electrically isolates the second trace from the pillar. A moisture barrier surrounds the semiconductor devices around a periphery of the semiconductor structure, and extends from the substrate through the dielectric layer to the conductive pillar.

Abstract: A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack.

Abstract: In a method aspect, a multiplicity of ICs are attached to routing on a structurally supportive carrier (such as a wafer). The dice are encapsulated and then both the dice and the encapsulant layer are thinned with the carrier in place. A second routing layer is formed over the first encapsulant layer and conductive vias are provided to electrically couple the first and second routing layers as desired. External I/O contacts (e.g. solder bumps) are provided to facilitate electrical connection of the second routing layer (or a subsequent routing layer in stacked packages) to external devices. A contact encapsulant layer is then formed over the first encapsulant layer and the second routing layer in a manner that embeds the external I/O contacts at least partially therein. After the contact encapsulant layer has been formed, the carrier itself may be thinned significantly and singulated to provide a number of very low profile packages. The described approach can also be used to form stacked multi-chip packages.

Abstract: The present invention is aimed to provide a thermosetting resin composition which is easily produced, has excellent storage stability and thermal stability while maintaining high transparency and preventing formation of voids on the occasion of semiconductor chip bonding, and gives a cured product having excellent heat resistance, a flip-chip mounting adhesive containing the thermosetting resin composition, a method for producing a semiconductor device using the flip-chip mounting adhesive, and a semiconductor device produced by the method for producing a semiconductor device. The present invention is a thermosetting resin composition including an epoxy resin, an acid anhydride having a bicycle skeleton, and an imidazole curing accelerator that is in a liquid form at an ordinary temperature.

Abstract: Provided is a semiconductor device including a flexible circuit board which includes a first external electrode provided on a first face and second and third external electrodes provided on a second face; a plurality of memory devices and passive components; a supporter which is provided with a groove on one face; and a computing processor device. The memory devices and the passive components are connected to the first external electrode, the one face of the supporter is bonded on the first face of the flexible circuit board so that the groove houses the memory devices and the passive components. The flexible circuit board is bent along a perimeter of the supporter to be wrapped around a side face and another face of the supporter. On the flexible circuit board, the second external electrode is provided on the second face which is opposite to the first external electrode, and the third external electrode is provided on the second face which is bent to the another face of the supporter.

Abstract: An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.

Abstract: A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.

Abstract: A microelectronic package includes a substrate overlying the front face of a microelectronic element. A plurality of metal bumps can project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. A conductive matrix material can contact the second ends and at least portions of the lateral surfaces of respective ones of the metal bumps and join the metal bumps with contacts of the microelectronic element.

Abstract: A chip-scale package includes an encapsulating layer, a chip embedded in the encapsulating layer and having an active surface exposed from the encapsulating layer, a buffering dielectric layer formed on the encapsulating layer and the chip, a build-up dielectric layer formed on the buffering dielectric layer, and a circuit layer formed on the build-up dielectric layer and having conductive blind vias penetrating the build-up dielectric layer and being in communication with the openings of the buffering dielectric layer and electrically connected to the chip, wherein the build-up dielectric layer and the buffering dielectric layer are made of different materials. Therefore, delamination does not occur between the buffering dielectric layer and the encapsulating layer, because the buffering dielectric layer is securely bonded to the encapsulating layer and the buffering dielectric layer is evenly distributed on the encapsulating layer.

Abstract: A method for selectively transferring active components from a source substrate to a destination substrate includes pressing a first stamp having first pillars protruding therefrom against active components on the source substrate to adhere respective primary surfaces of the active components including electrical connections thereon to respective transfer surfaces of the first pillars. A second stamp having second pillars protruding therefrom is pressed against the active components on the first stamp to adhere respective secondary surfaces of the active components to respective transfer surfaces of the second pillars. The transfer surfaces of the second pillars have greater adhesive strength than the first pillars. The second stamp is pressed against a destination substrate to adhere the respective primary surfaces of the active components including the electrical connections thereon to a receiving surface of the destination substrate.

Abstract: A semiconductor package includes a substrate having a flip chip bonding area. A plurality of recessed bump pads are disposed in the flip chip bonding area. The substrate further includes a solder mask that covers a circuit area. A chip having a plurality of metal bumps is mounted in the flip chip bonding area. The metal bumps are respectively connected to the recessed bump pads. An underfill is filled into the gap between the substrate and the chip.

Abstract: A microelectronic assembly may include a substrate containing a dielectric element having first and second opposed surfaces. The dielectric element may include a first dielectric layer adjacent the first surface, and a second dielectric layer disposed between the first dielectric layer and the second surface. A Young's modulus of the first dielectric layer may be at least 50% greater than the Young's modulus of the second dielectric layer, which is less than two gigapascal (GPa). A conductive structure may extend through the first and second dielectric layers and electrically connect substrate contacts at the first surface with terminals at the second surface. The substrate contacts may be joined with contacts of a microelectronic element through conductive masses, and a rigid underfill may be between the microelectronic element and the first surface. The terminals may be usable to bond the microelectronic assembly to contacts of a component external to the microelectronic assembly.

Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.