Abstract: A lateral silicon controlled rectifier structure includes a P-type substrate; an N-well region in the P-type substrate; a first P+ doped region in the N-well region and being connected to an anode; a P-well region in the P-type substrate and bordering upon the N-well region; a first N+ doped region formed in the P-well region and separated from the first P+ doped region by a spacing distance, the first N+ doped region being connected to a cathode; and a gate structure overlying a portion of the P-type substrate between the first P+ doped region and the first N+ doped region.

Abstract: A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Abstract: An integrated circuit package including a semiconductor die and a flexible circuit (flex circuit), and a method for forming the integrated circuit package. The flex circuit can include a direct connect pad which is not electrically coupled to an active trace, a blind via electrically coupled to the direct connect pad, and a semiconductor die having a bond pad which is electrically coupled to the direct connect pad using a conductor. The bond pad, the conductor, the direct connect pad, and the blind via can all be vertically aligned, each with the other.

Abstract: Disclosed herein is a semiconductor package. The semiconductor package includes a semiconductor module, a first heat dissipation unit, a second heat dissipation unit and a housing. The semiconductor module contains a semiconductor device. The first heat dissipation unit is provided under the semiconductor module. The first heat dissipation unit includes at least one first pipe through which first cooling water passes. A first rotator is rotatably disposed in the first pipe. The second heat dissipation unit is provided on the semiconductor module. The second heat dissipation unit includes at least one second pipe through which second cooling water passes. A second rotator is rotatably disposed in the second pipe. The housing is provided on opposite sides of the semiconductor module, the first heat dissipation unit and the second heat dissipation unit and supports the semiconductor module, the first heat dissipation unit and the second heat dissipation unit.

Abstract: A metal leadframe strip (500) for semiconductor devices is described. The leadframe strip has a plurality of sites (510) for assembling semiconductor chips. The sites alternate with zones (520) for connecting the leadframe to molding compound runners. The sites (510) have mechanically rough and optically matte surfaces (511, 512). The zones (520) have at least portions with mechanically flattened and optically shiny metal surfaces (521, 522). The flattened surface portions transition into the rough surface portions by a step.

Abstract: A combined diode, lead assembly incorporating two expansion joints. The combined diode, lead assembly incorporating two expansion joints includes a diode having a first diode terminal and a second diode terminal, a first conductor and a second conductor. The first conductor includes a first terminal that is electrically coupled to the diode at the first diode terminal and a second terminal that is configured as a first expansion joint, which is configured to electrically couple to a first interconnecting-conductor and is configured to reduce a stress applied to the diode by the first conductor. The second conductor includes a first terminal that is electrically coupled to the diode at the second diode terminal and a second terminal that is configured as a second expansion joint, which is configured to electrically couple to a second interconnecting-conductor and is configured to reduce a stress applied to the diode by the second conductor.

Abstract: One illustrative method disclosed herein includes forming a conductive pad in a layer of insulating material, forming a passivation layer above the conductive pad, performing at least one etching process on the passivation layer to define an opening in the passivation layer that exposes at least a portion of the conductive pad, forming a protective layer on the passivation layer, in the opening and on the exposed portion of the conductive pad, forming a heat-curable material layer above the protective layer, performing an etching process to define a patterned heat-curable material layer having an opening that exposes a portion of the protective layer, performing an etching process on the protective layer to thereby expose at least a portion of the conductive pad and forming a conductive bump that is conductively coupled to the conductive pad.

Abstract: A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.

Abstract: A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like microelectronic elements attached together at dicing lanes. Each microelectronic element has boundaries defined by edges including a first edge and a second edge. The first and second microelectronic substrates can be joined in different orientations, such that first edges of microelectronic elements of the first microelectronic substrate are aligned with second edges of microelectronic elements of the second microelectronic substrate. After exposing traces at the first and second edges of the microelectronic elements of the stacked microelectronic substrates, first and second leads can be formed which are connected to the exposed traces of the first and second microelectronic substrates, respectively. The second leads can be electrically isolated from the first leads.

Abstract: A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes.

Abstract: A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The microelectronic element can include a plurality of stacked electrically interconnected semiconductor chips. The substrate can have contacts facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations within the microelectronic element.

Abstract: A power semiconductor package structure includes a carrier, a first power chip, a second power chip, a first conductive sheet, a second conductive sheet and a third conductive sheet. The first power chip has a first surface and a second surface opposing to the first surface. A first control electrode and a first main power electrode are disposed on the first surface, and a second main power electrode is disposed on the second surface. The second surface is disposed on the carrier, and electrically connected to the carrier through the second main power electrode. The second power chip has a third surface and a fourth surface opposing to the third surface. A third main power electrode is disposed on the third surface, and a fourth main power electrode is disposed on the fourth surface. The fourth surface is disposed on the first power chip. The first conductive sheet is electrically connected to the first main power electrode and the fourth main power electrode.

Abstract: An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface of the wiring substrate. The plural lands include a first land group arranged in a plurality of rows and arranged along a peripheral edge portion of the lower surface of the wiring substrate, and a second land group arranged inside the first land group in the lower surface of the wiring substrate. The lands in the first land group are arranged with a first pitch, and the lands in the second land group are arranged with a second pitch higher than the first pitch.

Abstract: A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between any two adjacent columns of the terminals. The axial plane can intersect the central region.

Abstract: A display device includes a substrate, a display region having pixels on the substrate, a drive circuit element mounted on a peripheral portion of the substrate, a plurality of terminal portions formed on the peripheral portion and arranged on a mounting portion of the drive circuit element, and a plurality of wiring lines prolonged from the terminal portions to the outside of the mounting portion of the substrate. The terminal parts are arranged to two lines of the plurality of wiring lines along one end of the mounting portion, a plurality of bumps connected to each of the terminal portions by an anisotropic conductive film are formed on the plane facing the terminal portion of the drive circuit element, a part of the plurality bumps include a first bump and a second bump which is adjoined close to the first bump.

Abstract: A semiconductor device having a printed circuit board and a semiconductor chip. The printed circuit board includes a chip region, a plurality of first ball lands adjacent to the chip region, and at least one second ball land adjacent to the first ball lands. The semiconductor chip is mounted on the chip region. The first ball lands are arranged to have a first pitch. One of the first ball lands which is nearest to the second ball land, and the second ball land have a second pitch greater than the first pitch.

Abstract: A method includes forming a patterned buildup layer on a first surface of a dielectric layer, the patterned buildup layer including a patterned buildup layer opening exposing a trace coupled to the dielectric layer. A conductor layer is flash plated on the patterned buildup layer and within the patterned buildup layer opening. The patterned buildup layer opening is filled with a blanket conductive filler layer. The blanket conductive filler layer and the conductor layer are planarized to form a flip chip bump.

Abstract: Technology is provided in which, when forming a trench of a narrow width in a thick semiconductor layer, a trench can be formed without the occurrence of semiconductor residue. In this Specification, a semiconductor device in which a trench is formed in a semiconductor layer is disclosed. In the semiconductor layer of the semiconductor device, a compensation pattern which compensates for sudden changes in the width of the trench is formed at a place at which the width of the trench changes suddenly. In the semiconductor layer of the above-described semiconductor device, since a compensation pattern is formed at a place at which the trench width changes suddenly, in the case where forming the trench using a deep RIE method, the occurrence of steep inclined portions arising from semiconductor residue can be prevented. Consequently, when forming, a trench of a narrow width in a thick semiconductor layer, the occurrence of semiconductor residue can be prevented.

Abstract: A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package.

Abstract: Embodiments of the present invention provide a printed wiring board in which solder bumps of a mounted semiconductor chip are less prone to be ruptured. The printed wiring board includes a dielectric layer having a main surface and a connecting pad embedded in the dielectric layer. The connecting pad is shaped like a brimmed hat. That is, the connecting pad includes a plate portion whose diameter is larger than that of a contact portion. The main surface of the contact portion is exposed at the main surface of the dielectric layer. Diameter of the contact portion is substantially the same as diameter of an under bump metal at the semiconductor chip side, when mechanical stress is applied, the stress disperses evenly to both of the connecting pad and the under bump metal, and thus rupture is less prone to occur.

Abstract: A semiconductor wafer including an electrostatic discharge (ESD) protective device, and methods for fabricating the same. In one aspect, the method includes forming a first semiconductor device in a first semiconductor die region on the semiconductor wafer; forming a second semiconductor device in a second semiconductor die region on the semiconductor wafer; and forming a protective device in a scribe line region between (i) the first semiconductor die region and (ii) the second semiconductor die region.

Abstract: An anchored conductive damascene buried in a multi-density dielectric layer and method for forming the same, the anchored conductive damascene including a dielectric layer with an opening extending through a thickness of the dielectric layer; wherein the dielectric layer comprises at least one relatively higher density portion and a relatively lower density portion, the relatively lower density portion forming a contiguous major portion of the dielectric layer; and, wherein the opening in the relatively lower density portion has a lateral dimension relatively larger compared to the relatively higher density portion to form anchoring steps.

Abstract: In a method of manufacturing a semiconductor package including a wire binding process, a first end of the bonding wire is bonded to a first pad so as to form a first bond portion. A second end of the bonding wire is bonded to a second pad, wherein an interface surface between the bonding wire and the second pad has a first connecting area. The bonded second end of the bonding wire is scrubbed so as to form a second bond portion, wherein a new interface surface between the bonding wire and the second pad has a second connecting area larger than the first connecting area. A remainder of the bonding wire is separated from the second bond portion.

Abstract: A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved.

Abstract: An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.

Abstract: A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.

Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.

Abstract: A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major surface, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/O contacts.

Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

Abstract: A microelectronic package can include a substrate having first, second, and third apertures extending between first and second surfaces thereof, first, second, and third microelectronic elements each having a surface facing the first surface, and a plurality of terminals exposed at a central region of the second surface. The apertures can have first, second, and third axes extending in directions of the lengths of the respective apertures. The first and second axes can be parallel to one another. The third axis can be transverse to the first axis. The central region of the second surface of the substrate can be disposed between the first and second axes. The terminals can be configured to carry sufficient address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within at least one of the microelectronic elements.

Abstract: A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern.

Abstract: Semiconductor devices that contain a system in package and methods for making such packages are described. The semiconductor device with a system in package (SIP) contains a first IC die, passive components, and discrete devices that are contained in a lower level of the package. The SIP also contains a second IC die that is vertically separated from the first IC die by an array of metal interposers, thereby isolating the components of the first IC die from the components of the second IC die. Such a configuration provides more functionality within a single semiconductor package while also reducing or eliminating local heating in the package. Other embodiments are also described.

Abstract: A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern. The first region and the second region have same area.

Abstract: There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width as the metal post and the top surface of the solder post being substantially rounded, and an intermetallic compound layer disposed at the interface between the metal post and the solder post. An oxide layer formed on the solder post prevents solder post under reflow from being changed into a spherical shape. An intermetallic compound layer may be formed by an aging process at the interface between the metal post and the solder post. The bump structure can realize fine pitch semiconductor package without a short between neighboring bumps.

Abstract: A semiconductor package structure is provided. The structure includes a semiconductor chip having a plurality of interconnect layers formed thereover. A first passivation layer is formed over the plurality of interconnect layers. A stress buffer layer is formed over the first passivation layer. A bonding pad is formed over the stress buffer layer. A second passivation layer is formed over a portion of the bonding pad, the second passivation having at least one opening therein exposing a portion of the bonding pad.

Abstract: Devices and methods for electrical interconnection for microelectronic circuits are disclosed. One method of electrical interconnection includes forming a bundle of microfilaments, wherein at least two of the microfilaments include electrically conductive portions extending along their lengths. The method can also include bonding the microfilaments to corresponding bond pads of a microelectronic circuit substrate to form electrical connections between the electrically conductive portions and the corresponding bond pads. A microelectronic circuit can include a bundle of microfilaments bonded to corresponding bond pads to make electrical connection between corresponding bonds pads and electrically-conductive portions of the microfilaments.

Abstract: An apparatus comprises a first chip layer comprising a first component coupled to a first side of a first flex layer, the first component comprising a plurality of electrical pads. The first chip layer also comprises a first plurality of feed-thru pads coupled to the first side of the first flex layer and a first encapsulant encapsulating the first component, the first encapsulant having a portion thereof removed to form a first plurality of cavities in the first encapsulant and to expose the first plurality of feed-thru pads by way of the first plurality of cavities.

Abstract: A semiconductor device including an intermediate insulating film formed over a plurality of first conductors over a semiconductor substrate. Contact holes are formed in the intermediate insulating film over the first conductors, and contact plugs are buried in the contact holes, respectively. A plurality of second conductors are formed over the plurality of contact plugs on the intermediate insulating film, respectively, and are electrically connected to the plurality of first conductors via the contact plugs. In certain regions of the semiconductor device, the contact plugs may terminate within the intermediate insulating film, thereby electrically insulating the second conductors from the first conductors.

Abstract: A leadframe design for a diode or other semiconductor device that reduces stress on the device and provides increased heat dissipation is provided. According to various embodiments, the leadframe has a contoured profile including a recessed area and a raised surface within the recessed area. The surface supports the device such that the edges of the device extend past the surface. Also provided are device assemblies including the novel leadframes. In certain embodiments, the assemblies include one or more leadframes attached via a solder joint to a device. According to various embodiments, the leadframes are attached to the front side of the device, back side of the device or both. In particular embodiments, the device is a bypass diode for one or more solar cells in a solar module.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a carrier having a contact pad; forming a first resist layer, having a first resist opening, over the carrier and the contact pad, the first resist opening partially exposing the first contact pad; forming a second resist layer, having a second resist opening over the first resist opening, the second resist opening partially exposing the first resist layer; mounting an integrated circuit over the carrier; and forming an internal interconnect between the integrated circuit and the carrier, the internal interconnect filling the second resist opening with no space between the second resist layer in the second resist opening.

Abstract: A surface mount semiconductor device has a semiconductor die encapsulated in a molding compound. Electrical contact elements of an intermediate set are disposed on the molding compound. A set of coated wires electrically connect bonding pads of the semiconductor die and the electrical contact elements of the intermediate set. A layer of insulating material covers the coated wires, the die and the electrical contact elements of the intermediate set. Electrically conductive elements are exposed at an external surface of the layer of insulating material and contact respective electrical contact elements of the intermediate set through the layer of insulating material.

Abstract: An assembly and method of making same are provided. The assembly can include a first component including a dielectric region having an exposed surface, a conductive pad at the surface defined by a conductive element having at least a portion extending in an oscillating or spiral path along the surface, and a an electrically conductive bonding material joined to the conductive pad and bridging an exposed portion of the dielectric surface between adjacent segments. The conductive pad can permit electrical interconnection of the first component with a second component having a terminal joined to the pad through the electrically conductive bonding material. The path of the conductive element may or may not overlap or cross itself.

Abstract: An electric sub-assembly has an integrated circuit, which contains at least one power semi-conductor component and additional electronic components, the latter being interconnected and linked to connections by the conductors of a lead frame (1, 2, 3). The lead frame (1, 2, 3) has at least one cooling surface (3), which is connected in a thermally conductive manner to a thermal contact (4) of the integrated circuit or circuits. The cooling surface has a greater surface area than the thermal contact surface (4) of the integrated circuit or circuits and is wider than the parts (1) of the lead frame that are used as electric conductors.

Abstract: For a DC to DC converter circuit integrated on a packaged die, the relative positions of various die pads and power MOSFETs on the die for a small outline integrated circuit package are described.

Abstract: An integrated circuit device includes a Cu pillar and a solder layer overlying the Cu pillar. A Co-containing metallization layer is formed to cover the Cu pillar and the solder layer, and then a thermally reflow process is performed to form a solder bump and drive the Co element into the solder bump. Next, an oxidation process is performed to form a cobalt oxide layer on the sidewall surface of the Cu pillar.

Abstract: A semiconductor device includes a substrate having external connection terminals, and a semiconductor chip mounted over a semiconductor-chip mounting portion of the substrate. The external connection terminals are formed by sequentially forming an electroless nickel plating layer, an electroless gold plating layer, and an electrolytic gold plating layer on a terminal portion formed on a surface of the substrate.

Abstract: A semiconductor package containing a field effect transistor (FET) used in a high frequency band includes a mounting circuit substrate on which the semiconductor device is mounted. The mounting circuit substrate has a gate wiring conductor, a drain wiring conductor, and a source wiring conductor, which are connected to the gate electrode, the drain electrode, and the source electrode, respectively, of the semiconductor device. The gate wiring conductor and the drain wiring conductor extend toward each other so that their adjacent or facing ends are in close proximity to each other, thereby increasing the capacitance between the gate wiring conductor and the drain wiring conductor.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a substrate; mounting a base integrated circuit on the substrate; forming a leadframe interposer, over the base integrated circuit, by: providing a metal sheet, mounting an integrated circuit die on the metal sheet, injecting a molded package body on the integrated circuit die and the metal sheet, and forming a ball pad, a bond finger, or a combination thereof from the metal sheet that is not protected by the molded package body; coupling a circuit package on the ball pad; and forming a component package on the substrate, the base integrated circuit, and the leadframe interposer.

Abstract: Methods and systems for forming a variety of integrated circuits, having quite different interfaces and packages, from a single manufactured die. Preferably the die has bond pads for at least a first mode of operation positioned along only two of its four sides, and these bond pads are sufficient to construct a multi-chip module in which the die is functional in the first mode of operation. Many of the pads on these two sides are duplicated on third and/or fourth sides, except that power management circuitry prevents wasteful capacitive current onto whichever of the duplicated pads is not connected out. Optionally the third and/or fourth sides can be used for connections needed for a mode which is not available with two sides only.

Abstract: Wire bond pad and solder ball or controlled collapse chip connections C4 are combined on a planar surface of a an integrated circuit device to provide a die. Known good die (KGD) testing is optionally performed using wire bond connections or stress tolerant solder ball connections. The KGD testing is conducted after the integrated circuit dies are diced from a wafer. Solder ball or C4 array connections which withstand thermal stress are used to KGD test the die prior to final use of the wire bond pad connections to an end use device. Alternatively, wire bond pads are used to test the die while maintaining the solder ball or C4 array in a pristine condition for bonding to a final end product device. Both testing with the solder ball C4 array contacts and with the wire bond connections provides metallurgical connections for the KGD test. The solder ball or C4 array is connected to the wire bond pads and either connection can be used to burn-in test the die.