Abstract: A method for forming a semiconductor die and a flip-chip integrated circuit device are disclosed that include a power and ground mesh that is oriented diagonally. A layout of a semiconductor die is formed by generating a first integrated circuit design and copying and rotating the design so as to form three additional integrated circuit design blocks. The power and ground mesh layer includes four overlying sets of power and ground strips that are oriented diagonally and symmetric. Because the power and ground strips of the present invention are angled and correspond to the underlying integrated circuit design, they allow for powering both rotated and non-rotated logic while maintaining identical interconnection points and capacitive loading across all the repeated blocks. In addition, the angled power and ground strips allow for easily coupling power and ground to structures around the periphery of the power and ground strips.

Abstract: Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other.

Abstract: A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have relatively greater surface areas at the corners of the semiconductor package as compared to those at other areas and are formed to have the greatest surface area within a designable range. Additionally, occurrence of cracks may be inhibited at junctions of other solder balls by forming dummy solder pads at the outermost corners among the outer ball pads formed proximate to the corners of the wiring substrate. Stress arising during a board level reliability test is absorbed without product failure at junctions between the dummy solder pads and dummy solder balls.

Abstract: Stress barrier structures for semiconductor chips, and methods of fabrication thereof are described. In one embodiment, the semiconductor device includes a semiconductor substrate that includes active circuitry and an interconnect metallization structure over the active circuitry, wherein the interconnect metallization structure includes a layer of low-k insulating layer. A first metal bump is disposed over the semiconductor substrate and coupled to the active circuitry of the semiconductor substrate. A first stress barrier structure is disposed under the metal bump, and disposed over the low-k insulating layer, and a second substrate is disposed over the first metal bump.

Abstract: A semiconductor component and method for producing. The semiconductor component includes a semiconductor device and a leadframe. A package layout is defined and the orientation of electrically conductive members with respect to the semiconductor device and inner contact areas of the leadframe is altered so as to maximize the interfacial bonding area. The constraints of the standard package dimensions and the component assembly method are taken into account.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate further includes at least one signal layer having a plurality of electrical signal traces formed thereon. The package includes a discrete non-active electrical component mounted on the package so that the integrated circuit die is electrically connected with an electrical signal trace of the package through the discrete non-active electrical component. And in one particular implementation, the discrete non-active electrical component comprises a capacitive element arranged in series between the electrical signal traces and the die so that the capacitor operates as a package mounted AC coupling capacitor.

Abstract: A wire bond chip package includes a chip carrier; a semiconductor die having a die face and a die edge, the semiconductor die being mounted on a die attach surface of the chip carrier, wherein a plurality of input/output (I/O) pads are situated in or on the semiconductor die; a rewiring laminate structure on the semiconductor die, the rewiring laminate structure comprising a plurality of redistribution bond pads; a plurality of bond wires interconnecting the redistribution bond pads with the chip carrier; and a mold cap encapsulating at least the semiconductor die and the bond wires.

Abstract: A semiconductor device includes a tape carrier substrate having a flexible insulating film base, a plurality of conductor wirings provided on the film base, and wiring bumps respectively formed so as to cover an upper surface and both side surfaces of the conductor wirings, and a semiconductor chip mounted on the tape carrier substrate, wherein electrodes of the semiconductor chip are connected to the conductor wirings via the wiring bumps. Electrode bumps are formed on the electrodes of the semiconductor chip, the electrodes of the semiconductor chip are connected to the conductor wirings via a bonding between the wiring bumps and the electrode bumps, and the electrode bumps are harder than the wiring bumps. This structure can reduce bonding damages to the electrodes of the semiconductor chip caused by a process of connecting the electrodes and the conductor wirings via the bumps.

Abstract: Techniques for arranging ball grid arrays for producing low thermal resistance packages. One embodiment is for a ball grid array package that comprises a substrate, the substrate having a top surface and a bottom surface. A plurality of thermal balls are coupled to the bottom surface of the substrate, and at least one vias is positioned between every pair of the plurality of thermal balls. Other embodiments contemplate a ball grid array comprising thermal balls with a via located between every four thermal balls, wherein at least one vias is substituted for a thermal ball in the ball grid array.

Abstract: A cube semiconductor package includes one or more stacked together and interconnected semiconductor chip modules. The cube semiconductor package includes a semiconductor chip module and connection members. The semiconductor chip module includes a semiconductor chip which has a first and second surface, side surfaces, bonding pads, through-electrodes and redistribution lines. The second surface faces away from the first surface. The side surfaces connect to the first and second surfaces. The bonding pads are placed on the first surface. The through-electrodes pass through the first and second surfaces. The redistribution lines are placed at least on one of the first and second surfaces and are electrically connected to the through-electrodes and the bonding pads, and have ends flush with the side surfaces. The connection members are placed on the side surfaces and electrically connected with the ends of the redistribution lines.

Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

Abstract: An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

Abstract: A semiconductor chip package including a film substrate and a semiconductor chip loaded on the semiconductor chip is provided. The semiconductor chip includes a plurality of input pads and a plurality of output pads. A power supply input pad of the input pads is formed at a different edge from an edge of the semiconductor chip where other input pads are formed. The film substrate includes input lines and output lines. The input lines of the film substrate are connected to the corresponding input pads of the semiconductor chip, and the output lines thereof are connected to the corresponding output pads of the semiconductor chip.

Abstract: A land pattern, a method of manufacturing a printed circuit board (PCB) and a PCB incorporating a land pattern. In one embodiment, the land pattern includes: (1) a quadrilateral component outline area having diagonally opposed first and second corners and diagonally opposed third and fourth corners, defined according to a body configuration of a particular component type and located on a surface of a substrate and (2) first and second exposed conductive pads located within said area respectively proximate said first and second corners, coupled to respective first and second circuit conductors of said substrate, configured according to a terminal configuration of said type and separated from said third and fourth corners such that a component of said particular component type may be placed on the land pattern in multiple orientations without causing a short circuit.

Abstract: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

Abstract: In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.

Abstract: A semiconductor apparatus of the present invention includes: (i) a wire substrate having an insulating substrate in which a plurality of wire patterns are provided, (ii) a semiconductor element installed on the wire substrate with the insulating resin interposed therebetween, and a plurality of connecting terminals provided in the semiconductor element are electrically connected to connecting terminals of the wire patterns, respectively. In the semiconductor apparatus, the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns, and an entire upper face of each of the mark patterns is covered with the insulating resin.

Abstract: A semiconductor package apparatus includes a first semiconductor chip bonded onto a substrate of which metal wire turning upward; and a second semiconductor chip conductively bonded onto the first semiconductor chip in a vertical direction such that a metal wire of the second semiconductor chip and the metal wire of the first semiconductor chip have facing points. The semiconductor package apparatus includes a third semiconductor chip conductively bonded onto the first semiconductor chip in the vertical direction to be disposed horizontally with the second semiconductor chip such that a metal wire of the third semiconductor chip and the metal wire of the first semiconductor chip have facing points.

Abstract: Provided is a semiconductor power module package including a bonding area on a direct bonding cupper (DBC) board. The semiconductor power module package includes: one or more semiconductor chips; a sealing member sealing the one or more semiconductor chips; a plurality of leads electrically connected to the one or more semiconductor chips and exposed from the sealing member; and an external bonding member electrically connected to the one or more semiconductor chips and electrically connecting an external circuit board exposed from the sealing member.

Abstract: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.

Abstract: A flip-chip package structure comprises a carrier, a block bump, and a die. The carrier is a lead frame or substrate that comprises a lead pattern side, and an electrode pin is disposed on the lead pattern side. The die comprises an active side, and a bond pad is disposed on the active side. The block bump is bonded to the electrode pin; the bond pad of the die is attached on the carrier through the block bump, so that the die and the carrier joint together to form the flip chip package structure. Besides, the block bump is formed by the wedge bonding, and therefore in bumping size and shapes can easily form larger bump, which will increase the compactness between the die and the carrier.

Abstract: Plural via portions formed on a package substrate of a BGA include a first through-hole portion extended in the plane direction by an extension wiring connected to a land portion and a second through-hole portion that is arranged on the land portion serving as pad-on-via, whereby high-density wiring and multi-function of the BGA can be realized by using the package substrate having a two-layer wiring structure. Accordingly, cost for the package substrate can be reduced, and hence, cost for the BGA can be reduced, compared to a multi-layer wiring structure having four or six wiring layers.

Abstract: An integrated circuit package system provides a leadframe having a short lead finger and a long lead finger. A first die is placed in the leadframe. A second die is offset from the first die. The offset second die is attached to the first die and the long lead finger with an adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant.

Abstract: In a wiring structure of a semiconductor device and a method of manufacturing the same, a wiring structure includes a contact pad, a contact plug, a spacer and an insulation interlayer pattern. The contact pad is electrically connected to a contact region of a substrate. The contact plug is provided on the contact pad and is electrically connected to the contact pad. The spacer faces an upper side surface of the contact pad and sidewalls of the contact plug. The insulation interlayer pattern has an opening, the contact plug and the spacer being provided in the opening. The spacer of the wiring structure may prevent the contact pad from being damaged by a cleaning solution while forming a contact plug to be connected to a capacitor.

Abstract: A semiconductor package has a capacitor die and a packaging substrate. The capacitor die is coupled to circuitry on a front or back side of a die coupled to the packaging substrate for providing decoupling capacitance. In one example, the capacitor die is coupled to a land side of the packaging substrate in an area depopulated of a packaging array and adjacent to the packaging array. In another example, the capacitor die may be stacked on the die and coupled through wire bonds to circuitry on the die. The capacitor die reduces impedance of the integrated circuit allowing operation at higher frequencies.

Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.

Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions.

Abstract: Integrate circuit die terminal arrangements and configurations for mounting an integrate circuit die on a package substrate to reduce package transmission paths. In one embodiment, terminals for signals sensitive to trace length outside a die are arranged at the corners of the die. The die is mounted on a package substrate in an angle with respect to a package substrate to point the corners of the die at the edges of the package substrate to reduce trace length outside the die. The center of the die may or may not coincide with the center of the substrate. In one embodiment, when compare to a centered, non-rotated die mounting position, mounting a die with corners pointing at the edges of the package substrate does not cause significant differences in substrate warpage.

Abstract: A semiconductor package includes a semiconductor substrate having a semiconductor device arranged on one surface thereof; a cap substrate having one surface that opposes the one surface of the semiconductor substrate via a gap; a spacer that is arranged between the one surface of the semiconductor substrate and the one surface of the cap substrate, and that joins the semiconductor substrate and the cap substrate; and a filter that is provided on the cap substrate so as to overlap with the semiconductor device without overlapping with the spacer. The semiconductor package and method of manufacture can suppress exfoliation of the filter caused by chipping during the dicing step.

Abstract: One embodiment of the present invention provides advice for providing a low noise power supply package to an integrated circuit comprising a semiconductor die, input/output power supply terminals, and an array of embedded ceramic capacitors selected from discrete, planar and combinations thereof wherein said capacitors are placed in the locations selected from within the perimeter of the shadow of the semiconductor die, partially within the perimeter of the shadow of the semiconductor die, near the perimeter of the shadow of the semiconductor die, and combinations thereof.

Abstract: A microelectronic device structure as provided herein includes a conductive via having a body portion extending into a substrate from an upper surface thereof and a connecting portion laterally extending along the upper surface of the substrate. The connecting portion includes a recess therein opposite the upper surface of the substrate. The recess is confined within the connecting portion of the conductive via and does not extend beneath the upper surface of the substrate. A microelectronic device structure is also provided that includes a conductive via having a body portion extending into a substrate from an upper surface thereof and an end portion below the upper surface of the substrate. The end portion has a greater width than that of the body portion. A solder wettable layer is provided on the end portion. The solder wettable layer is formed of a material having a greater wettability with a conductive metal than that of the end portion of conductive via.

Abstract: A connecting terminal provided on a substrate and a connector provided on an electronic device are connected via a bump formed of a first member, which is formed of an anisotropic conductive paste including particles of a conductive material, and a second member which is different in conductivity from the first member. According to such a structure, since the anisotropic conductive paste which is softer as compared to a solder bump is used, stress applied to an interface between the bump and the connecting terminal is relaxed. Accordingly, reliability of connection can be assured even when using a substrate with large surface irregularities and/or bending, in which stress occurs relatively easily in a connection part of the bump and the connecting terminal.

Abstract: An electronic component includes: a semiconductor substrate having a first surface and a second surface opposing to the first surface; a trans-substrate conductive plug that penetrates the semiconductor substrate from the first surface to the second surface; an electronic element provided in the vicinity of the first surface of the semiconductor; and a sealing member that seals the electronic element between the sealing member and the first surface, wherein the electronic element is electrically connected to the trans-substrate conductive plug.

Abstract: Provided are a package structure and a package substrate, including: a substrate body having a plurality of matrix-arranged electrical contact pads formed on at least one surface thereof, wherein a solder mask layer is formed on said surface and has a plurality of openings for exposing the electrical contact pads, respectively; a first electroless-plated layer disposed on the electrical contact pads, on the walls of the openings and at the peripheries of the openings; and a second electroless-plated layer disposed on the first electroless-plated layer, the first and second electroless-plated layers constituting a recessed electrical connection structure. By forming the even electroless-plated layers on the electrical contact pads. The invention overcomes drawbacks of the prior art, namely breakage of interfaces between solder bumps and electrical contact pads and even damage of the package structure otherwise caused by excessive differences in stress between the solder bumps.

Abstract: A semiconductor device including: a semiconductor substrate in which an integrated circuit is formed; an insulating layer formed on the semiconductor substrate and having a first surface and a second surface which is higher than the first surface; a first electrode formed to avoid the second surface and electrically connected to the inside of the semiconductor substrate; and a second electrode formed on the second surface and electrically connected to the inside of the semiconductor substrate.

Abstract: An electronic component such as a semiconductor device is provided which is capable of preventing wiring breakage in a stress concentration region of surface layer wiring lines. In a semiconductor device provided with a support ball (5), no ordinary wiring line is formed in a region (7(A)) in the vicinity of the support ball (5) and a region (7(B)) at the end of the semiconductor chip facing the support ball (5), which are the stress concentration regions of the package substrate (2). Instead, a wiring line (6(C)) is formed away from these regions or a wide wiring line is formed in these regions.

Abstract: A semiconductor die includes a plurality of drivers and a plurality of bonding pads. Each driver is formed by a plurality of interconnected modules and has an associated bonding pad to which at least one of the modules of the driver is electrically connected. The modules of some of the drivers are positioned outside of the associated bonding pad toward a periphery of the die. The bonding pads may be arranged, for example, in a double- or triple-staggered pattern around the periphery of the die.

Abstract: A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion.

Abstract: In a power MOS transistor, for example, a source electrode is formed so as to be commonly connected to a plurality of source regions formed on the front surface. Thus, a current density varies based on in-plane resistance of the source electrode, thereby providing the necessity of increasing the number of wires connecting the sources and a lead. In the invention, an electrode structure includes a copper plating layer 10e formed on a pad electrode 10a by an electrolytic plating method, and a nickel plating layer 10f and a gold plating layer formed so as to cover the upper and side surfaces of the copper plating layer 10e by an electroless plating method.

Abstract: A flip-chip electrical coupling (100, 200, 300) is formed between first and second electrical components (110, 180; 410, 480). The coupling (100, 200, 300) includes a bump (240, 340) and a contact pad (315). The first electrical component (110, 210, 310, 410) includes the contact pad (315) electrically coupled to the first electrical component (110, 210, 310, 410) and a passivation layer (130, 230, 330) overlying the first electrical component (110, 210, 310, 410) and the contact pad (315). The passivation layer (130, 230, 330) is arranged having an opening (120, 220, 320) positioned over the contact pad (315). A bump (240, 340) is positioned overlying the opening (120, 220, 320) and substantially overlying the passivation layer (130, 230, 330). The bump (240, 340) is formed to be in electrical contact with the contact pad (315). The bump (240, 340) is arranged to couple the first and second electrical components (110, 180; 410, 480) during the flip-chip coupling process.

Abstract: A method of minimizing crosstalk in an IC package including (A) routing a first signal between first pads and a first trace layer in an congested area, (B) routing the first signal between the first and second trace layers in an non-congested area, (C) routing the first signal between the second trace layer and first pins in the non-congested area, (D) routing a second signal between second pads and the first trace layer in the congested area, (E) routing the second signal between the first and the second trace layers in the congested area and (F) routing the second signal between the second trace layer and second pins in the non-congested area, wherein (i) all of the first and second pins are arranged along a line and (ii) the first pins are offset from the second pins by a gap of at least two inter-pin spaces.

Abstract: A semiconductor device according to the present invention includes: a semiconductor chip; a sealing resin layer formed on the semiconductor chip; and a post electrode formed in a through-hole penetrating through the sealing resin layer in a thickness direction, and having a hemispheric top surface.

Abstract: A semiconductor die has a surface and an active region on the surface. A thick-film coating is applied to the surface of the semiconductor die to cover only a portion or entire of the active region before the semiconductor die is cut from a wafer. The thick-film coating reduces the stress to the semiconductor die. The thick-film coating does not cover the bonding pads of the semiconductor die to avoid influencing the bonding wires bonding to the boding pads.

Abstract: An integrated circuit package system provides a leadframe having a short lead finger, a long lead finger, and a support bar. A first die is placed in the leadframe. An adhesive is attached to the first die, the long lead finger, and the support bar. A second die is offset from the first die. The offset second die is attached to the adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant.

Abstract: A method (300) for fabricating an integrated circuit includes the step of providing a substrate having a semiconductor surface (305). For at least one masking level (e.g. gate electrode, contact or via) of the integrated circuit, a mask pattern for the masking level is partitioned into a first mask and at least a second mask (310). The first mask provides features in a first grid pattern and the second mask provides features in a second grid pattern. The first and second grid pattern have respective features that interleave with one another over at least one area. A first photoresist film is applied onto the surface of the substrate (315). The first grid pattern is printed using the first mask (320). The second grid pattern is printed using the second mask (325). The first and said second grid pattern are then etched into the surface of the substrate (330).

Abstract: The invention provides a connecting structure for a flip-chip semiconductor package in which cracking and delamination are inhibited or reduced to improve reliability, and in which the potential range of designs is expanded for the inner circuitry of circuit boards and the inductance is reduced. The invention is a connecting structure for a flip-chip semiconductor package, including: a circuit board having a core layer and at least one build-up layer; a semiconductor element connected via metal bumps to the circuit board; and a sealing resin composition with which gaps between the semiconductor element and circuit board are filled, wherein a cured product of the sealing resin composition has a glass transition temperature between 60° C. and 150° C. and a coefficient of linear expansion from room temperature to the glass transition temperature being between 15 ppm/° C. and 35 ppm/° C., a cured product of the build-up layer has a the glass transition temperature of at least 170° C.

Abstract: In a method for manufacturing a semiconductor module, a metal layer is formed on a support substrate. Then, first conductive posts and a first insulating layer are formed on the metal layer. The first insulating layer surrounds the sides of the first conductive posts. Then, second conductive posts are formed above the first conductive posts. The second conductive posts are electrically connected to the first conductive posts. Then, a second insulating layer is formed so as to cover the second conductive posts. The second insulating layer is made of adhesive resin. Finally, a semiconductor device is adhered to the second conductive posts by the second insulating layer while a gap between the first semiconductor device and the first insulating layer is sealed by the second insulating layer.

Abstract: A semiconductor device (20) in which a semiconductor element (2) is mounted on one of a front side and a back side of a wiring board (3), and a plurality of lands (9) (23) for external connection are provided on the other side of the wiring board, the land (9) (23) including a land terminal (10) (24) formed on the wiring board and a spherical solder ball (11) (25) formed on the land terminal, wherein a first land (23) immediately below an outer end corner (B) of the semiconductor element (2) is larger in size than the other lands (9).

Abstract: A chip package comprising a carrier, a chip, a plurality of first conductive elements, an encapsulation, and a conductive film is provided. The carrier has a carrying surface and a back surface opposite to the carrying surface. Furthermore, the carrier has a plurality of common contacts in the periphery of the carrying surface. The chip is disposed on the carrying surface and electrically connected to the carrier. In addition, the first conductive elements are disposed on the common contacts respectively. The encapsulation is disposed on the carrying surface and encapsulating the chip. Moreover, the conductive film is disposed over the encapsulation and the first conductive elements, so as to electrically connect with the common contacts via the first conductive elements. A process for fabricating the chip package is further provided. The chip package is capable of preventing the EMI problem and thus provides superior electrical performance.