Protection Against Radiation, E.g., Light, Electromagnetic Waves (epo) Patents (Class 257/E23.114)
  • Publication number: 20090302436
    Abstract: A shielded semiconductor device is made by mounting semiconductor die to a first substrate. An encapsulant is formed over the semiconductor die and first substrate. A dicing channel is formed through the encapsulant between the semiconductor die. A hole is drilled in the first substrate along the dicing channel on each side of the semiconductor die. A shielding layer is formed over the encapsulant and semiconductor die. The hole is lined with the shielding layer. The first substrate is singulated to separate the semiconductor die. The first substrate is mounted to a second substrate. A metal pillar is formed in the opening to electrically connect the shielding layer to a ground plane in the second substrate. The metal pillar includes a hook for a mechanically secure connection to the shielding layer. An interconnect structure is formed on the first substrate to electrically connect the semiconductor die to the second substrate.
    Type: Application
    Filed: June 10, 2008
    Publication date: December 10, 2009
    Applicant: STATS CHIPPAC, LTD.
    Inventors: OhHan Kim, SeungWon Kim, JoungUn Park
  • Patent number: 7629674
    Abstract: A shielded package includes a shield assembly having a shield fence, a shield lid, and a shield lid adhesive electrically coupling the shield lid to the shield fence. The shield fence includes a porous sidewall through which molding compound passes during molding of the shielded package. Further, the shield fence includes a central aperture through which an electronic component is die attached and wire bonded.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: December 8, 2009
    Assignee: Amkor Technology, Inc.
    Inventor: Donald Craig Foster
  • Publication number: 20090294928
    Abstract: A shielded semiconductor device is made by embedding a ground shield between layers of a substrate. Semiconductor die are mounted to the substrate over the ground shields. An encapsulant is formed over the semiconductor die and substrate. The encapsulant is diced to form dicing channels between the semiconductor die. A plurality of openings is drilled into the substrate along the dicing channels down through the ground shield on each side of the semiconductor die. A top shield is formed over the semiconductor die. The openings in the substrate are filled with a shielding material to electrically and mechanically connect the top shield to the ground shield. The substrate is singulated to separate the semiconductor die with top shield and ground shield into individual semiconductor devices. IPDs in the semiconductor die generate electromagnetic interference which is blocked by the respective top shield and ground shield.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 3, 2009
    Applicant: STATS CHIPPAC, LTD.
    Inventors: OhHan Kim, SunMi Kim, KyungHoon Lee
  • Publication number: 20090294931
    Abstract: An electronic component package having an EMI shielded space is disclosed. The package comprises a substrate having an electronic component located on its surface and a conductive enclosure having a top and downwardly extending sides enclosing the component and defining a shielded space. A vent opening is provided through the substrate and is located in the shielded space for venting the shielded space. A second vent opening may be provided in the top of the conductive enclosure.
    Type: Application
    Filed: August 10, 2009
    Publication date: December 3, 2009
    Inventors: Man-Lung Sham, Huili Fu, Chang-Hwa Chung
  • Publication number: 20090294930
    Abstract: The present invention relates to relates to a semiconductor package having a function of shielding electromagnetic interference (EMI), a manufacturing method thereof and a jig, and more particularly, to such a semiconductor package having an electromagnetic interference (EMI)-shielding function, a manufacturing method thereof and a jig for use in a plasma sputtering, in which a nickel alloy is coated on the surface of a semiconductor package by a sputtering method so as to shield electromagnetic interference (EMI) generated from the semiconductor package.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 3, 2009
    Inventors: Jum-chae YOON, Eun-soo Hyun, Seung-ki Kim
  • Publication number: 20090294929
    Abstract: A seal ring structure disposed along a periphery of an integrated circuit. The seal ring is divided into at least a first portion and a second portion. The second portion is positioned facing and shielding an analog and/or RF circuit block from a noise. A deep N well is disposed in a P substrate and is positioned under the second portion. The deep N well reduces the substrate noise coupling.
    Type: Application
    Filed: November 19, 2008
    Publication date: December 3, 2009
    Inventors: Tung-Hsing Lee, Tien-Chang Chang, Yuan-Hung Chung
  • Patent number: 7626247
    Abstract: A method and system for fabricating an electromagnetic radiation shield for an electronics package is disclosed. The electronics package includes a substrate, at least one ground contact feature, and a protective layer. The electronics package is physically coupled to at least one additional electronics package through at least the substrate. The method and system include exposing a portion of the ground contact feature(s) by removing a portion of the electronics package above the ground contact feature(s). The exposing step forms at least one trench above the ground contact feature(s). The method and system also include depositing an electromagnetic radiation shield that substantially covers the electronics package, fills the trench(es), and is electrically connected to the ground contact feature(s).
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: December 1, 2009
    Assignee: Atmel Corporation
    Inventor: Ken Lam
  • Publication number: 20090289335
    Abstract: An integrated circuit package system includes: providing a tie bar and a lead adjacent thereto; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield connected to the tie bar; and encapsulating the integrated circuit and the shield. An integrated circuit package system also includes: forming a lead and a support structure with substantially the same material as the lead and elevated above the lead; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield on the support structure; and encapsulating the integrated circuit and the shield.
    Type: Application
    Filed: May 21, 2008
    Publication date: November 26, 2009
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Henry Descalzo Bathan, Guruprasad Badakere Govindaiah
  • Publication number: 20090290320
    Abstract: A structure for blocking electromagnetic interference (EMI) may include at least one electromagnetic wave inducing member and an electromagnetic wave filtering member. The at least one electromagnetic wave inducing member may be provided to an electronic device to induce an electromagnetic wave applied to the electronic device. The electromagnetic wave filtering member may be provided to the electronic device to filter the electromagnetic wave induced by the at least one electromagnetic wave inducing member. Thus, the electromagnetic wave filtering member may remove the electromagnetic wave concentrated on the at least one electromagnetic wave inducing member, so that the electromagnetic wave applied to the electronic device may be effectively removed. As a result, circuits in the electronic device may be protected from the EMI.
    Type: Application
    Filed: May 20, 2009
    Publication date: November 26, 2009
    Inventor: Eun-Seok Song
  • Patent number: 7622793
    Abstract: A novel apparatus and method for providing a radio frequency (“RF”) input/output (“I/O”) land grid array (“LGA”) package structure. The package structure comprises grounded shield rings surrounding free-standing RF I/O interconnects. The free-standing RF I/O interconnects eliminate long leads and the shield rings provide ground protection thereby minimizing losses, inductance, leakage, and crosstalk, and improving performance.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: November 24, 2009
    Inventor: Richard A. Anderson
  • Publication number: 20090283876
    Abstract: A semiconductor package structure including a conductive adhesive material which is used to form an electromagnetic interference shield-forming Faraday cage. The Faraday cage incorporates a module lid as the top surface thereof, the conductive material as the sides and a laminate ground plane(s) or substrate as its bottom. Also disclosed is a method for fabricating the foregoing semiconductor package structure.
    Type: Application
    Filed: May 13, 2008
    Publication date: November 19, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: J. Richard Behun, Erwin B. Cohen
  • Publication number: 20090283877
    Abstract: A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.
    Type: Application
    Filed: May 15, 2009
    Publication date: November 19, 2009
    Applicant: Xintec Inc.
    Inventors: Chia-Lun Tsai, Ching-Yu Ni, Jack Chen, Wen-Cheng Chien
  • Publication number: 20090278240
    Abstract: Disclosed is a semiconductor apparatus that prevents diffusion of materials of a magnetic film during the process for manufacturing the semiconductor apparatus. The semiconductor apparatus includes: a substrate; a semiconductor device formed on a principal surface of the substrate and including an interconnect layer; a magnetic shielding film of a magnetic material covering the semiconductor device; and a buffer film disposed between the semiconductor device and the magnetic shielding film. The buffer film prevents diffusion of the magnetic material of the magnetic shielding film.
    Type: Application
    Filed: April 28, 2009
    Publication date: November 12, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Kishou Kaneko, Naoya Inoue, Yoshihiro Hayashi
  • Patent number: 7615841
    Abstract: A semiconductor structure for preventing coupling noise in integrated circuits and a method of forming the same are provided. The semiconductor structure includes a signal-grounded seal ring. The seal ring includes a plurality of metal lines, each in a respective metal layer and surrounding a circuit region of the semiconductor chip, a plurality of vias connecting respective metal lines, and a plurality of dielectric layers isolating each metal layer from any other metal layers. The seal ring may further include additional seal rings formed inside or outside the seal ring. The semiconductor structure may include laser fuses and protective rings. The protective rings are preferably signal grounded. Cross talk between sub circuits in a chip can be reduced by forming a seal ring extension between the sub circuits.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: November 10, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Hsueh-Chung Chen
  • Publication number: 20090273062
    Abstract: A semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the panel for receiving a semiconductor therein. The feet extend from respective channel walls for attachment to a substrate.
    Type: Application
    Filed: July 6, 2009
    Publication date: November 5, 2009
    Inventors: Virgil Cotoco Ararao, Il Kwon Shim, Seng Guan Chow, Sheila Marie L. Alvarez
  • Publication number: 20090261460
    Abstract: A semiconductor package has a first conductive layer formed on a top surface of a substrate. A conductive via is formed between the first conductive layer and a bottom surface of the substrate. A semiconductor component is mounted to the substrate and electrically connected to the first electrical contact pad. The semiconductor component can be a flip chip semiconductor device, wire bond semiconductor device, or passive component. An encapsulant is deposited over the semiconductor component. The encapsulant extends into a channel formed on a side of the substrate from the top surface to the bottom surface of the substrate. An interconnect structure is formed over the bottom surface of the substrate. A heat spreader structure can be disposed over the semiconductor component. An EMI shield can be disposed over the semiconductor component. A plurality of semiconductor components can be stacked in a package-in-package arrangement.
    Type: Application
    Filed: June 26, 2009
    Publication date: October 22, 2009
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Heap Hoe Kuan, Seng Guan Chow, Linda Pei Ee Chua
  • Publication number: 20090256244
    Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of an internal grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.
    Type: Application
    Filed: June 22, 2009
    Publication date: October 15, 2009
    Inventors: Kuo-Hsien Liao, Chi-Tsung Chiu, Chih-Pin Hung
  • Publication number: 20090251131
    Abstract: A current determiner comprising a first input conductor and a first current sensor, formed of a plurality of magnetoresistive, anisotropic, ferromagnetic thin-film layers at least two of which are separated from one another by a nonmagnetic layer positioned therebetween, and both supported on a substrate adjacent to but electrically isolated from one another with the first current sensor positioned in those magnetic fields arising from any input currents. A first shield/concentrator of a material exhibiting a substantial magnetic permeability is positioned between the substrate and the first input conductor. The substrate can include a monolithic integrated circuit structure containing electronic circuit components of which at least one is electrically connected to the first input conductor.
    Type: Application
    Filed: June 10, 2009
    Publication date: October 8, 2009
    Applicant: NVE Corporation
    Inventors: John K. Myers, James M. Daughton
  • Patent number: 7598596
    Abstract: A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: October 6, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jaynal A. Molla, Gregory W. Grynkewich, Eric J. Salter
  • Patent number: 7598606
    Abstract: An integrated package system with die and package combination including forming a leadframe having internal leads and external leads, encapsulating a first integrated circuit on the leadframe, and encapsulating a second integrated circuit over the first integrated circuit.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: October 6, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Ming Ying, Il Kwon Shim
  • Publication number: 20090243052
    Abstract: An electronic device includes a substrate, an active circuit, and a shielding structure. The active circuit is formed on the substrate. The shielding structure is disposed surrounding the active circuit, and includes a first heavy ion-doped region, first metal stack, second heavy ion-doped region, second metal stack and top metal. The first heavy ion-doped is formed in the substrate and located at a first side of the active circuit. The first metal stack is formed on the first heavy ion-doped region of the substrate, wherein the first metal stack is connected to a ground voltage. The second heavy ion-doped region is formed in the substrate and located at a second side of the active circuit. The second metal stack is formed on the second heavy ion-doped region of the substrate. The top metal is formed on the first metal stack and second metal stack and passing over the active circuit.
    Type: Application
    Filed: March 26, 2008
    Publication date: October 1, 2009
    Applicant: MaxRise Inc.
    Inventor: Hwey-Ching Chien
  • Publication number: 20090243051
    Abstract: Microelectronic device assemblies having integrated conductive shields are disclosed herein. The microelectronic device assemblies include a semiconductor substrate having a bond site and a solder ball electrically connected to the bond site, a dielectric sidewall at least partially encapsulating the semiconductor substrate, and a conductive shield in direct contact with the sidewall and in electrical communication with the solder ball and the bond site.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kiran Kumar Vanam, Alan G. Wood, James M. Derderian, Derek J. Gochnour, Owen R. Fay, Luke G. England
  • Publication number: 20090243012
    Abstract: A microelectronic device assembly with an integrated conductive shield is disclosed herein. The microelectronic device assembly includes a semiconductor substrate, an integrated circuit carried by the semiconductor substrate, a dielectric encapsulant encasing at least a portion of the semiconductor substrate. The microelectronic device assembly also includes a conductive shield in direct contact with at least a portion of the dielectric encapsulant and an interconnect extending through the semiconductor substrate and in direct contact with the conductive shield.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kiran Kumar Vanam, Derek J. Gochnour, Alan G. Wood, James M. Derderian, Luke G. England, Owen R. Fay
  • Publication number: 20090236700
    Abstract: A semiconductor device includes a wiring board, a semiconductor element mounted on the wiring board, a sealing resin configured to cover the semiconductor element, a ground electrode having an end connected to a wiring layer of the wiring board and an exposing part exposed at a surface of the sealing resin, and a shielding member configured to cover the sealing resin and be connected to the ground electrode.
    Type: Application
    Filed: June 8, 2009
    Publication date: September 24, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Susumu MORIYA
  • Publication number: 20090224376
    Abstract: A circuit board having a board body includes a via structure. The via structure includes a conductive connector passing through the board body and a conductive shield member surrounding at least a portion of the conductive connector. The shield member prevents distortion of a data signal applied to the conductive connector, and also intercepts electromagnetic waves generated by the conductive connector.
    Type: Application
    Filed: May 8, 2008
    Publication date: September 10, 2009
    Inventors: Bok Kyu CHOI, Sang Joon LIM, Eul Chul JANG
  • Publication number: 20090218701
    Abstract: An integrated circuit includes a first integrated circuit die having a first circuit and a first inductive interface and a second integrated circuit die having a second circuit and a second inductive interface. A substrate is coupled to support the first integrated circuit die and the second integrated circuit die, the substrate including a magnetic communication path aligned with the first inductive interface and the second inductive interface, to magnetically communicate signals between the first circuit and the second circuit.
    Type: Application
    Filed: February 28, 2008
    Publication date: September 3, 2009
    Applicant: BROADCOM CORPORATION
    Inventor: Ahmadreza (Reza) Rofougaran
  • Patent number: 7582951
    Abstract: Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages is described. A die-up or die-down package includes a heat spreader cap defining a cavity, an IC die, and a leadframe. The leadframe includes a centrally located die attach pad, a plurality of leads, and a plurality of tie bars that couple the die attach pad to the leads. The IC die is mounted to the die attach pad. A planar rim portion of the cap that surrounds the cavity is coupled to the leadframe. The cap and the leadframe form an enclosure structure that substantially encloses the IC die, and shields EMI emanating from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: September 1, 2009
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Reza-ur Rahman Khan
  • Patent number: 7582959
    Abstract: A driver module structure includes a flexible circuit board (2) provided with a wiring pattern (7), a semiconductor device mounted on the flexible circuit board (2), and an electrically conductive heat-radiating member (4) joined to the semiconductor device. The wiring pattern (7) includes a ground wiring pattern (8). The flexible circuit board (2) has a cavity (9) that exposes a portion of the ground wiring pattern (8). The exposed portion of the ground wiring pattern (8) and the heat-radiating member (4) are connected to establish electrical continuity via a member (11) that is fitted into the cavity (9).
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: September 1, 2009
    Assignee: Panasonic Corporation
    Inventor: Hiroyuki Fukusako
  • Publication number: 20090212401
    Abstract: The present invention provides a package system including: providing a semiconductor die with a contact pad and a ground pad, mounting the semiconductor die on a package substrate using and adhesive layer, forming a vertical conductive structure on top of the ground pad in the semiconductor die, encapsulating at least portions of the semiconductor die, the vertical conductive structure, and the package substrate using an encapsulant, covering at least portions of the encapsulant and the vertical conductive structure with a shielding layer to place the vertical conductive structure in electrical contact with the shielding layer, and connecting the shielding layer to the package substrate.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 27, 2009
    Inventors: Byung Tai Do, Rui Huang, Seng Guan Chow, Heap Hoe Kuan
  • Publication number: 20090212402
    Abstract: Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect.
    Type: Application
    Filed: April 24, 2009
    Publication date: August 27, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Yasutaka NAKASHIBA
  • Patent number: 7579672
    Abstract: A semiconductor package with electromagnetic shielding capabilities is disclosed. The semiconductor package includes a substrate (101), a plurality of semiconductor dies (102), a plurality of shielding metal elements (103), a plurality of grounding metal elements (104) and a plurality of conductive metal elements (110). The semiconductor dies are disposed on an upper surface (105) of the substrate along a horizontal direction. The shielding metal elements are provided on the upper surface of the substrate, and are arranged between and around the semiconductor dies so that each semiconductor die is surrounded by the shielding metal elements and thus electromagnetic interference in the horizontal direction can be effectively shielded from each semiconductor die.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: August 25, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Chia-fu Wu
  • Publication number: 20090206455
    Abstract: A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top surface has an IC die attached thereon. A second portion of the top surface has a plurality of first attach pads on opposing sides of the IC die for electrically coupling to a first electronic device on top of the IC die. At least a third portion of the top surface is positioned laterally with respect to the first and second portion. The third portion includes a plurality of second attach pads for electrically coupling to at least a second electronic device. At least one of the electrically conductive layers includes a coupling trace that couples at least one of the plurality of second attach pads to the IC die and/or one or more of the plurality of first attach pads.
    Type: Application
    Filed: February 19, 2009
    Publication date: August 20, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: PETER R. HARPER, KENNETH MAGGIO
  • Publication number: 20090200648
    Abstract: A method and system is disclosed for facilitating miniaturization of an electronic device by efficiently utilizing available space. Specifically, in an exemplary embodiment, there is provided an electronic device comprising a substrate, a cavity formed in the substrate, and a bridge coupled to the substrate such that it spans the cavity. Further, the device may include a semiconductor device coupled to the bridge such that the semiconductor device is positioned within the cavity. In some embodiments, the bridge may include a tape automated bonding (TAB) tape having various layers, including a layer configured to provide electromagnetic shielding.
    Type: Application
    Filed: February 8, 2008
    Publication date: August 13, 2009
    Inventor: Irvin W. Graves, JR.
  • Publication number: 20090200647
    Abstract: An integrated circuit pad structure includes a ground strip (206) positioned below a pad (101). In one example a conductive element (102) is coupled to the pad (101), and at least two tiled layers, positioned below the first conductive element (102) and positioned above the ground strip (206) are included. A conductor (203), may run beneath the ground strip (206). In a second example, a pad (101) is seated on a ground shield cage having a bottom conductive ground element (302) including several ground strips where at least one ground strip (116) is along a signal routing path. The ground shield cage further includes a set of stacked conductive ground elements, stacked to form sidewalls (209, 210) of the cage. The top conductive ground element (301) of the stacked elements has an inner perimeter and an outer perimeter, such that the inner perimeter surrounds the pad (101) and the top conductive ground element (301) is in the plane of the conductive element (102) coupled to the pad (101).
    Type: Application
    Filed: February 8, 2008
    Publication date: August 13, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jyoti P. Mondal, David B. Harr
  • Patent number: 7573124
    Abstract: A semiconductor packaging structure having electromagnetic shielding function is disclosed, in which the packaging structure includes a carrier and a semiconductor substrate disposed thereon. The semiconductor substrate has a patterned passivation layer and a patterned metal layer disposed thereon, in which the patterned metal layer is electrically connected to at least a grounding pad of the carrier via a wire, whereby possessing the semiconductor packaging structure to have electromagnetic shielding function. A method for manufacturing a semiconductor packaging structure having electromagnetic shielding function is also disclosed in the present invention.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: August 11, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Meng-Jen Wang, Kuo-Pin Yang, Wei-Min Hsiao, Sheng-Yang Peng
  • Publication number: 20090194852
    Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) a grounding element disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface; (4) a package body disposed adjacent to the upper surface and covering the semiconductor device and the grounding element; and (5) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a lateral surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The grounding element corresponds to a remnant of a conductive bump, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.
    Type: Application
    Filed: December 16, 2008
    Publication date: August 6, 2009
    Inventors: Chi-Tsung Chiu, Chih-Pin Hung, Jui-Cheng Huang
  • Publication number: 20090194851
    Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element disposed adjacent to a periphery of the substrate unit; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of tile package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of a grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.
    Type: Application
    Filed: December 16, 2008
    Publication date: August 6, 2009
    Inventors: Chi-Tsung Chiu, Chih-Pin Hung, Jui-Cheng Huang
  • Publication number: 20090194853
    Abstract: A method of manufacture of a shielded stacked integrated circuit packaging system includes forming a first integrated circuit structure having a first substrate and a first integrated circuit die; mounting a shield over the first substrate and the first integrated circuit die; mounting a second integrated circuit structure having a second substrate and a second integrated circuit die over the shield; and forming a package encapsulation for covering the first integrated circuit die, the shield, and the second integrated circuit structure.
    Type: Application
    Filed: April 14, 2009
    Publication date: August 6, 2009
    Inventors: Ki Youn Jang, YoungMin Kim, Hyung Jun Jeon
  • Patent number: 7569915
    Abstract: A shielding arrangement for protecting a circuit containing magnetically sensitive materials from external stray magnetic fields. A shield of a material having a relatively high permeability is formed over the magnetically sensitive materials using thin film deposition techniques. Alternatively, a planar shield is affixed directly to a surface of semiconductor die containing an integrated circuit structure.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: August 4, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Richard K. Spielberger, Romney R. Katti
  • Patent number: 7569922
    Abstract: A semiconductor device includes: a first semiconductor chip face-down mounted on a substrate; a second semiconductor chip face-up mounted on the first semiconductor chip; an electromagnetic shielding plate inserted between the first semiconductor chip and the second semiconductor chip; and a bonding wire bonded on the substrate so as to be astride of the electromagnetic shielding plate.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: August 4, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiharu Ogata
  • Publication number: 20090184404
    Abstract: An electromagnetic shielding structure for a multi-chip package module includes a substrate having at least one conductive point, a plurality of chips, an encapsulating body and an electromagnetic shielding layer. Wherein the chips are arranged and encapsulated by the encapsulating body on the substrate. The electromagnetic shielding layer is arranged on the encapsulating body and the conductive point to shield highly frequency electromagnetic wave by printing. Meanwhile, the electromagnetic shielding layer can replace the conventional metal shell to reduce the whole size of the multi-chip package module.
    Type: Application
    Filed: April 30, 2008
    Publication date: July 23, 2009
    Inventor: En-Min Jow
  • Publication number: 20090184403
    Abstract: An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed by forming a conductive layer (34, 46) over an encapsulant (32). The conductive layer includes a combination of a conductive glue (38, 48, 52) and a metal paint (36, 50). A wire loop (30) is coupled to the conductive layer and a leadframe (10).
    Type: Application
    Filed: September 14, 2005
    Publication date: July 23, 2009
    Applicant: FREESCALE SEMICONDUCTOR. INC.
    Inventors: Zhi-Jie Wang, Jian-Yong Liu
  • Publication number: 20090184405
    Abstract: A package structure is provided. The package structure includes a substrate, a semiconductor device, and a shielding cap. The substrate has at least an alignment recess located at a corner of the substrate. The semiconductor device is disposed on an upper surface of the substrate. The shielding cap having an alignment pin covers the semiconductor device. The alignment pin is inserted into the alignment recess.
    Type: Application
    Filed: June 24, 2008
    Publication date: July 23, 2009
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Hsin-Chieh Lu
  • Publication number: 20090179311
    Abstract: A semiconductor component of semiconductor chip size includes a semiconductor chip. The semiconductor chip has a metallic coating that completely covers the side edges, the rear side and the top side, on which surface-mountable external contacts are arranged. One embodiment includes power semiconductor components, wherein the metallic coating connects a rear side electrode to one of the surface-mountable external contacts on the top side of a power semiconductor chip.
    Type: Application
    Filed: March 20, 2009
    Publication date: July 16, 2009
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Matthias Stecher
  • Publication number: 20090180733
    Abstract: A system package using flexible optical waveguides and electrical wires, and a signal processing method thereof are disclosed. Several rigid substrates having highly integrated electronic elements and optical elements mounted thereon can be electrically and optically connected by using flexible substrates that are electrically wired and optically connected. The package can be variously changed when configuring the package by the flexible substrate and the heat dissipation device and the electromagnetic shielding device are installed in the inside of the package, making it possible to solve electromagnetic wave interference problems and thermal problems occurring in the inside of the package.
    Type: Application
    Filed: January 9, 2009
    Publication date: July 16, 2009
    Applicant: KOREA PHOTONICS TECHNOLOGY INSTITUTE
    Inventors: Sung Hwan HWANG, Byung Sup Rho, Jung Woon Lim, Woo Jin Lee
  • Patent number: 7560329
    Abstract: The semiconductor device comprises a gate electrode 112 formed over a semiconductor substrate 10, a sidewall spacer 116 formed on the side wall of the gate electrode 112, a sidewall spacer 144 formed on the side wall of the gate electrode 112 with the sidewall spacer 116 formed on, and an oxide film 115 formed between the sidewall spacer 116 and the sidewall spacer 144, and the semiconductor substrate 10. The film thickness of the oxide film 115 between the sidewall spacer 144 and the semiconductor substrate 10 is thinner than the film thickness of the oxide film 115 between the sidewall spacer 116 and the semiconductor substrate 10.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: July 14, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Shinichi Nakagawa
  • Publication number: 20090174041
    Abstract: Structures and methods for blocking ultraviolet rays during a film depositing process for semiconductor device are disclosed. In one embodiment, a semiconductor device includes an oxide-nitride-oxide (ONO) film formed on a semiconductor substrate, a gate electrode formed on the ONO film, a lower layer insulation film formed on the ONO film and the gate electrode, and a ultraviolet (UV) blocking layer based on a plurality of granular particles scattered in at least one insulation film formed on lower layer insulation film, where the UV blocking layer suppresses UV rays generated during an additional film deposition from reaching the ONO film.
    Type: Application
    Filed: June 5, 2008
    Publication date: July 9, 2009
    Inventor: Naoki TAKEGUCHI
  • Publication number: 20090166819
    Abstract: A chipset package structure includes a carrier, a plurality of pinouts, at least one semiconductor package preforms, at least one electromagnetic shielding layer and a protective layer. The pinouts are disposed on the carrier. The semiconductor package preforms is disposed on the second surface of the carrier and electrically connected to the pinouts. The electromagnetic shielding layer is disposed on the semiconductor package preforms and the electromagnetic shielding layer. At least one of the electromagnetic shielding layers comprises a carbon nanotube film structure. The protective layer covers the electromagnetic shielding layer.
    Type: Application
    Filed: October 9, 2008
    Publication date: July 2, 2009
    Applicants: TSINGHUA UNIVERSITY, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: WEN-HUA CHEN, ZHENG-HE FENG, PING-YANG CHUANG
  • Patent number: 7550833
    Abstract: A semiconductor device comprises a plurality of semiconductor constructions being mutually laminated each having a semiconductor substrate and a plurality of external connection electrodes arranged on the semiconductor substrate respectively, an insulating layer formed around the peripheries of the semiconductor constructions, an upper layer insulating film formed on an uppermost one of the semiconductor constructions and the insulating layer, and upper layer wirings arranged on the upper layer insulating film by electrically connecting to the external connection electrodes of semiconductor constructions.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: June 23, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventor: Ichiro Mihara
  • Publication number: 20090152688
    Abstract: An integrated circuit package system comprising: providing a substrate; coupling an integrated circuit to the substrate; mounting a shielding element around the integrated circuit; applying a conductive shielding layer on the shielding element; and coupling a system interconnect to the shielding element.
    Type: Application
    Filed: December 13, 2007
    Publication date: June 18, 2009
    Inventors: Byung Tai Do, Heap Hoe Kuan, Rui Huang