Abstract: Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect.

Abstract: There is provided a semiconductor chip mounting substrate including a substrate on which a mounting region for mounting a semiconductor chip and a connection region for interlayer connection of the semiconductor chip are formed, and a plurality of alignment marks for alignment at the time of stacking which are provided around or in the connection region on the substrate, wherein a reinforcing member as a reinforcing region for reinforcing a portion between the plurality of alignment marks is provided on the substrate.

Abstract: A magnetic memory device in which an MRAM element is magnetically shielded from large external magnetic fields. The magnetic memory device includes: a substrate; a magnetic random access memory mounted on the substrate, the magnetic random access memory including a memory element having a magnetized pinned layer with fixed direction of magnetization and a magnetic layer with changeable direction of magnetization stacked on one another; another element mounted on the substrate; and a pair of magnetic shielding layers which magnetically shield the memory element, the magnetic shielding layers located relatively above and below the memory element and within a region corresponding to an area occupied by the memory element.

Abstract: An example of a circuit structure may include a first dielectric layer having first and second surfaces, and a channel extending at least partially between the first and second surfaces and along a length of the first dielectric layer. First and second conductive layers may be disposed on respective portions of the first and second surfaces. A first conductor, having an end, may be disposed on a surface of the first dielectric layer, including at least a first portion extending around at least a portion of the conductor end. The second conductive layer may line the channel extending around a portion of the conductor end. Some examples may include a stripline having a second conductor connected to the first conductor. Some examples may include a cover having a wall positioned on the first dielectric over the second conductor.

Abstract: A shielded electronic package, comprising a semiconductor device, an insulating housing surrounding the semiconductor device and a metal coating on the insulating housing. The metal coating covers all but those portions of the insulating housing that are adjacent to connective structures on one or more mounting sides of the insulating housing.

Abstract: Disclosed is a semiconductor device which has a circuit-forming region. The semiconductor device has a semiconductor substrate, a plurality of insulating interlayer films, a guard ring, and a first MIM capacitor. The insulating interlayer films, which are stacked one upon another, are provided over the semiconductor substrate. The guard ring is formed in the plurality of insulating interlayer films and surrounds the circuit-forming region. The guard ring is separated from an insulating interlayer film including a topmost interconnect. The MIM capacitor is provided between the guard ring and the insulating interlayer film including the topmost interconnect.

Abstract: A sheet to form a protective film for chips includes a release sheet and a protective film forming layer formed on a detachable surface of the release sheet. The protective film forming layer includes a thermosetting and/or energy ray-curable component and a binder polymer component.

Abstract: A semiconductor package with electromagnetic shielding capabilities is disclosed. The semiconductor package includes a substrate (101), a plurality of semiconductor dies (102), a plurality of shielding metal elements (103), a plurality of grounding metal elements (104) and a plurality of conductive metal elements (110). The semiconductor dies are disposed on an upper surface (105) of the substrate along a horizontal direction. The shielding metal elements are provided on the upper surface of the substrate, and are arranged between and around the semiconductor dies so that each semiconductor die is surrounded by the shielding metal elements and thus electromagnetic interference in the horizontal direction can be effectively shielded from each semiconductor die.

Abstract: A semiconductor package with an electromagnetic shield is disclosed. The semiconductor package includes two substrates (102, 202; 103, 203) and an electromagnetic shield (101, 201). Each substrate has at least one die (108, 208; 112, 212) provided thereon. The electromagnetic shield is disposed between the two substrates for shielding electromagnetic interference between adjacent dies of the two substrates. One of the two substrates defines a cavity (109, 209) for partially accommodating the electromagnetic shield. Accordingly, the overall vertical height and the volume of the semiconductor package are not increased, and the heat dissipation efficiency of the semiconductor package is enhanced.

Abstract: A cap package includes a substrate on which a chip is mounted. A cap is made of silicon doped with non-metal dopant. The cap is capped on the substrate to define with the substrate an accommodation chamber that receives the chip inside. The chip is electrically connected with a conducting portion of the substrate which is grounded.

Abstract: A chip module having a chip which is mounted by means of chip adhesive on a mount and is electrically connected via bonding wires to contact pads, and an encapsulation compound which surrounds the chip and the bonding wires and is bounded by a subarea of the mount. The encapsulation compound is radiation-hardened and heat-hardened in a combined form and has radiation-impermeable pigments.

Abstract: A package includes: a package body including a substrate, an electronic component mounted on a first surface of the substrate, and a sealing resin layer for sealing the electronic component; and a shield case for covering the sealing resin layer, the shield case being made of metal and having an inverted U-shape in a cross-sectional view, wherein a bent part of the shield case is formed in such a manner that at least a part of an end of the shield case is bent toward a second surface of the substrate opposite to the first surface, and the bent part abuts on the second surface so that the shield case is attached to the substrate.

Abstract: A package may comprise a substrate provided with noise absorbing material. The noise absorbing material may absorb noise from a signal path in the substrate to prevent the noise from reaching other signals or signal paths.

Abstract: The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging.

Abstract: With respect to the central plane which horizontally cuts a multi-chip module, constituent materials of the same type are disposed in a plane symmetrical manner. Each of an upper structure and a lower structure, which sandwich the central plane which horizontally cuts the multi-chip module, includes a base and electronic components, as the aforesaid constituent materials.

Abstract: A shielded stacked integrated circuit package system is provided including forming a first integrated circuit structure having a first substrate and a first integrated circuit die; mounting a shield over the first substrate and the first integrated circuit die; mounting a second integrated circuit structure having a second substrate and a second integrated circuit die over the shield; and forming a package encapsulation for covering the first integrated circuit die, the shield, and the second integrated circuit structure.

Abstract: A novel apparatus and method for providing a radio frequency (“RF”) input/output (“I/O”) land grid array (“LGA”) package structure. The package structure comprises grounded shield rings surrounding free-standing RF I/O interconnects. The free-standing RF I/O interconnects eliminate long leads and the shield rings provide ground protection thereby minimizing losses, inductance, leakage, and crosstalk, and improving performance.

Abstract: A semiconductor device package includes a semiconductor device mounted to a substrate, a wall erected around the semiconductor device with a height taller than the height of the semiconductor device, at least one metal member provided in the wall or against the wall; and a lid secured to the metal member. The metal member and the lid enclose substantially the semiconductor device for providing electromagnetic interference shielding.

Abstract: The invention relates to a method for producing a rewiring printed circuit board with a substrate wafer having passage connections between a first and a second surface. One embodiment of the method comprises applying and patterning masking layers on the first and the second surfaces, thereby uncovering a first contact location on the first surface and a second contact location on the second surface; applying a protective layer to the second surface in order to protect the corresponding masking layer and the second contact location during subsequent method steps; applying a first conductor structure to the first surface, the first conductor structure on the first surface covering the first contact location; removing the protective layer on the second surface; and applying a second conductor structure to the second surface, the second conductor structure on the second surface covering the second contact location.

Abstract: A semiconductor device with a plastic housing composition includes a semiconductor chip and an internal wiring. The plastic housing composition is electrically conductive and electrically connected to a first contact pad of the internal wiring. A first side of the semiconductor chip is electrically insulated from the plastic housing composition by an insulation layer.

Abstract: A three dimensional integrated circuit structure includes at least first and second devices, each device comprising a substrate and a device layer formed over the substrate, the first and second devices being bonded together in a stack, wherein the bond between the first and second devices comprises a metal-to-metal bond and a non-metal-to-non-metal bond.

Abstract: A method of forming a micro-pattern in a semiconductor device that is less than approximately 130 nm using the KrF exposure equipment. A method of forming a micro-pattern in a semiconductor device includes at least one of the following steps: Forming an etching layer, a hard mask layer, an organic bottom anti-reflection (BARC) layer, and/or a photoresist film on and/or over a semiconductor substrate. Forming a photoresist pattern by exposing and developing the photoresist film. Forming a BARC layer pattern using the photoresist pattern as a mask. Forming a hard mask layer pattern using the BARC layer pattern as an etch mask. Forming an etching layer pattern by using the hard mask layer pattern as an etch mask.

Abstract: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.

Abstract: Various structures chip packages are disclosed including a magnetoresistive random access memory (“MRAM”) device and a magnetic shield structure. The magnetic shield structure may be made from material having either ferromagnetic or diamagnetic material and may be shaped and incorporated into the chip package to divert stray magnetic fields away from the MRAM device.

Abstract: A structure for shielding high frequency passive elements includes a first face of a semi-conductive substrate in parallel with a second face of a non-conductive substrate. The first face of the semi-conductive substrate is substantially parallel to a second face thereof. A passive element is disposed in the non-conductive substrate and is isolated from the second face of the non-conductive substrate. A plurality of conductive conduits disposed in the semi-conductive substrate extends from the first face to the second face thereof, each of the conduits isolated from one another by the semi-conductive substrate material and disposed substantially beneath the passive element. A ground plane disposed on the second face of the semi-conductive substrate electrically connects the conductive conduits disposed therein. An electrical connection between an electronic circuit in the semi-conductive substrate, the passive element and the ground plane holds the passive device and the ground plane at different potentials.

Abstract: A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.

Abstract: A semiconductor chip package may include a substrate, which may have bonding pads formed thereon. A semiconductor chip mounted on the substrate may have chip pads, and electrical connections for connecting the chip pads of the semiconductor chip to the substrate bonding pads. The semiconductor chip and the electrical connections on the substrate may be encapsulated, and a board attached to a portion of a surface of the substrate may not be encapsulated.

Abstract: A semiconductor package includes a semiconductor chip having first and second pads, a first insulation layer pattern formed on the semiconductor chip and having first and second openings that expose the first and the second pads, respectively, a first conductive layer pattern elongated along the first insulation layer pattern from the first pad, a first external terminal formed on the first conductive layer pattern, a second insulation layer pattern formed on the first conductive layer pattern and the first insulation layer pattern to expose the first external terminal and having a third opening in communication with the second opening, a second conductive layer pattern elongated along the second insulation layer pattern from the second pad, and a second external terminal formed on the second conductive layer pattern.

Abstract: A semiconductor element capable of reducing noises of a circuit propagating to another circuit through a seal ring is provided. A semiconductor element includes, on a surface of a semiconductor substrate: a plurality of circuits; a ring-shaped seal ring surrounding the plurality of circuits; and wiring connecting between the seal ring and an external low-impedance node.

Abstract: In the case of a chip (1) having an integrated circuit (2), a dielectric mirror coating (3) having at least two dielectric layers (6, 7, . . . H, I, H) is applied as light protection means for the at least one integrated circuit (2) on at least one portion of the surface of the chip (1).

Abstract: A semiconductor package includes a chip including a conductive pattern thereon, a conductive network attached on a surface of the chip to absorb static electricity, at least one conductive rod attached to the conductive network, wherein the at least one conductive rod is formed substantially perpendicularly to the conductive network, and a grounding portion discharging the static electricity absorbed from the conductive network.

Abstract: A semiconductor device package includes a plurality of stacked semiconductor chips and a spacer interposed therebetween. The spacer includes a first spacer and a second spacer stacked on one another. The first and the second spacers have different principal surfaces. If the second spacer has a larger principal surface than the first spacer, flexure of the upper semiconductor chip can be avoided.

Abstract: A semiconductor packaging structure having electromagnetic shielding function is disclosed, in which the packaging structure includes a carrier and a semiconductor substrate disposed thereon. The semiconductor substrate has a patterned passivation layer and a patterned metal layer disposed thereon, in which the patterned metal layer is electrically connected to at least a grounding pad of the carrier via a wire, whereby possessing the semiconductor packaging structure to have electromagnetic shielding function. A method for manufacturing a semiconductor packaging structure having electromagnetic shielding function is also disclosed in the present invention.

Abstract: An electronic circuit package and fabricating method thereof. The method includes: integrating a radio frequency circuit device and a semiconductor die on a printed circuit board; forming a bumper pad of metal on the printed circuit board around the radio frequency circuit device; forming a molding on the printed circuit board to include the radio frequency circuit device and the semiconductor die therein; and forming one or more grooves on a portion of the molding and inserting a can into the grooves. The electronic circuit package includes: a printed circuit board; a radio frequency circuit device and a semiconductor die integrated on the printed circuit board; a molding formed on the printed circuit board to include the radio frequency circuit device and the semiconductor die therein; one or more grooves formed in the molding to enclose the radio frequency circuit device; and a can inserted into the grooves.

Abstract: A semiconductor package includes a semiconductor chip; and an encapsulant for covering the semiconductor chip, such that the encapsulant includes a molding part for covering the semiconductor chip to protect the semiconductor chip from the external environment; and an electromagnetic shielding part for covering an outer surface of the molding part and containing therein electrically conductive particles for shielding an electromagnetic wave radiated from the semiconductor chip to the outside and an electromagnetic wave incident from the outside to the semiconductor chip.

Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device.

Abstract: An electrical circuit includes a multilayer printed circuit board and a housing which shields against electromagnetic interference. A portion of at least one outer layer of the printed circuit board are in the form of contact areas which are connected to a respective conductor area on a further layer of the printed circuit board. The conductor area occupies an area region that is offset with respect to the contact area and forms a bushing capacitor with a ground area of the outer layer.

Abstract: The present invention discloses an electronic package to contain and protect an integrated circuit (IC) chip. The electronic package further includes a leadframe, a flexible circuit or PCB type of substrate. The leadframe, flexible circuit or PCB type substrate further includes solder contacts, which are aligned with via holes in the molding layers on the top and bottom sides of the package. These via holes are for placing solder paste or solder balls from above and below for electrical access to the IC chip. These solder balls provide access for electrical testing after the package is mounted on a motherboard. They also provide the connection points for stacking multiple packages vertically.

Abstract: Disclosed is a stacked integration module having a small thickness while guaranteeing thermal and operational stabilities when operated at high frequencies. The stacked integration module includes a printed circuit board having first and second surfaces facing each other, at least one hole extending through the first and second surfaces, and a recess formed on the second surface; and a metallic member having an upper surface, the second surface of the printed circuit board being seated on the upper surface while making contact with the upper surface. The stacked integration module is simpler than conventional modules in terms of structure and process. The metallic member, which is made of a plate-shaped material having a larger area than conventional heat-radiation means, is advantageous for cooling and electromagnetic wave shielding.

Abstract: A semiconductor device package includes a semiconductor device mounted to a substrate, a wall erected around the semiconductor device with a height taller than the height of the semiconductor device, at least one metal member provided in the wall or against the wall; and a lid secured to the metal member. The metal member and the lid enclose substantially the semiconductor device for providing electromagnetic interference shielding.

Abstract: A semiconductor device has a semiconductor substrate; a shielding element formed by a conductor on a top side of the semiconductor substrate; an active element formed by a conductor and a semiconductor on the top side of the semiconductor substrate; a dielectric layer formed between the shielding element and the active element to electrically isolate the shielding element and the active element. The shielding element includes a first conductor layer formed as a flat plate, and a first external contact that is formed on the top side of the first conductor layer and is connected to the first conductor layer; and the active element includes a second conductor layer that is formed between the semiconductor substrate and the first conductor layer, and is connected to the semiconductor substrate.

Abstract: A capacitive structure and technique for allowing near-instantaneous charge transport and reliable, wide-band RF ground paths in integrated circuit devices such as integrated circuit dies, integrated circuit packages, printed circuit boards, and electronic circuit substrates is presented. Methods for introducing resistive loss, dielectric loss, magnetic loss, and/or radiation loss in a signal absorption ring implemented around a non-absorptive area of one or more conductive layers of an integrated circuit structure to dampen laterally flowing Electro-Magnetic (EM) waves between electrically adjacent conductive layers of the device are also presented.

Abstract: A multilayer dielectric substrate that mounts a semiconductor device in a cavity formed on a substrate. The multilayer dielectric substrate includes an opening formed in a surface-layer grounding conductor on the substrate in the cavity, and an impedance transformer, with a length of about ¼ of an in-substrate effective wavelength of a signal wave, electrically connected through the opening to the cavity. The multilayer dielectric substrate further includes a short-circuited end dielectric transmission line with a length of about ¼ of the in-substrate effective wavelength of the signal wave, a coupling opening formed on an inner-layer grounding conductor in a connecting section of the impedance transformer and the dielectric transmission line, and a resistor formed in the coupling opening.

Abstract: A surface acoustic wave device has a SAW device element 10 and a package 20 housing the SAW device element. The package includes a resin substrate 20 having metal patterns 21 and 22 formed on both surfaces thereof, and a resin cap 32. The SAW device element is mounted on one of the metal patterns of the resin substrate. The resin cap is adhered to the resin substrate to cover the SAW device element. The surfaces of the resin substrate are flush with corresponding end surfaces of the resin cap.

Abstract: In a semiconductor chip, a body has a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces. A plurality of electrode pads are formed on the top surface of the body to connect to an external terminal. A shielding conductive film is formed on the surfaces excluding the top surface of the body where the pattern is formed. A conductive via is extended through the body to connect one of the electrode pads with the conductive film.

Abstract: To provide a shield substrate, semiconductor package and semiconductor device which can give improved resistance to thermal stress. The shield substrate according to this invention is provided with a conductive film on which slits each having a shape through which electromagnetic wave noise does not leak are formed. These slits are rectangular slits formed in an array on the conductive film. In accordance with this configuration, the length of the straight line on the conductive film is interrupted by the slits, and thermal stress generated on the conductive film is interrupted by the slits. Thus, the thermal stress on the conductive film will not be excessively concentrated at one point, thereby preventing crack or flake-off from occurring on the conductive film.

Abstract: According to this invention, a semiconductor device has an upper surface on which an external connection electrode is formed and a lower surface which opposes the upper surface and is in a mirror surface state. A roughened region roughened by laser marking is formed at part of the lower surface. The roughened region includes a product information mark of the semiconductor device itself. The product information mark is printed by laser marking. The number, size, shape, and layout position of the roughened regions are decided to make it possible to, when the lower surface is irradiated with light, read the product information from the difference in light reflectance between the roughened region and mirror-finished region.

Abstract: For hermetic encapsulation of a component, which includes a chip with component structures applied on a substrate in a flip-chip construction, a material is applied onto the lower edge of the chip and regions of the substrate abutting the chip, and then a first continuous metal layer is applied on the back side of the chip and on the material, as well as on edge regions of the substrate abutting the material. For hermetic encapsulation, a second sealing metal layer is subsequently applied by a solvent-free process at least on those regions of the first metal layer that cover the material.

Abstract: An electrical component includes a substrate, a first integrated circuit attached to the substrate, a metal portion coupled to the first integrated circuit, and a second integrated circuit attached to the first integrated circuit. The metal portion is sandwiched between the first integrated circuit and the second integrated circuit.

Abstract: A high frequency circuit module for use in an automotive radar or the like, in which RF circuit parts are mounted on both sides of a hard multilayer dielectric substrate, and a transmission line connecting the RF circuit parts provided on both sides is constructed by a via group including a periodical structure or a via having a coaxial structure perpendicular to faces of the multilayer dielectric substrate. As the multilayer dielectric substrate, a hard multilayer substrate using metallic layers as a microstrip line wiring layer, a DC/IF signal line layer, and grounding metal layers for shielding which are disposed on and under the DC/IF signal line is employed. By using the transmission line achieved by a through via having the periodical structure or the through via having the coaxial structure, an electromagnetic wave propagating in parallel between the grounding conductors is confined.