STAIR STEP FORMATION USING AT LEAST TWO MASKS
Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
Latest MICRON TECHNOLOGY, INC. Patents:
- APPARATUSES AND METHODS FOR FORCING MEMORY CELL FAILURES IN A MEMORY DEVICE
- APPARATUSES AND METHODS FOR ADDRESS BASED MEMORY PERFORMANCE
- MEMORY ARRAY STRUCTURES AND METHODS OF THEIR FABRICATION
- FUSE LOGIC TO PERFORM SELECTIVELY ENABLED ECC DECODING
- LOW POWER CLOCK INJECTION DURING IDLE MODE OPERATIONS
The present disclosure relates generally to semiconductor memory apparatuses and methods of forming, and more particularly, to apparatuses and methods for stair step formation using at least two masks.
BACKGROUNDMemory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive memory, e.g., RRAM, and Flash memory, among others.
Memory devices are utilized as volatile and non-volatile data storage for a wide range of electronic applications. Flash memory typically uses a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, solid state drives (SSDs), digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices.
Memory devices can comprise memory arrays of memory cells, which can be arranged in various two or three dimensional configurations. Circuitry coupled to a memory array can be arranged in a substantially planar configuration, for instance. Interconnections are used to couple memory cells and associated circuitry.
Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area being less than the first exposed area. Conductive material is removed from the second exposed area. An initial length of the second mask is less than a length of the first exposed area and an initial width of the second mask is at least a width of the first exposed area plus a distance equal to a difference between the initial length of the second mask and a final length of the second mask after a stair step structure is formed.
In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure.
The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate various embodiments of the present disclosure and are not to be used in a limiting sense.
The terms “first,” “second,” “third,” and “fourth” may be used herein, and/or in the claims, merely for convenience in differentiating the nomenclature of various features from one another. The use of such terms does not necessarily imply that the materials are of different composition, but sometimes are used to distinguish between materials formed at different elevations, at different times, or in different manners, even if of the same composition. The use of such terms does not intend to convey a particular ordering of the features, including, but not limited to, an order of forming.
A first select gate 108, such as a drain select gate (SGD), can be arranged at a first end of a number of the vertical strings of series-coupled memory cells 103, and a second select gate 110, such as a source select gate (SGS), can be arranged at a second end, e.g., opposite end, of the vertical strings of series-coupled memory cells 103.
A plurality of data lines 102 can be oriented in a first plane, and further oriented in a first direction in the first plane, the vertical strings of series-coupled memory cells 103 being oriented orthogonal to the first plane. A plurality of access lines 105 can be oriented in a second plane, and further oriented in a second direction in the second plane.
As shown in
One or more source lines 104 can be oriented in a third plane, the third plane being substantially parallel to the first and second planes. The source lines 104 can be further oriented in the second direction, e.g., the same direction as the access lines 105 as shown in
The access lines 105 are coupled to (and in some cases from) control gates of memory cells at a particular level and can be used to select a particular one of the series-coupled memory cells within a vertical string. In this manner, a particular memory cell can be selected and electrically coupled to a data line 102 via operation of the first select gate 108, second select gate 110, and an access line 105. The access lines 105 can be configured to select a memory cell at a particular location within one or more of the vertical strings of series-coupled memory cells 103.
As can be observed in
For example,
A lower step can extend laterally a sufficient distance beyond a next higher step so that a vertical coupling can be made to the portion of the lower step extending laterally past the next higher step. In this manner, a vertical conductor 112 can be coupled to the lower step, such as to an access line 105, select gate 108 or 110, or source line 104, which each can correspond to a step in the stair step structure 106.
The memory array 100 can be coupled to various circuitry associated with operating the memory array 100. Such circuitry can include string driver circuitry, for instance. As an example, horizontal conductive lines 114 can be routed from the memory array 100, for example, to a string driver. Steps of the stair step structure 106 can be coupled to the conductive lines 114, e.g., via the vertical conductors 112. In this manner, an electrical coupling can be made between the vertical stack of access lines 105, select gates 108/110, and/or source lines 104, and the string driver, e.g., via the planar horizontal conductive lines 114.
The strings of NAND memory cells can be arranged with select gate transistors coupled at each end, e.g., source, drain. Each string can include a number of memory cells coupled in series, drain-to-source. Vertical strings of NAND memory cells can be arranged such that the string of series-coupled memory cells are linearly arranged in a vertical orientation, or can be arranged in non-linear configuration such as in a “U” shape, with portions of the “U” shape being oriented vertically, for example. That is, the string of series-coupled memory cells can be arranged in a dimension orthogonal to the planes encompassing the access lines, e.g., word lines, and data lines, e.g., bit lines.
The access lines 206, select gate 208 (SGD), and select gate 210 (SGS) of a memory array 200 can be coupled to respective global access lines 228 through selection transistors 218. The selection transistors 218 can be field effect transistors (FETs), for example. The selection transistors 218 can be controlled via the block high voltage switch output (BLKHVSW_OUT) signal line 226, which is coupled between an output of a block high voltage switch 220 and, for example, the gate of each of the selection transistors 218. The block high voltage switch 220 receives as inputs, for example, a block selection address 222 and an input voltage 224 to produce the BLKHVSW_OUT signal on the block high voltage switch output signal line 226 when appropriate to couple the access lines 206, select gate 208 (SGD), and select gate 210 (SGS) of memory array 200 to the global access lines 228.
In a sensing operation, such as a read or a program verify operation, global access line driver 216 provides positive voltage signals to global access lines 228, e.g., global word lines, to select a particular local access line coupled to memory cells being sensed. Unselected access lines, such as access lines not coupled to memory cells being read or verified, can be provided with a pass voltage (Vpass), while the selected access line can be provided with a read voltage. Other techniques are possible for reading and/or programming memory cells. According to various embodiments, the memory array 200 can be implemented as a 3D memory array with the strings being oriented vertically and the string driver 216, including the selection transistors 218, can be implemented as a substantially planar device, such as is shown in
Vertical conductors 312 are shown coupled to the various steps where a lower step extends beyond the step above the respective lower step. The vertical conductors 312 are coupled to horizontal conductive lines 314, which in turn are coupled to the substantially planar string driver 316, such as in the manner shown schematically in
A photo resist 430-1 is formed over the stack 409. As shown in
In this manner a stair step is formed of the select gate 408 material, insulating material 407-5, and access line 406-3 material, with respect to the rest of the materials of stack 409.
The material removal processes can be further repeated, each subsequent removal process utilizing a photo resist mask that is smaller by a stair step width associated with each respective location of stair step formation, e.g., each of left, right, front, and back edges. A stair step width can be 10 micro meters, for example.
The top view shown in
Therefore, while forming stair steps in one direction, e.g., the horizontal direction in
However, even with the reduction in size of the photo resist 530-2, the photo resist 530-2 still extends past the edges of the select gate 508 material at which stair step formation is not to occur, e.g., at the upper and lower edges of the select gate 508 material. This proportional over-extension of the photo resist beyond edges of the select gate 508 material at which stair step structure is not to be formed can be utilized where the photo resist is re-sized in place, such as by trimming or etch of the photo resist material.
As described above, the material removal processes can be further repeated, each one utilizing a photo resist that is smaller by a stair step width on each respective location of stair step formation, e.g., each of left and right edges, and optionally, smaller by a similar amount in the perpendicular direction.
The stair step structure shown in
According to various embodiments, the area mask 750A is formed over the stack of conductive and insulating materials with the opening therethrough so as to expose an area of the stacked materials, e.g., conductive material, in which a stair step structure is to be formed. In this manner, the area mask 750A can define a first exposed area of the stack of conductive materials, which is left exposed through opening 752A.
A photo resist mask can be formed over the opening 752A, extending to, or past, e.g., overlapping, the area mask 750A. According to some embodiments, the photo resist mask can formed of a material that has an etching rate greater than that of the area mask. According to various embodiments, the photo resist mask can be formed over a portion of the first exposed area of the conductive material. In this manner, the photo resist mask can define a second exposed area, the second exposed area being less than the first exposed area. For example, the second exposed area 746 is defined within opening 752A in part by photo resist mask 753.
According to various embodiments, the second exposed area is less than all of the first exposed area of the conductive material. For example, the photo resist mask can be formed first as shown at 753 for a first material removal process leaving areas 746 of the stack, e.g., conductive material, exposed and subject to material removal. Conductive material (and underlying insulating and/or conductive materials) in area 746 do not have portions of the area mask 750A or the photo resist mask, e.g., 753, formed thereover. As can be seen in
An initial width, e.g., in the vertical Y direction shown in
The amount of initial overlap can depend on how many stair steps comprise the stair step structure. According to some embodiments, the initial width of the photo resist mask can be at least the width of the area mask plus a product of a number of stair steps in the stair step structure times an amount by which the photo resist mask is resized to form one stair step. That is, if the photo resist mask is etched and/or trimmed all around a same distance between material removal to form respective stair steps, then in order to maintain some overlap, or at least abut an edge of the area mask for the last step formation so as not to allow unintended removal of material, the photo resist mask can be oversized with respect to the width of the area mask window by an amount per stair step times the quantity of stair steps.
According to a number of embodiments, the photo resist mask can initially overlap the portion of the area mask by an amount by which the photo resist mask is reduced to form a next stair step times a quantity of stair steps to be formed. For instance, a stair step structure involving two stair steps can be formed by two material removal processes, which typically only involves resizing the photo resist mask once. Therefore, the photo resist mask can initially overlap the area mask by the distance that the photo resist mask is reduced in size during one material removal process. A stair step structure involving three stair steps can be formed by using two photo resist mask resizings, e.g., 3−1=2. Therefore, the photo resist mask can initially overlap the area mask by the distance that the photo resist mask is reduced in size during two photo resist mask resizings.
As shown in
Subsequently, the initially-formed photo resist mask 753 can be re-sized, e.g. formed, to a smaller size and located at the position shown at dotted outline 754 for a second material removal process, re-sized to a smaller size and located at the position shown at dotted outline 755 for a third material removal process, re-sized to a smaller size and located at the position shown at dotted outline 756 for a fourth material removal process, and re-sized to a smaller size and located at the position shown at dotted outline 757 for a fifth material removal process. Only one of photo resist masks 753, 754, 755, 756, or 757 is formed over the opening 752A at a time. The photo resist masks 753, 754, 755, 756, or 757 can be centered over the opening 752A, i.e., centered in one direction over the opening 752A such that the two exposed areas 746 are of equal area, as shown in
The area mask 750A with opening 752A limits a stair step structure to be formed at only certain portions of a stack of materials, such as at one edge, two edges, or at only a portion of each of one or two edges, as is described with respect to
As shown in
Subsequently, the photo resist mask can be re-sized, e.g. formed, as shown at 754 for a second material removal process, re-sized as shown at 755 for a third material removal process, re-sized as shown at 756 for a fourth material removal process, and re-sized as shown at 757 for a fifth material removal process. The area mask 750B can remain in place, as shown, for all material removal processes. In this manner, a stair step structure can be formed within opening 752B, for example, at the right side of opening 752B.
A number of photo resist mask configurations can be used in conjunction with the area mask 868 to form a stair step structure involving the inner stack columns 863, in the location shown in
As can be observed in
The first material removal can include shortening a length of the at least one inner stack of columns to be less than a length of the two outer stacks of columns. Further material removal processes, e.g., etches, can be used to form the stair step structure at the shortened end of the at least one inner stack of columns, e.g., the end not aligned with the outer stacks of columns. Although not shown in
As will be appreciated from the foregoing illustrations and descriptions, an area mask can be used to define areas of the stack at which stair step structures are not to be formed. A photo resist mask can thereafter be used in different footprint configurations, e.g., shrinking, in areas not protected by the area mask to form one or more stair step structures. The area mask can have an opening therethrough such that the area mask is configured to cover some portion of a stack of conductive and/or insulating materials that is not to be etched in any material removal process used to form a stair step structure, and not cover another portion of the stack of conductive and/or insulating materials that is to be etched in a material removal process used to form a stair step structure. In this manner, stair step formation can be confined to only those areas in which stair steps are needed in a final configuration of the stack of conductive and/or insulating materials (as opposed to stair step structures being formed and subsequently removed).
Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of various embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.
In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.
Claims
1. A method for forming a memory structure, comprising:
- forming a first mask over a conductive material to define a first exposed area; and
- forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area; and
- removing conductive material from the second exposed area,
- wherein an initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
2. The method of claim 1, wherein the second mask is formed of a material that has an etching rate greater than that of the first mask.
3. The method of claim 1, wherein the first mask is a hard mask and the second mask is a photo resist mask.
4. The method of claim 1, further comprising resizing the second mask by an amount such that the second exposed area includes an additional area of at least one more stair step.
5. The method of claim 1, wherein the first dimension is a length, and the second dimension is a width.
6. The method of claim 5, wherein the initial width of the second mask is at least the width of the first exposed area plus a product of a number of stair steps in the stair step structure times an amount by which the width of the second mask is resized to form one stair step.
7. The method of claim 1, wherein forming the second mask over the portion of the first exposed area to define a second exposed area includes forming the second mask centered in one direction within the first exposed area such that the second exposed area has two portions of equal area on opposite ends of the first exposed area.
8. The method of claim 1, wherein forming the second mask over the portion of the first exposed area to define a second exposed area includes forming the second mask offset from center in one direction within the first exposed area such that the second exposed area is at one end of the first exposed area.
9. The method of claim 1, wherein forming the first mask includes forming an opening to define the first exposed area.
10. The method of claim 9, wherein forming the second mask includes forming the second mask completely across the opening in at least one dimension.
11. The method of claim 9, wherein forming the second mask includes forming the second mask to overlap the first mask on opposite edges of the opening.
12. The method of claim 9, wherein forming the opening comprises forming an opening having a non-square shape.
13. The method of claim 12, wherein forming the second mask includes forming the second mask to overlap the first mask at three of four edges of the non-square shape.
14. The method of claim 1, wherein the second exposed area includes two non-contiguous portions.
15. The method of claim 1, wherein the conductive material is a polysilicon material, the polysilicon material being arranged in a stack of materials that includes alternating polysilicon material and oxide material.
16. A method of forming a memory structure, comprising:
- forming a first mask over a stack of materials that includes alternating conductive materials and insulating materials, the first mask covering a first area of the stack of materials in which a stair step structure is not to be subsequently formed and not covering a second area of the stack of materials in which the stair step structure is to be subsequently formed;
- forming a second mask over a first portion of the second area and over a portion of the first mask; and
- removing some of the alternating conductive materials and insulating materials from a second portion of the second area not covered by the first mask or the second mask,
- wherein the second mask initially overlaps a dimension of the second area by at least an amount by which the second mask is reduced to form a next stair step times a quantity of stair steps to be formed.
17. The method of claim 16, wherein the second mask still overlaps a portion of the first mask after the last stair step is formed.
18. The method of claim 16, wherein after the last stair step is formed, the second mask still overlaps the dimension of the second area.
19. The method of claim 16, further comprising:
- reducing a size of the second mask by removing the amount from each side; and
- removing additional alternating conductive materials and insulating materials from a third portion of the second area not covered by the first mask or the second mask having the reduced size, the third portion including the second portion.
20. The method of claim 16, wherein forming the first mask includes forming the first mask over the first and second areas of the stack of materials; and
- forming an opening in the first mask over the second area.
21. The method of claim 16, wherein forming the second mask includes forming the second mask centered in one direction within the second area in which a stair step structure is to be formed.
22. A method of forming a memory structure, comprising:
- forming a plurality of stacks of columns of alternating conductive materials and insulating materials, the plurality of stacks of columns arranged side-by-side with at least one inner stack of columns being located between two outer stacks of columns;
- forming a first mask over the two outer stacks of columns and a first portion of the at least one inner stack of columns;
- forming a second mask over a portion of the first mask and a second portion of the at least one inner stack of columns not covered by the first mask; and
- removing a first amount of the alternating conductive materials and insulating materials of the at least one inner stack of columns not covered by the first mask or the second mask.
23. The method of claim 22, further comprising:
- re-sizing the second mask to cover less than the second portion of the at least one inner stack of columns not covered by the first mask; and
- removing a second amount of the alternating conductive materials and insulating materials of the at least one inner stack of columns not covered by the first mask or the second mask to form a stair step structure.
24. The method of claim 23, wherein removing the first amount includes shortening a length of the at least one inner stack of columns to be less than a length of the two outer stacks of columns.
25. The method of claim 24, wherein removing a second amount includes removing the second amount from an end of the at least one inner stack of columns from which the first amount was removed to shorten the length of the at least one inner stack of columns.
26. The method of claim 22, wherein forming a plurality of stacks of columns includes forming a plurality of inner stacks of columns located between the two outer stacks of columns.
27. A method of forming a memory structure, comprising:
- forming a plurality of alternating conductive materials and insulating materials;
- forming a first mask of hard mask material over the plurality of alternating conductive materials and insulating materials;
- patterning the first mask to have an area exposing the plurality of alternating conductive materials and insulating materials;
- forming a second mask over the first mask and the area exposing the plurality of alternating conductive materials and insulating materials;
- patterning the second mask to expose a first portion of the area exposing the plurality of alternating conductive materials and insulating materials; and
- removing a number of the plurality of alternating conductive materials and insulating materials in the first portion of the area exposing the plurality of alternating conductive materials and insulating materials to form at least one stair step,
- wherein the second mask is formed to overlap a dimension of the area exposing the plurality of alternating conductive materials and insulating materials by at least an amount by which the second mask is reduced in size during removing the number of the plurality of alternating conductive materials and insulating materials.
28. A memory, comprising:
- a vertical string of memory cells;
- horizontal conductive lines coupled to the memory cells, the horizontal conductive lines formed from a stack of alternating conductive having a stair step structure formed at only one edge of the stack; and
- a string driver coupled to the conductive lines via vertical conductors coupled to respective stair steps of the stair step structure.
29. The apparatus of claim 28, wherein the stack has the stair step structure formed on only a portion of the only one edge thereof.
30. The apparatus of claim 28, wherein the string of memory cells is arranged as a three dimensional NAND strings.
31. The apparatus of claim 28, wherein the stack of alternating conductive materials and insulating materials includes a plurality of stacks of columns of alternating conductive materials and insulating materials, the plurality of stacks of columns arranged side-by-side with at least one inner stack of columns being located between two outer stacks of columns,
- wherein the at least one inner stack of columns comprises the stair step structure.
32. The apparatus of claim 31, wherein the at least one inner stack of columns is of shorter length than the two outer stacks of columns.
33. The apparatus of claim 32, wherein the at least one inner stack of columns has a first end located in-line with and adjacent to first ends of the two outer stacks of columns, and the at least one inner stack of columns has a second end located not in line with second ends of the two outer stacks of columns, the stair step structure being formed at the second end of the at least one inner stack of columns.
Type: Application
Filed: Jul 6, 2012
Publication Date: Jan 9, 2014
Applicant: MICRON TECHNOLOGY, INC. (Boise, ID)
Inventors: Chang Wan Ha (San Ramon, CA), Graham R. Wolstenholme (Boise, ID), Deepak Thimmegowda (Boise, ID)
Application Number: 13/543,154
International Classification: H01L 21/308 (20060101); H01L 23/522 (20060101); H01L 21/283 (20060101);